1 /** 2 * \file 3 * 4 * \brief Component description for DAC 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMR34_DAC_COMPONENT_ 31 #define _SAMR34_DAC_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR DAC */ 35 /* ========================================================================== */ 36 /** \addtogroup SAMR34_DAC Digital-to-Analog Converter */ 37 /*@{*/ 38 39 #define DAC_U2244 40 #define REV_DAC 0x112 41 42 /* -------- DAC_CTRLA : (DAC Offset: 0x00) (R/W 8) Control A -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint8_t SWRST:1; /*!< bit: 0 Software Reset */ 47 uint8_t ENABLE:1; /*!< bit: 1 Enable DAC Controller */ 48 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 49 } bit; /*!< Structure used for bit access */ 50 uint8_t reg; /*!< Type used for register access */ 51 } DAC_CTRLA_Type; 52 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 53 54 #define DAC_CTRLA_OFFSET 0x00 /**< \brief (DAC_CTRLA offset) Control A */ 55 #define DAC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (DAC_CTRLA reset_value) Control A */ 56 57 #define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */ 58 #define DAC_CTRLA_SWRST (_U_(0x1) << DAC_CTRLA_SWRST_Pos) 59 #define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable DAC Controller */ 60 #define DAC_CTRLA_ENABLE (_U_(0x1) << DAC_CTRLA_ENABLE_Pos) 61 #define DAC_CTRLA_MASK _U_(0x03) /**< \brief (DAC_CTRLA) MASK Register */ 62 63 /* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W 8) Control B -------- */ 64 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 65 typedef union { 66 struct { 67 uint8_t DIFF:1; /*!< bit: 0 Differential mode enable */ 68 uint8_t REFSEL:2; /*!< bit: 1.. 2 Reference Selection for DAC0/1 */ 69 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 70 } bit; /*!< Structure used for bit access */ 71 uint8_t reg; /*!< Type used for register access */ 72 } DAC_CTRLB_Type; 73 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 74 75 #define DAC_CTRLB_OFFSET 0x01 /**< \brief (DAC_CTRLB offset) Control B */ 76 #define DAC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (DAC_CTRLB reset_value) Control B */ 77 78 #define DAC_CTRLB_DIFF_Pos 0 /**< \brief (DAC_CTRLB) Differential mode enable */ 79 #define DAC_CTRLB_DIFF (_U_(0x1) << DAC_CTRLB_DIFF_Pos) 80 #define DAC_CTRLB_REFSEL_Pos 1 /**< \brief (DAC_CTRLB) Reference Selection for DAC0/1 */ 81 #define DAC_CTRLB_REFSEL_Msk (_U_(0x3) << DAC_CTRLB_REFSEL_Pos) 82 #define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos)) 83 #define DAC_CTRLB_REFSEL_VREFPU_Val _U_(0x0) /**< \brief (DAC_CTRLB) External reference unbuffered */ 84 #define DAC_CTRLB_REFSEL_VDDANA_Val _U_(0x1) /**< \brief (DAC_CTRLB) Analog supply */ 85 #define DAC_CTRLB_REFSEL_VREFPB_Val _U_(0x2) /**< \brief (DAC_CTRLB) External reference buffered */ 86 #define DAC_CTRLB_REFSEL_INTREF_Val _U_(0x3) /**< \brief (DAC_CTRLB) Internal bandgap reference */ 87 #define DAC_CTRLB_REFSEL_VREFPU (DAC_CTRLB_REFSEL_VREFPU_Val << DAC_CTRLB_REFSEL_Pos) 88 #define DAC_CTRLB_REFSEL_VDDANA (DAC_CTRLB_REFSEL_VDDANA_Val << DAC_CTRLB_REFSEL_Pos) 89 #define DAC_CTRLB_REFSEL_VREFPB (DAC_CTRLB_REFSEL_VREFPB_Val << DAC_CTRLB_REFSEL_Pos) 90 #define DAC_CTRLB_REFSEL_INTREF (DAC_CTRLB_REFSEL_INTREF_Val << DAC_CTRLB_REFSEL_Pos) 91 #define DAC_CTRLB_MASK _U_(0x07) /**< \brief (DAC_CTRLB) MASK Register */ 92 93 /* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W 8) Event Control -------- */ 94 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 95 typedef union { 96 struct { 97 uint8_t STARTEI0:1; /*!< bit: 0 Start Conversion Event Input DAC 0 */ 98 uint8_t STARTEI1:1; /*!< bit: 1 Start Conversion Event Input DAC 1 */ 99 uint8_t EMPTYEO0:1; /*!< bit: 2 Data Buffer Empty Event Output DAC 0 */ 100 uint8_t EMPTYEO1:1; /*!< bit: 3 Data Buffer Empty Event Output DAC 1 */ 101 uint8_t INVEI0:1; /*!< bit: 4 Enable Invertion of DAC 0 input event */ 102 uint8_t INVEI1:1; /*!< bit: 5 Enable Invertion of DAC 1 input event */ 103 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 104 } bit; /*!< Structure used for bit access */ 105 struct { 106 uint8_t STARTEI:2; /*!< bit: 0.. 1 Start Conversion Event Input DAC x */ 107 uint8_t EMPTYEO:2; /*!< bit: 2.. 3 Data Buffer Empty Event Output DAC x */ 108 uint8_t INVEI:2; /*!< bit: 4.. 5 Enable Invertion of DAC x input event */ 109 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 110 } vec; /*!< Structure used for vec access */ 111 uint8_t reg; /*!< Type used for register access */ 112 } DAC_EVCTRL_Type; 113 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 114 115 #define DAC_EVCTRL_OFFSET 0x02 /**< \brief (DAC_EVCTRL offset) Event Control */ 116 #define DAC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_EVCTRL reset_value) Event Control */ 117 118 #define DAC_EVCTRL_STARTEI0_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 0 */ 119 #define DAC_EVCTRL_STARTEI0 (_U_(1) << DAC_EVCTRL_STARTEI0_Pos) 120 #define DAC_EVCTRL_STARTEI1_Pos 1 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 1 */ 121 #define DAC_EVCTRL_STARTEI1 (_U_(1) << DAC_EVCTRL_STARTEI1_Pos) 122 #define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC x */ 123 #define DAC_EVCTRL_STARTEI_Msk (_U_(0x3) << DAC_EVCTRL_STARTEI_Pos) 124 #define DAC_EVCTRL_STARTEI(value) (DAC_EVCTRL_STARTEI_Msk & ((value) << DAC_EVCTRL_STARTEI_Pos)) 125 #define DAC_EVCTRL_EMPTYEO0_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 0 */ 126 #define DAC_EVCTRL_EMPTYEO0 (_U_(1) << DAC_EVCTRL_EMPTYEO0_Pos) 127 #define DAC_EVCTRL_EMPTYEO1_Pos 3 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 1 */ 128 #define DAC_EVCTRL_EMPTYEO1 (_U_(1) << DAC_EVCTRL_EMPTYEO1_Pos) 129 #define DAC_EVCTRL_EMPTYEO_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC x */ 130 #define DAC_EVCTRL_EMPTYEO_Msk (_U_(0x3) << DAC_EVCTRL_EMPTYEO_Pos) 131 #define DAC_EVCTRL_EMPTYEO(value) (DAC_EVCTRL_EMPTYEO_Msk & ((value) << DAC_EVCTRL_EMPTYEO_Pos)) 132 #define DAC_EVCTRL_INVEI0_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 0 input event */ 133 #define DAC_EVCTRL_INVEI0 (_U_(1) << DAC_EVCTRL_INVEI0_Pos) 134 #define DAC_EVCTRL_INVEI1_Pos 5 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 1 input event */ 135 #define DAC_EVCTRL_INVEI1 (_U_(1) << DAC_EVCTRL_INVEI1_Pos) 136 #define DAC_EVCTRL_INVEI_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC x input event */ 137 #define DAC_EVCTRL_INVEI_Msk (_U_(0x3) << DAC_EVCTRL_INVEI_Pos) 138 #define DAC_EVCTRL_INVEI(value) (DAC_EVCTRL_INVEI_Msk & ((value) << DAC_EVCTRL_INVEI_Pos)) 139 #define DAC_EVCTRL_MASK _U_(0x3F) /**< \brief (DAC_EVCTRL) MASK Register */ 140 141 /* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ 142 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 143 typedef union { 144 struct { 145 uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun Interrupt Enable for DAC 0 */ 146 uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun Interrupt Enable for DAC 1 */ 147 uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */ 148 uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */ 149 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 150 } bit; /*!< Structure used for bit access */ 151 struct { 152 uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun Interrupt Enable for DAC x */ 153 uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */ 154 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 155 } vec; /*!< Structure used for vec access */ 156 uint8_t reg; /*!< Type used for register access */ 157 } DAC_INTENCLR_Type; 158 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 159 160 #define DAC_INTENCLR_OFFSET 0x04 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */ 161 #define DAC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */ 162 163 #define DAC_INTENCLR_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable for DAC 0 */ 164 #define DAC_INTENCLR_UNDERRUN0 (_U_(1) << DAC_INTENCLR_UNDERRUN0_Pos) 165 #define DAC_INTENCLR_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable for DAC 1 */ 166 #define DAC_INTENCLR_UNDERRUN1 (_U_(1) << DAC_INTENCLR_UNDERRUN1_Pos) 167 #define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable for DAC x */ 168 #define DAC_INTENCLR_UNDERRUN_Msk (_U_(0x3) << DAC_INTENCLR_UNDERRUN_Pos) 169 #define DAC_INTENCLR_UNDERRUN(value) (DAC_INTENCLR_UNDERRUN_Msk & ((value) << DAC_INTENCLR_UNDERRUN_Pos)) 170 #define DAC_INTENCLR_EMPTY0_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer 0 Empty Interrupt Enable */ 171 #define DAC_INTENCLR_EMPTY0 (_U_(1) << DAC_INTENCLR_EMPTY0_Pos) 172 #define DAC_INTENCLR_EMPTY1_Pos 3 /**< \brief (DAC_INTENCLR) Data Buffer 1 Empty Interrupt Enable */ 173 #define DAC_INTENCLR_EMPTY1 (_U_(1) << DAC_INTENCLR_EMPTY1_Pos) 174 #define DAC_INTENCLR_EMPTY_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer x Empty Interrupt Enable */ 175 #define DAC_INTENCLR_EMPTY_Msk (_U_(0x3) << DAC_INTENCLR_EMPTY_Pos) 176 #define DAC_INTENCLR_EMPTY(value) (DAC_INTENCLR_EMPTY_Msk & ((value) << DAC_INTENCLR_EMPTY_Pos)) 177 #define DAC_INTENCLR_MASK _U_(0x0F) /**< \brief (DAC_INTENCLR) MASK Register */ 178 179 /* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ 180 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 181 typedef union { 182 struct { 183 uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun Interrupt Enable for DAC 0 */ 184 uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun Interrupt Enable for DAC 1 */ 185 uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */ 186 uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */ 187 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 188 } bit; /*!< Structure used for bit access */ 189 struct { 190 uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun Interrupt Enable for DAC x */ 191 uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */ 192 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 193 } vec; /*!< Structure used for vec access */ 194 uint8_t reg; /*!< Type used for register access */ 195 } DAC_INTENSET_Type; 196 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 197 198 #define DAC_INTENSET_OFFSET 0x05 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */ 199 #define DAC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */ 200 201 #define DAC_INTENSET_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable for DAC 0 */ 202 #define DAC_INTENSET_UNDERRUN0 (_U_(1) << DAC_INTENSET_UNDERRUN0_Pos) 203 #define DAC_INTENSET_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable for DAC 1 */ 204 #define DAC_INTENSET_UNDERRUN1 (_U_(1) << DAC_INTENSET_UNDERRUN1_Pos) 205 #define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable for DAC x */ 206 #define DAC_INTENSET_UNDERRUN_Msk (_U_(0x3) << DAC_INTENSET_UNDERRUN_Pos) 207 #define DAC_INTENSET_UNDERRUN(value) (DAC_INTENSET_UNDERRUN_Msk & ((value) << DAC_INTENSET_UNDERRUN_Pos)) 208 #define DAC_INTENSET_EMPTY0_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer 0 Empty Interrupt Enable */ 209 #define DAC_INTENSET_EMPTY0 (_U_(1) << DAC_INTENSET_EMPTY0_Pos) 210 #define DAC_INTENSET_EMPTY1_Pos 3 /**< \brief (DAC_INTENSET) Data Buffer 1 Empty Interrupt Enable */ 211 #define DAC_INTENSET_EMPTY1 (_U_(1) << DAC_INTENSET_EMPTY1_Pos) 212 #define DAC_INTENSET_EMPTY_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer x Empty Interrupt Enable */ 213 #define DAC_INTENSET_EMPTY_Msk (_U_(0x3) << DAC_INTENSET_EMPTY_Pos) 214 #define DAC_INTENSET_EMPTY(value) (DAC_INTENSET_EMPTY_Msk & ((value) << DAC_INTENSET_EMPTY_Pos)) 215 #define DAC_INTENSET_MASK _U_(0x0F) /**< \brief (DAC_INTENSET) MASK Register */ 216 217 /* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ 218 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 219 typedef union { // __I to avoid read-modify-write on write-to-clear register 220 struct { 221 __I uint8_t UNDERRUN0:1; /*!< bit: 0 DAC 0 Underrun */ 222 __I uint8_t UNDERRUN1:1; /*!< bit: 1 DAC 1 Underrun */ 223 __I uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty */ 224 __I uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty */ 225 __I uint8_t :4; /*!< bit: 4.. 7 Reserved */ 226 } bit; /*!< Structure used for bit access */ 227 struct { 228 __I uint8_t UNDERRUN:2; /*!< bit: 0.. 1 DAC x Underrun */ 229 __I uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty */ 230 __I uint8_t :4; /*!< bit: 4.. 7 Reserved */ 231 } vec; /*!< Structure used for vec access */ 232 uint8_t reg; /*!< Type used for register access */ 233 } DAC_INTFLAG_Type; 234 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 235 236 #define DAC_INTFLAG_OFFSET 0x06 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */ 237 #define DAC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */ 238 239 #define DAC_INTFLAG_UNDERRUN0_Pos 0 /**< \brief (DAC_INTFLAG) DAC 0 Underrun */ 240 #define DAC_INTFLAG_UNDERRUN0 (_U_(1) << DAC_INTFLAG_UNDERRUN0_Pos) 241 #define DAC_INTFLAG_UNDERRUN1_Pos 1 /**< \brief (DAC_INTFLAG) DAC 1 Underrun */ 242 #define DAC_INTFLAG_UNDERRUN1 (_U_(1) << DAC_INTFLAG_UNDERRUN1_Pos) 243 #define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) DAC x Underrun */ 244 #define DAC_INTFLAG_UNDERRUN_Msk (_U_(0x3) << DAC_INTFLAG_UNDERRUN_Pos) 245 #define DAC_INTFLAG_UNDERRUN(value) (DAC_INTFLAG_UNDERRUN_Msk & ((value) << DAC_INTFLAG_UNDERRUN_Pos)) 246 #define DAC_INTFLAG_EMPTY0_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer 0 Empty */ 247 #define DAC_INTFLAG_EMPTY0 (_U_(1) << DAC_INTFLAG_EMPTY0_Pos) 248 #define DAC_INTFLAG_EMPTY1_Pos 3 /**< \brief (DAC_INTFLAG) Data Buffer 1 Empty */ 249 #define DAC_INTFLAG_EMPTY1 (_U_(1) << DAC_INTFLAG_EMPTY1_Pos) 250 #define DAC_INTFLAG_EMPTY_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer x Empty */ 251 #define DAC_INTFLAG_EMPTY_Msk (_U_(0x3) << DAC_INTFLAG_EMPTY_Pos) 252 #define DAC_INTFLAG_EMPTY(value) (DAC_INTFLAG_EMPTY_Msk & ((value) << DAC_INTFLAG_EMPTY_Pos)) 253 #define DAC_INTFLAG_MASK _U_(0x0F) /**< \brief (DAC_INTFLAG) MASK Register */ 254 255 /* -------- DAC_STATUS : (DAC Offset: 0x07) (R/ 8) Status -------- */ 256 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 257 typedef union { 258 struct { 259 uint8_t READY0:1; /*!< bit: 0 DAC 0 Startup Ready */ 260 uint8_t READY1:1; /*!< bit: 1 DAC 1 Startup Ready */ 261 uint8_t EOC0:1; /*!< bit: 2 DAC 0 End of Conversion */ 262 uint8_t EOC1:1; /*!< bit: 3 DAC 1 End of Conversion */ 263 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 264 } bit; /*!< Structure used for bit access */ 265 struct { 266 uint8_t READY:2; /*!< bit: 0.. 1 DAC x Startup Ready */ 267 uint8_t EOC:2; /*!< bit: 2.. 3 DAC x End of Conversion */ 268 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 269 } vec; /*!< Structure used for vec access */ 270 uint8_t reg; /*!< Type used for register access */ 271 } DAC_STATUS_Type; 272 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 273 274 #define DAC_STATUS_OFFSET 0x07 /**< \brief (DAC_STATUS offset) Status */ 275 #define DAC_STATUS_RESETVALUE _U_(0x00) /**< \brief (DAC_STATUS reset_value) Status */ 276 277 #define DAC_STATUS_READY0_Pos 0 /**< \brief (DAC_STATUS) DAC 0 Startup Ready */ 278 #define DAC_STATUS_READY0 (_U_(1) << DAC_STATUS_READY0_Pos) 279 #define DAC_STATUS_READY1_Pos 1 /**< \brief (DAC_STATUS) DAC 1 Startup Ready */ 280 #define DAC_STATUS_READY1 (_U_(1) << DAC_STATUS_READY1_Pos) 281 #define DAC_STATUS_READY_Pos 0 /**< \brief (DAC_STATUS) DAC x Startup Ready */ 282 #define DAC_STATUS_READY_Msk (_U_(0x3) << DAC_STATUS_READY_Pos) 283 #define DAC_STATUS_READY(value) (DAC_STATUS_READY_Msk & ((value) << DAC_STATUS_READY_Pos)) 284 #define DAC_STATUS_EOC0_Pos 2 /**< \brief (DAC_STATUS) DAC 0 End of Conversion */ 285 #define DAC_STATUS_EOC0 (_U_(1) << DAC_STATUS_EOC0_Pos) 286 #define DAC_STATUS_EOC1_Pos 3 /**< \brief (DAC_STATUS) DAC 1 End of Conversion */ 287 #define DAC_STATUS_EOC1 (_U_(1) << DAC_STATUS_EOC1_Pos) 288 #define DAC_STATUS_EOC_Pos 2 /**< \brief (DAC_STATUS) DAC x End of Conversion */ 289 #define DAC_STATUS_EOC_Msk (_U_(0x3) << DAC_STATUS_EOC_Pos) 290 #define DAC_STATUS_EOC(value) (DAC_STATUS_EOC_Msk & ((value) << DAC_STATUS_EOC_Pos)) 291 #define DAC_STATUS_MASK _U_(0x0F) /**< \brief (DAC_STATUS) MASK Register */ 292 293 /* -------- DAC_SYNCBUSY : (DAC Offset: 0x08) (R/ 32) Synchronization Busy -------- */ 294 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 295 typedef union { 296 struct { 297 uint32_t SWRST:1; /*!< bit: 0 Software Reset */ 298 uint32_t ENABLE:1; /*!< bit: 1 DAC Enable Status */ 299 uint32_t DATA0:1; /*!< bit: 2 Data DAC 0 */ 300 uint32_t DATA1:1; /*!< bit: 3 Data DAC 1 */ 301 uint32_t DATABUF0:1; /*!< bit: 4 Data Buffer DAC 0 */ 302 uint32_t DATABUF1:1; /*!< bit: 5 Data Buffer DAC 1 */ 303 uint32_t :26; /*!< bit: 6..31 Reserved */ 304 } bit; /*!< Structure used for bit access */ 305 struct { 306 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 307 uint32_t DATA:2; /*!< bit: 2.. 3 Data DAC x */ 308 uint32_t DATABUF:2; /*!< bit: 4.. 5 Data Buffer DAC x */ 309 uint32_t :26; /*!< bit: 6..31 Reserved */ 310 } vec; /*!< Structure used for vec access */ 311 uint32_t reg; /*!< Type used for register access */ 312 } DAC_SYNCBUSY_Type; 313 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 314 315 #define DAC_SYNCBUSY_OFFSET 0x08 /**< \brief (DAC_SYNCBUSY offset) Synchronization Busy */ 316 #define DAC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (DAC_SYNCBUSY reset_value) Synchronization Busy */ 317 318 #define DAC_SYNCBUSY_SWRST_Pos 0 /**< \brief (DAC_SYNCBUSY) Software Reset */ 319 #define DAC_SYNCBUSY_SWRST (_U_(0x1) << DAC_SYNCBUSY_SWRST_Pos) 320 #define DAC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (DAC_SYNCBUSY) DAC Enable Status */ 321 #define DAC_SYNCBUSY_ENABLE (_U_(0x1) << DAC_SYNCBUSY_ENABLE_Pos) 322 #define DAC_SYNCBUSY_DATA0_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC 0 */ 323 #define DAC_SYNCBUSY_DATA0 (_U_(1) << DAC_SYNCBUSY_DATA0_Pos) 324 #define DAC_SYNCBUSY_DATA1_Pos 3 /**< \brief (DAC_SYNCBUSY) Data DAC 1 */ 325 #define DAC_SYNCBUSY_DATA1 (_U_(1) << DAC_SYNCBUSY_DATA1_Pos) 326 #define DAC_SYNCBUSY_DATA_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC x */ 327 #define DAC_SYNCBUSY_DATA_Msk (_U_(0x3) << DAC_SYNCBUSY_DATA_Pos) 328 #define DAC_SYNCBUSY_DATA(value) (DAC_SYNCBUSY_DATA_Msk & ((value) << DAC_SYNCBUSY_DATA_Pos)) 329 #define DAC_SYNCBUSY_DATABUF0_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 0 */ 330 #define DAC_SYNCBUSY_DATABUF0 (_U_(1) << DAC_SYNCBUSY_DATABUF0_Pos) 331 #define DAC_SYNCBUSY_DATABUF1_Pos 5 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 1 */ 332 #define DAC_SYNCBUSY_DATABUF1 (_U_(1) << DAC_SYNCBUSY_DATABUF1_Pos) 333 #define DAC_SYNCBUSY_DATABUF_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC x */ 334 #define DAC_SYNCBUSY_DATABUF_Msk (_U_(0x3) << DAC_SYNCBUSY_DATABUF_Pos) 335 #define DAC_SYNCBUSY_DATABUF(value) (DAC_SYNCBUSY_DATABUF_Msk & ((value) << DAC_SYNCBUSY_DATABUF_Pos)) 336 #define DAC_SYNCBUSY_MASK _U_(0x0000003F) /**< \brief (DAC_SYNCBUSY) MASK Register */ 337 338 /* -------- DAC_DACCTRL : (DAC Offset: 0x0C) (R/W 16) DAC n Control -------- */ 339 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 340 typedef union { 341 struct { 342 uint16_t LEFTADJ:1; /*!< bit: 0 Left Adjusted Data */ 343 uint16_t ENABLE:1; /*!< bit: 1 Enable DAC0 */ 344 uint16_t CCTRL:2; /*!< bit: 2.. 3 Current Control */ 345 uint16_t :2; /*!< bit: 4.. 5 Reserved */ 346 uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ 347 uint16_t DITHER:1; /*!< bit: 7 Dithering Mode */ 348 uint16_t REFRESH:4; /*!< bit: 8..11 Refresh period */ 349 uint16_t :4; /*!< bit: 12..15 Reserved */ 350 } bit; /*!< Structure used for bit access */ 351 uint16_t reg; /*!< Type used for register access */ 352 } DAC_DACCTRL_Type; 353 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 354 355 #define DAC_DACCTRL_OFFSET 0x0C /**< \brief (DAC_DACCTRL offset) DAC n Control */ 356 #define DAC_DACCTRL_RESETVALUE _U_(0x0000) /**< \brief (DAC_DACCTRL reset_value) DAC n Control */ 357 358 #define DAC_DACCTRL_LEFTADJ_Pos 0 /**< \brief (DAC_DACCTRL) Left Adjusted Data */ 359 #define DAC_DACCTRL_LEFTADJ (_U_(0x1) << DAC_DACCTRL_LEFTADJ_Pos) 360 #define DAC_DACCTRL_ENABLE_Pos 1 /**< \brief (DAC_DACCTRL) Enable DAC0 */ 361 #define DAC_DACCTRL_ENABLE (_U_(0x1) << DAC_DACCTRL_ENABLE_Pos) 362 #define DAC_DACCTRL_CCTRL_Pos 2 /**< \brief (DAC_DACCTRL) Current Control */ 363 #define DAC_DACCTRL_CCTRL_Msk (_U_(0x3) << DAC_DACCTRL_CCTRL_Pos) 364 #define DAC_DACCTRL_CCTRL(value) (DAC_DACCTRL_CCTRL_Msk & ((value) << DAC_DACCTRL_CCTRL_Pos)) 365 #define DAC_DACCTRL_CCTRL_CC100K_Val _U_(0x0) /**< \brief (DAC_DACCTRL) GCLK_DAC <= 1.2MHz (100kSPS) */ 366 #define DAC_DACCTRL_CCTRL_CC1M_Val _U_(0x1) /**< \brief (DAC_DACCTRL) 1.2MHz < GCLK_DAC <= 6MHz (500kSPS) */ 367 #define DAC_DACCTRL_CCTRL_CC12M_Val _U_(0x2) /**< \brief (DAC_DACCTRL) 6MHz < GCLK_DAC <=12MHz (1MSPS) */ 368 #define DAC_DACCTRL_CCTRL_CC100K (DAC_DACCTRL_CCTRL_CC100K_Val << DAC_DACCTRL_CCTRL_Pos) 369 #define DAC_DACCTRL_CCTRL_CC1M (DAC_DACCTRL_CCTRL_CC1M_Val << DAC_DACCTRL_CCTRL_Pos) 370 #define DAC_DACCTRL_CCTRL_CC12M (DAC_DACCTRL_CCTRL_CC12M_Val << DAC_DACCTRL_CCTRL_Pos) 371 #define DAC_DACCTRL_RUNSTDBY_Pos 6 /**< \brief (DAC_DACCTRL) Run in Standby */ 372 #define DAC_DACCTRL_RUNSTDBY (_U_(0x1) << DAC_DACCTRL_RUNSTDBY_Pos) 373 #define DAC_DACCTRL_DITHER_Pos 7 /**< \brief (DAC_DACCTRL) Dithering Mode */ 374 #define DAC_DACCTRL_DITHER (_U_(0x1) << DAC_DACCTRL_DITHER_Pos) 375 #define DAC_DACCTRL_REFRESH_Pos 8 /**< \brief (DAC_DACCTRL) Refresh period */ 376 #define DAC_DACCTRL_REFRESH_Msk (_U_(0xF) << DAC_DACCTRL_REFRESH_Pos) 377 #define DAC_DACCTRL_REFRESH(value) (DAC_DACCTRL_REFRESH_Msk & ((value) << DAC_DACCTRL_REFRESH_Pos)) 378 #define DAC_DACCTRL_MASK _U_(0x0FCF) /**< \brief (DAC_DACCTRL) MASK Register */ 379 380 /* -------- DAC_DATA : (DAC Offset: 0x10) ( /W 16) DAC n Data -------- */ 381 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 382 typedef union { 383 struct { 384 uint16_t DATA:16; /*!< bit: 0..15 DAC0 Data */ 385 } bit; /*!< Structure used for bit access */ 386 uint16_t reg; /*!< Type used for register access */ 387 } DAC_DATA_Type; 388 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 389 390 #define DAC_DATA_OFFSET 0x10 /**< \brief (DAC_DATA offset) DAC n Data */ 391 #define DAC_DATA_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATA reset_value) DAC n Data */ 392 393 #define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) DAC0 Data */ 394 #define DAC_DATA_DATA_Msk (_U_(0xFFFF) << DAC_DATA_DATA_Pos) 395 #define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos)) 396 #define DAC_DATA_MASK _U_(0xFFFF) /**< \brief (DAC_DATA) MASK Register */ 397 398 /* -------- DAC_DATABUF : (DAC Offset: 0x14) ( /W 16) DAC n Data Buffer -------- */ 399 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 400 typedef union { 401 struct { 402 uint16_t DATABUF:16; /*!< bit: 0..15 DAC0 Data Buffer */ 403 } bit; /*!< Structure used for bit access */ 404 uint16_t reg; /*!< Type used for register access */ 405 } DAC_DATABUF_Type; 406 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 407 408 #define DAC_DATABUF_OFFSET 0x14 /**< \brief (DAC_DATABUF offset) DAC n Data Buffer */ 409 #define DAC_DATABUF_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATABUF reset_value) DAC n Data Buffer */ 410 411 #define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) DAC0 Data Buffer */ 412 #define DAC_DATABUF_DATABUF_Msk (_U_(0xFFFF) << DAC_DATABUF_DATABUF_Pos) 413 #define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos)) 414 #define DAC_DATABUF_MASK _U_(0xFFFF) /**< \brief (DAC_DATABUF) MASK Register */ 415 416 /* -------- DAC_DBGCTRL : (DAC Offset: 0x18) (R/W 8) Debug Control -------- */ 417 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 418 typedef union { 419 struct { 420 uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ 421 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 422 } bit; /*!< Structure used for bit access */ 423 uint8_t reg; /*!< Type used for register access */ 424 } DAC_DBGCTRL_Type; 425 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 426 427 #define DAC_DBGCTRL_OFFSET 0x18 /**< \brief (DAC_DBGCTRL offset) Debug Control */ 428 #define DAC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_DBGCTRL reset_value) Debug Control */ 429 430 #define DAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DAC_DBGCTRL) Debug Run */ 431 #define DAC_DBGCTRL_DBGRUN (_U_(0x1) << DAC_DBGCTRL_DBGRUN_Pos) 432 #define DAC_DBGCTRL_MASK _U_(0x01) /**< \brief (DAC_DBGCTRL) MASK Register */ 433 434 /** \brief DAC hardware registers */ 435 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 436 typedef struct { 437 __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ 438 __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 (R/W 8) Control B */ 439 __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 8) Event Control */ 440 RoReg8 Reserved1[0x1]; 441 __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ 442 __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ 443 __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ 444 __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x07 (R/ 8) Status */ 445 __I DAC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */ 446 __IO DAC_DACCTRL_Type DACCTRL[2]; /**< \brief Offset: 0x0C (R/W 16) DAC n Control */ 447 __O DAC_DATA_Type DATA[2]; /**< \brief Offset: 0x10 ( /W 16) DAC n Data */ 448 __O DAC_DATABUF_Type DATABUF[2]; /**< \brief Offset: 0x14 ( /W 16) DAC n Data Buffer */ 449 __IO DAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x18 (R/W 8) Debug Control */ 450 } Dac; 451 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 452 453 /*@}*/ 454 455 #endif /* _SAMR34_DAC_COMPONENT_ */ 456
