1 /** 2 * \file 3 * 4 * \brief Component description for TCC 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAMR21_TCC_COMPONENT_ 30 #define _SAMR21_TCC_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR TCC */ 34 /* ========================================================================== */ 35 /** \addtogroup SAMR21_TCC Timer Counter Control */ 36 /*@{*/ 37 38 #define TCC_U2213 39 #define REV_TCC 0x101 40 41 /* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t SWRST:1; /*!< bit: 0 Software Reset */ 46 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 47 uint32_t :3; /*!< bit: 2.. 4 Reserved */ 48 uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */ 49 uint32_t :1; /*!< bit: 7 Reserved */ 50 uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */ 51 uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */ 52 uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */ 53 uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */ 54 uint32_t :9; /*!< bit: 15..23 Reserved */ 55 uint32_t CPTEN0:1; /*!< bit: 24 Capture Channel 0 Enable */ 56 uint32_t CPTEN1:1; /*!< bit: 25 Capture Channel 1 Enable */ 57 uint32_t CPTEN2:1; /*!< bit: 26 Capture Channel 2 Enable */ 58 uint32_t CPTEN3:1; /*!< bit: 27 Capture Channel 3 Enable */ 59 uint32_t :4; /*!< bit: 28..31 Reserved */ 60 } bit; /*!< Structure used for bit access */ 61 struct { 62 uint32_t :24; /*!< bit: 0..23 Reserved */ 63 uint32_t CPTEN:4; /*!< bit: 24..27 Capture Channel x Enable */ 64 uint32_t :4; /*!< bit: 28..31 Reserved */ 65 } vec; /*!< Structure used for vec access */ 66 uint32_t reg; /*!< Type used for register access */ 67 } TCC_CTRLA_Type; 68 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 69 70 #define TCC_CTRLA_OFFSET 0x00 /**< \brief (TCC_CTRLA offset) Control A */ 71 #define TCC_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (TCC_CTRLA reset_value) Control A */ 72 73 #define TCC_CTRLA_SWRST_Pos 0 /**< \brief (TCC_CTRLA) Software Reset */ 74 #define TCC_CTRLA_SWRST (_U_(0x1) << TCC_CTRLA_SWRST_Pos) 75 #define TCC_CTRLA_ENABLE_Pos 1 /**< \brief (TCC_CTRLA) Enable */ 76 #define TCC_CTRLA_ENABLE (_U_(0x1) << TCC_CTRLA_ENABLE_Pos) 77 #define TCC_CTRLA_RESOLUTION_Pos 5 /**< \brief (TCC_CTRLA) Enhanced Resolution */ 78 #define TCC_CTRLA_RESOLUTION_Msk (_U_(0x3) << TCC_CTRLA_RESOLUTION_Pos) 79 #define TCC_CTRLA_RESOLUTION(value) (TCC_CTRLA_RESOLUTION_Msk & ((value) << TCC_CTRLA_RESOLUTION_Pos)) 80 #define TCC_CTRLA_RESOLUTION_NONE_Val _U_(0x0) /**< \brief (TCC_CTRLA) Dithering is disabled */ 81 #define TCC_CTRLA_RESOLUTION_DITH4_Val _U_(0x1) /**< \brief (TCC_CTRLA) Dithering is done every 16 PWM frames */ 82 #define TCC_CTRLA_RESOLUTION_DITH5_Val _U_(0x2) /**< \brief (TCC_CTRLA) Dithering is done every 32 PWM frames */ 83 #define TCC_CTRLA_RESOLUTION_DITH6_Val _U_(0x3) /**< \brief (TCC_CTRLA) Dithering is done every 64 PWM frames */ 84 #define TCC_CTRLA_RESOLUTION_NONE (TCC_CTRLA_RESOLUTION_NONE_Val << TCC_CTRLA_RESOLUTION_Pos) 85 #define TCC_CTRLA_RESOLUTION_DITH4 (TCC_CTRLA_RESOLUTION_DITH4_Val << TCC_CTRLA_RESOLUTION_Pos) 86 #define TCC_CTRLA_RESOLUTION_DITH5 (TCC_CTRLA_RESOLUTION_DITH5_Val << TCC_CTRLA_RESOLUTION_Pos) 87 #define TCC_CTRLA_RESOLUTION_DITH6 (TCC_CTRLA_RESOLUTION_DITH6_Val << TCC_CTRLA_RESOLUTION_Pos) 88 #define TCC_CTRLA_PRESCALER_Pos 8 /**< \brief (TCC_CTRLA) Prescaler */ 89 #define TCC_CTRLA_PRESCALER_Msk (_U_(0x7) << TCC_CTRLA_PRESCALER_Pos) 90 #define TCC_CTRLA_PRESCALER(value) (TCC_CTRLA_PRESCALER_Msk & ((value) << TCC_CTRLA_PRESCALER_Pos)) 91 #define TCC_CTRLA_PRESCALER_DIV1_Val _U_(0x0) /**< \brief (TCC_CTRLA) No division */ 92 #define TCC_CTRLA_PRESCALER_DIV2_Val _U_(0x1) /**< \brief (TCC_CTRLA) Divide by 2 */ 93 #define TCC_CTRLA_PRESCALER_DIV4_Val _U_(0x2) /**< \brief (TCC_CTRLA) Divide by 4 */ 94 #define TCC_CTRLA_PRESCALER_DIV8_Val _U_(0x3) /**< \brief (TCC_CTRLA) Divide by 8 */ 95 #define TCC_CTRLA_PRESCALER_DIV16_Val _U_(0x4) /**< \brief (TCC_CTRLA) Divide by 16 */ 96 #define TCC_CTRLA_PRESCALER_DIV64_Val _U_(0x5) /**< \brief (TCC_CTRLA) Divide by 64 */ 97 #define TCC_CTRLA_PRESCALER_DIV256_Val _U_(0x6) /**< \brief (TCC_CTRLA) Divide by 256 */ 98 #define TCC_CTRLA_PRESCALER_DIV1024_Val _U_(0x7) /**< \brief (TCC_CTRLA) Divide by 1024 */ 99 #define TCC_CTRLA_PRESCALER_DIV1 (TCC_CTRLA_PRESCALER_DIV1_Val << TCC_CTRLA_PRESCALER_Pos) 100 #define TCC_CTRLA_PRESCALER_DIV2 (TCC_CTRLA_PRESCALER_DIV2_Val << TCC_CTRLA_PRESCALER_Pos) 101 #define TCC_CTRLA_PRESCALER_DIV4 (TCC_CTRLA_PRESCALER_DIV4_Val << TCC_CTRLA_PRESCALER_Pos) 102 #define TCC_CTRLA_PRESCALER_DIV8 (TCC_CTRLA_PRESCALER_DIV8_Val << TCC_CTRLA_PRESCALER_Pos) 103 #define TCC_CTRLA_PRESCALER_DIV16 (TCC_CTRLA_PRESCALER_DIV16_Val << TCC_CTRLA_PRESCALER_Pos) 104 #define TCC_CTRLA_PRESCALER_DIV64 (TCC_CTRLA_PRESCALER_DIV64_Val << TCC_CTRLA_PRESCALER_Pos) 105 #define TCC_CTRLA_PRESCALER_DIV256 (TCC_CTRLA_PRESCALER_DIV256_Val << TCC_CTRLA_PRESCALER_Pos) 106 #define TCC_CTRLA_PRESCALER_DIV1024 (TCC_CTRLA_PRESCALER_DIV1024_Val << TCC_CTRLA_PRESCALER_Pos) 107 #define TCC_CTRLA_RUNSTDBY_Pos 11 /**< \brief (TCC_CTRLA) Run in Standby */ 108 #define TCC_CTRLA_RUNSTDBY (_U_(0x1) << TCC_CTRLA_RUNSTDBY_Pos) 109 #define TCC_CTRLA_PRESCSYNC_Pos 12 /**< \brief (TCC_CTRLA) Prescaler and Counter Synchronization Selection */ 110 #define TCC_CTRLA_PRESCSYNC_Msk (_U_(0x3) << TCC_CTRLA_PRESCSYNC_Pos) 111 #define TCC_CTRLA_PRESCSYNC(value) (TCC_CTRLA_PRESCSYNC_Msk & ((value) << TCC_CTRLA_PRESCSYNC_Pos)) 112 #define TCC_CTRLA_PRESCSYNC_GCLK_Val _U_(0x0) /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK */ 113 #define TCC_CTRLA_PRESCSYNC_PRESC_Val _U_(0x1) /**< \brief (TCC_CTRLA) Reload or reset counter on next prescaler clock */ 114 #define TCC_CTRLA_PRESCSYNC_RESYNC_Val _U_(0x2) /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK and reset prescaler counter */ 115 #define TCC_CTRLA_PRESCSYNC_GCLK (TCC_CTRLA_PRESCSYNC_GCLK_Val << TCC_CTRLA_PRESCSYNC_Pos) 116 #define TCC_CTRLA_PRESCSYNC_PRESC (TCC_CTRLA_PRESCSYNC_PRESC_Val << TCC_CTRLA_PRESCSYNC_Pos) 117 #define TCC_CTRLA_PRESCSYNC_RESYNC (TCC_CTRLA_PRESCSYNC_RESYNC_Val << TCC_CTRLA_PRESCSYNC_Pos) 118 #define TCC_CTRLA_ALOCK_Pos 14 /**< \brief (TCC_CTRLA) Auto Lock */ 119 #define TCC_CTRLA_ALOCK (_U_(0x1) << TCC_CTRLA_ALOCK_Pos) 120 #define TCC_CTRLA_CPTEN0_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel 0 Enable */ 121 #define TCC_CTRLA_CPTEN0 (1 << TCC_CTRLA_CPTEN0_Pos) 122 #define TCC_CTRLA_CPTEN1_Pos 25 /**< \brief (TCC_CTRLA) Capture Channel 1 Enable */ 123 #define TCC_CTRLA_CPTEN1 (1 << TCC_CTRLA_CPTEN1_Pos) 124 #define TCC_CTRLA_CPTEN2_Pos 26 /**< \brief (TCC_CTRLA) Capture Channel 2 Enable */ 125 #define TCC_CTRLA_CPTEN2 (1 << TCC_CTRLA_CPTEN2_Pos) 126 #define TCC_CTRLA_CPTEN3_Pos 27 /**< \brief (TCC_CTRLA) Capture Channel 3 Enable */ 127 #define TCC_CTRLA_CPTEN3 (1 << TCC_CTRLA_CPTEN3_Pos) 128 #define TCC_CTRLA_CPTEN_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel x Enable */ 129 #define TCC_CTRLA_CPTEN_Msk (_U_(0xF) << TCC_CTRLA_CPTEN_Pos) 130 #define TCC_CTRLA_CPTEN(value) (TCC_CTRLA_CPTEN_Msk & ((value) << TCC_CTRLA_CPTEN_Pos)) 131 #define TCC_CTRLA_MASK _U_(0x0F007F63) /**< \brief (TCC_CTRLA) MASK Register */ 132 133 /* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W 8) Control B Clear -------- */ 134 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 135 typedef union { 136 struct { 137 uint8_t DIR:1; /*!< bit: 0 Counter Direction */ 138 uint8_t LUPD:1; /*!< bit: 1 Lock Update */ 139 uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ 140 uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */ 141 uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */ 142 } bit; /*!< Structure used for bit access */ 143 uint8_t reg; /*!< Type used for register access */ 144 } TCC_CTRLBCLR_Type; 145 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 146 147 #define TCC_CTRLBCLR_OFFSET 0x04 /**< \brief (TCC_CTRLBCLR offset) Control B Clear */ 148 #define TCC_CTRLBCLR_RESETVALUE _U_(0x00) /**< \brief (TCC_CTRLBCLR reset_value) Control B Clear */ 149 150 #define TCC_CTRLBCLR_DIR_Pos 0 /**< \brief (TCC_CTRLBCLR) Counter Direction */ 151 #define TCC_CTRLBCLR_DIR (_U_(0x1) << TCC_CTRLBCLR_DIR_Pos) 152 #define TCC_CTRLBCLR_LUPD_Pos 1 /**< \brief (TCC_CTRLBCLR) Lock Update */ 153 #define TCC_CTRLBCLR_LUPD (_U_(0x1) << TCC_CTRLBCLR_LUPD_Pos) 154 #define TCC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TCC_CTRLBCLR) One-Shot */ 155 #define TCC_CTRLBCLR_ONESHOT (_U_(0x1) << TCC_CTRLBCLR_ONESHOT_Pos) 156 #define TCC_CTRLBCLR_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBCLR) Ramp Index Command */ 157 #define TCC_CTRLBCLR_IDXCMD_Msk (_U_(0x3) << TCC_CTRLBCLR_IDXCMD_Pos) 158 #define TCC_CTRLBCLR_IDXCMD(value) (TCC_CTRLBCLR_IDXCMD_Msk & ((value) << TCC_CTRLBCLR_IDXCMD_Pos)) 159 #define TCC_CTRLBCLR_IDXCMD_DISABLE_Val _U_(0x0) /**< \brief (TCC_CTRLBCLR) Command disabled: Index toggles between cycles A and B */ 160 #define TCC_CTRLBCLR_IDXCMD_SET_Val _U_(0x1) /**< \brief (TCC_CTRLBCLR) Set index: cycle B will be forced in the next cycle */ 161 #define TCC_CTRLBCLR_IDXCMD_CLEAR_Val _U_(0x2) /**< \brief (TCC_CTRLBCLR) Clear index: cycle A will be forced in the next cycle */ 162 #define TCC_CTRLBCLR_IDXCMD_HOLD_Val _U_(0x3) /**< \brief (TCC_CTRLBCLR) Hold index: the next cycle will be the same as the current cycle */ 163 #define TCC_CTRLBCLR_IDXCMD_DISABLE (TCC_CTRLBCLR_IDXCMD_DISABLE_Val << TCC_CTRLBCLR_IDXCMD_Pos) 164 #define TCC_CTRLBCLR_IDXCMD_SET (TCC_CTRLBCLR_IDXCMD_SET_Val << TCC_CTRLBCLR_IDXCMD_Pos) 165 #define TCC_CTRLBCLR_IDXCMD_CLEAR (TCC_CTRLBCLR_IDXCMD_CLEAR_Val << TCC_CTRLBCLR_IDXCMD_Pos) 166 #define TCC_CTRLBCLR_IDXCMD_HOLD (TCC_CTRLBCLR_IDXCMD_HOLD_Val << TCC_CTRLBCLR_IDXCMD_Pos) 167 #define TCC_CTRLBCLR_CMD_Pos 5 /**< \brief (TCC_CTRLBCLR) TCC Command */ 168 #define TCC_CTRLBCLR_CMD_Msk (_U_(0x7) << TCC_CTRLBCLR_CMD_Pos) 169 #define TCC_CTRLBCLR_CMD(value) (TCC_CTRLBCLR_CMD_Msk & ((value) << TCC_CTRLBCLR_CMD_Pos)) 170 #define TCC_CTRLBCLR_CMD_NONE_Val _U_(0x0) /**< \brief (TCC_CTRLBCLR) No action */ 171 #define TCC_CTRLBCLR_CMD_RETRIGGER_Val _U_(0x1) /**< \brief (TCC_CTRLBCLR) Clear start, restart or retrigger */ 172 #define TCC_CTRLBCLR_CMD_STOP_Val _U_(0x2) /**< \brief (TCC_CTRLBCLR) Force stop */ 173 #define TCC_CTRLBCLR_CMD_UPDATE_Val _U_(0x3) /**< \brief (TCC_CTRLBCLR) Force update of double buffered registers */ 174 #define TCC_CTRLBCLR_CMD_READSYNC_Val _U_(0x4) /**< \brief (TCC_CTRLBCLR) Force COUNT read synchronization */ 175 #define TCC_CTRLBCLR_CMD_NONE (TCC_CTRLBCLR_CMD_NONE_Val << TCC_CTRLBCLR_CMD_Pos) 176 #define TCC_CTRLBCLR_CMD_RETRIGGER (TCC_CTRLBCLR_CMD_RETRIGGER_Val << TCC_CTRLBCLR_CMD_Pos) 177 #define TCC_CTRLBCLR_CMD_STOP (TCC_CTRLBCLR_CMD_STOP_Val << TCC_CTRLBCLR_CMD_Pos) 178 #define TCC_CTRLBCLR_CMD_UPDATE (TCC_CTRLBCLR_CMD_UPDATE_Val << TCC_CTRLBCLR_CMD_Pos) 179 #define TCC_CTRLBCLR_CMD_READSYNC (TCC_CTRLBCLR_CMD_READSYNC_Val << TCC_CTRLBCLR_CMD_Pos) 180 #define TCC_CTRLBCLR_MASK _U_(0xFF) /**< \brief (TCC_CTRLBCLR) MASK Register */ 181 182 /* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W 8) Control B Set -------- */ 183 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 184 typedef union { 185 struct { 186 uint8_t DIR:1; /*!< bit: 0 Counter Direction */ 187 uint8_t LUPD:1; /*!< bit: 1 Lock Update */ 188 uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ 189 uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */ 190 uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */ 191 } bit; /*!< Structure used for bit access */ 192 uint8_t reg; /*!< Type used for register access */ 193 } TCC_CTRLBSET_Type; 194 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 195 196 #define TCC_CTRLBSET_OFFSET 0x05 /**< \brief (TCC_CTRLBSET offset) Control B Set */ 197 #define TCC_CTRLBSET_RESETVALUE _U_(0x00) /**< \brief (TCC_CTRLBSET reset_value) Control B Set */ 198 199 #define TCC_CTRLBSET_DIR_Pos 0 /**< \brief (TCC_CTRLBSET) Counter Direction */ 200 #define TCC_CTRLBSET_DIR (_U_(0x1) << TCC_CTRLBSET_DIR_Pos) 201 #define TCC_CTRLBSET_LUPD_Pos 1 /**< \brief (TCC_CTRLBSET) Lock Update */ 202 #define TCC_CTRLBSET_LUPD (_U_(0x1) << TCC_CTRLBSET_LUPD_Pos) 203 #define TCC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TCC_CTRLBSET) One-Shot */ 204 #define TCC_CTRLBSET_ONESHOT (_U_(0x1) << TCC_CTRLBSET_ONESHOT_Pos) 205 #define TCC_CTRLBSET_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBSET) Ramp Index Command */ 206 #define TCC_CTRLBSET_IDXCMD_Msk (_U_(0x3) << TCC_CTRLBSET_IDXCMD_Pos) 207 #define TCC_CTRLBSET_IDXCMD(value) (TCC_CTRLBSET_IDXCMD_Msk & ((value) << TCC_CTRLBSET_IDXCMD_Pos)) 208 #define TCC_CTRLBSET_IDXCMD_DISABLE_Val _U_(0x0) /**< \brief (TCC_CTRLBSET) Command disabled: Index toggles between cycles A and B */ 209 #define TCC_CTRLBSET_IDXCMD_SET_Val _U_(0x1) /**< \brief (TCC_CTRLBSET) Set index: cycle B will be forced in the next cycle */ 210 #define TCC_CTRLBSET_IDXCMD_CLEAR_Val _U_(0x2) /**< \brief (TCC_CTRLBSET) Clear index: cycle A will be forced in the next cycle */ 211 #define TCC_CTRLBSET_IDXCMD_HOLD_Val _U_(0x3) /**< \brief (TCC_CTRLBSET) Hold index: the next cycle will be the same as the current cycle */ 212 #define TCC_CTRLBSET_IDXCMD_DISABLE (TCC_CTRLBSET_IDXCMD_DISABLE_Val << TCC_CTRLBSET_IDXCMD_Pos) 213 #define TCC_CTRLBSET_IDXCMD_SET (TCC_CTRLBSET_IDXCMD_SET_Val << TCC_CTRLBSET_IDXCMD_Pos) 214 #define TCC_CTRLBSET_IDXCMD_CLEAR (TCC_CTRLBSET_IDXCMD_CLEAR_Val << TCC_CTRLBSET_IDXCMD_Pos) 215 #define TCC_CTRLBSET_IDXCMD_HOLD (TCC_CTRLBSET_IDXCMD_HOLD_Val << TCC_CTRLBSET_IDXCMD_Pos) 216 #define TCC_CTRLBSET_CMD_Pos 5 /**< \brief (TCC_CTRLBSET) TCC Command */ 217 #define TCC_CTRLBSET_CMD_Msk (_U_(0x7) << TCC_CTRLBSET_CMD_Pos) 218 #define TCC_CTRLBSET_CMD(value) (TCC_CTRLBSET_CMD_Msk & ((value) << TCC_CTRLBSET_CMD_Pos)) 219 #define TCC_CTRLBSET_CMD_NONE_Val _U_(0x0) /**< \brief (TCC_CTRLBSET) No action */ 220 #define TCC_CTRLBSET_CMD_RETRIGGER_Val _U_(0x1) /**< \brief (TCC_CTRLBSET) Clear start, restart or retrigger */ 221 #define TCC_CTRLBSET_CMD_STOP_Val _U_(0x2) /**< \brief (TCC_CTRLBSET) Force stop */ 222 #define TCC_CTRLBSET_CMD_UPDATE_Val _U_(0x3) /**< \brief (TCC_CTRLBSET) Force update of double buffered registers */ 223 #define TCC_CTRLBSET_CMD_READSYNC_Val _U_(0x4) /**< \brief (TCC_CTRLBSET) Force COUNT read synchronization */ 224 #define TCC_CTRLBSET_CMD_NONE (TCC_CTRLBSET_CMD_NONE_Val << TCC_CTRLBSET_CMD_Pos) 225 #define TCC_CTRLBSET_CMD_RETRIGGER (TCC_CTRLBSET_CMD_RETRIGGER_Val << TCC_CTRLBSET_CMD_Pos) 226 #define TCC_CTRLBSET_CMD_STOP (TCC_CTRLBSET_CMD_STOP_Val << TCC_CTRLBSET_CMD_Pos) 227 #define TCC_CTRLBSET_CMD_UPDATE (TCC_CTRLBSET_CMD_UPDATE_Val << TCC_CTRLBSET_CMD_Pos) 228 #define TCC_CTRLBSET_CMD_READSYNC (TCC_CTRLBSET_CMD_READSYNC_Val << TCC_CTRLBSET_CMD_Pos) 229 #define TCC_CTRLBSET_MASK _U_(0xFF) /**< \brief (TCC_CTRLBSET) MASK Register */ 230 231 /* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) (R/ 32) Synchronization Busy -------- */ 232 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 233 typedef union { 234 struct { 235 uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */ 236 uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */ 237 uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */ 238 uint32_t STATUS:1; /*!< bit: 3 Status Busy */ 239 uint32_t COUNT:1; /*!< bit: 4 Count Busy */ 240 uint32_t PATT:1; /*!< bit: 5 Pattern Busy */ 241 uint32_t WAVE:1; /*!< bit: 6 Wave Busy */ 242 uint32_t PER:1; /*!< bit: 7 Period busy */ 243 uint32_t CC0:1; /*!< bit: 8 Compare Channel 0 Busy */ 244 uint32_t CC1:1; /*!< bit: 9 Compare Channel 1 Busy */ 245 uint32_t CC2:1; /*!< bit: 10 Compare Channel 2 Busy */ 246 uint32_t CC3:1; /*!< bit: 11 Compare Channel 3 Busy */ 247 uint32_t :4; /*!< bit: 12..15 Reserved */ 248 uint32_t PATTB:1; /*!< bit: 16 Pattern Buffer Busy */ 249 uint32_t WAVEB:1; /*!< bit: 17 Wave Buffer Busy */ 250 uint32_t PERB:1; /*!< bit: 18 Period Buffer Busy */ 251 uint32_t CCB0:1; /*!< bit: 19 Compare Channel Buffer 0 Busy */ 252 uint32_t CCB1:1; /*!< bit: 20 Compare Channel Buffer 1 Busy */ 253 uint32_t CCB2:1; /*!< bit: 21 Compare Channel Buffer 2 Busy */ 254 uint32_t CCB3:1; /*!< bit: 22 Compare Channel Buffer 3 Busy */ 255 uint32_t :9; /*!< bit: 23..31 Reserved */ 256 } bit; /*!< Structure used for bit access */ 257 struct { 258 uint32_t :8; /*!< bit: 0.. 7 Reserved */ 259 uint32_t CC:4; /*!< bit: 8..11 Compare Channel x Busy */ 260 uint32_t :7; /*!< bit: 12..18 Reserved */ 261 uint32_t CCB:4; /*!< bit: 19..22 Compare Channel Buffer x Busy */ 262 uint32_t :9; /*!< bit: 23..31 Reserved */ 263 } vec; /*!< Structure used for vec access */ 264 uint32_t reg; /*!< Type used for register access */ 265 } TCC_SYNCBUSY_Type; 266 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 267 268 #define TCC_SYNCBUSY_OFFSET 0x08 /**< \brief (TCC_SYNCBUSY offset) Synchronization Busy */ 269 #define TCC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (TCC_SYNCBUSY reset_value) Synchronization Busy */ 270 271 #define TCC_SYNCBUSY_SWRST_Pos 0 /**< \brief (TCC_SYNCBUSY) Swrst Busy */ 272 #define TCC_SYNCBUSY_SWRST (_U_(0x1) << TCC_SYNCBUSY_SWRST_Pos) 273 #define TCC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (TCC_SYNCBUSY) Enable Busy */ 274 #define TCC_SYNCBUSY_ENABLE (_U_(0x1) << TCC_SYNCBUSY_ENABLE_Pos) 275 #define TCC_SYNCBUSY_CTRLB_Pos 2 /**< \brief (TCC_SYNCBUSY) Ctrlb Busy */ 276 #define TCC_SYNCBUSY_CTRLB (_U_(0x1) << TCC_SYNCBUSY_CTRLB_Pos) 277 #define TCC_SYNCBUSY_STATUS_Pos 3 /**< \brief (TCC_SYNCBUSY) Status Busy */ 278 #define TCC_SYNCBUSY_STATUS (_U_(0x1) << TCC_SYNCBUSY_STATUS_Pos) 279 #define TCC_SYNCBUSY_COUNT_Pos 4 /**< \brief (TCC_SYNCBUSY) Count Busy */ 280 #define TCC_SYNCBUSY_COUNT (_U_(0x1) << TCC_SYNCBUSY_COUNT_Pos) 281 #define TCC_SYNCBUSY_PATT_Pos 5 /**< \brief (TCC_SYNCBUSY) Pattern Busy */ 282 #define TCC_SYNCBUSY_PATT (_U_(0x1) << TCC_SYNCBUSY_PATT_Pos) 283 #define TCC_SYNCBUSY_WAVE_Pos 6 /**< \brief (TCC_SYNCBUSY) Wave Busy */ 284 #define TCC_SYNCBUSY_WAVE (_U_(0x1) << TCC_SYNCBUSY_WAVE_Pos) 285 #define TCC_SYNCBUSY_PER_Pos 7 /**< \brief (TCC_SYNCBUSY) Period busy */ 286 #define TCC_SYNCBUSY_PER (_U_(0x1) << TCC_SYNCBUSY_PER_Pos) 287 #define TCC_SYNCBUSY_CC0_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel 0 Busy */ 288 #define TCC_SYNCBUSY_CC0 (1 << TCC_SYNCBUSY_CC0_Pos) 289 #define TCC_SYNCBUSY_CC1_Pos 9 /**< \brief (TCC_SYNCBUSY) Compare Channel 1 Busy */ 290 #define TCC_SYNCBUSY_CC1 (1 << TCC_SYNCBUSY_CC1_Pos) 291 #define TCC_SYNCBUSY_CC2_Pos 10 /**< \brief (TCC_SYNCBUSY) Compare Channel 2 Busy */ 292 #define TCC_SYNCBUSY_CC2 (1 << TCC_SYNCBUSY_CC2_Pos) 293 #define TCC_SYNCBUSY_CC3_Pos 11 /**< \brief (TCC_SYNCBUSY) Compare Channel 3 Busy */ 294 #define TCC_SYNCBUSY_CC3 (1 << TCC_SYNCBUSY_CC3_Pos) 295 #define TCC_SYNCBUSY_CC_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel x Busy */ 296 #define TCC_SYNCBUSY_CC_Msk (_U_(0xF) << TCC_SYNCBUSY_CC_Pos) 297 #define TCC_SYNCBUSY_CC(value) (TCC_SYNCBUSY_CC_Msk & ((value) << TCC_SYNCBUSY_CC_Pos)) 298 #define TCC_SYNCBUSY_PATTB_Pos 16 /**< \brief (TCC_SYNCBUSY) Pattern Buffer Busy */ 299 #define TCC_SYNCBUSY_PATTB (_U_(0x1) << TCC_SYNCBUSY_PATTB_Pos) 300 #define TCC_SYNCBUSY_WAVEB_Pos 17 /**< \brief (TCC_SYNCBUSY) Wave Buffer Busy */ 301 #define TCC_SYNCBUSY_WAVEB (_U_(0x1) << TCC_SYNCBUSY_WAVEB_Pos) 302 #define TCC_SYNCBUSY_PERB_Pos 18 /**< \brief (TCC_SYNCBUSY) Period Buffer Busy */ 303 #define TCC_SYNCBUSY_PERB (_U_(0x1) << TCC_SYNCBUSY_PERB_Pos) 304 #define TCC_SYNCBUSY_CCB0_Pos 19 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 0 Busy */ 305 #define TCC_SYNCBUSY_CCB0 (1 << TCC_SYNCBUSY_CCB0_Pos) 306 #define TCC_SYNCBUSY_CCB1_Pos 20 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 1 Busy */ 307 #define TCC_SYNCBUSY_CCB1 (1 << TCC_SYNCBUSY_CCB1_Pos) 308 #define TCC_SYNCBUSY_CCB2_Pos 21 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 2 Busy */ 309 #define TCC_SYNCBUSY_CCB2 (1 << TCC_SYNCBUSY_CCB2_Pos) 310 #define TCC_SYNCBUSY_CCB3_Pos 22 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer 3 Busy */ 311 #define TCC_SYNCBUSY_CCB3 (1 << TCC_SYNCBUSY_CCB3_Pos) 312 #define TCC_SYNCBUSY_CCB_Pos 19 /**< \brief (TCC_SYNCBUSY) Compare Channel Buffer x Busy */ 313 #define TCC_SYNCBUSY_CCB_Msk (_U_(0xF) << TCC_SYNCBUSY_CCB_Pos) 314 #define TCC_SYNCBUSY_CCB(value) (TCC_SYNCBUSY_CCB_Msk & ((value) << TCC_SYNCBUSY_CCB_Pos)) 315 #define TCC_SYNCBUSY_MASK _U_(0x007F0FFF) /**< \brief (TCC_SYNCBUSY) MASK Register */ 316 317 /* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */ 318 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 319 typedef union { 320 struct { 321 uint32_t SRC:2; /*!< bit: 0.. 1 Fault A Source */ 322 uint32_t :1; /*!< bit: 2 Reserved */ 323 uint32_t KEEP:1; /*!< bit: 3 Fault A Keeper */ 324 uint32_t QUAL:1; /*!< bit: 4 Fault A Qualification */ 325 uint32_t BLANK:2; /*!< bit: 5.. 6 Fault A Blanking Mode */ 326 uint32_t RESTART:1; /*!< bit: 7 Fault A Restart */ 327 uint32_t HALT:2; /*!< bit: 8.. 9 Fault A Halt Mode */ 328 uint32_t CHSEL:2; /*!< bit: 10..11 Fault A Capture Channel */ 329 uint32_t CAPTURE:3; /*!< bit: 12..14 Fault A Capture Action */ 330 uint32_t :1; /*!< bit: 15 Reserved */ 331 uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault A Blanking Time */ 332 uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault A Filter Value */ 333 uint32_t :4; /*!< bit: 28..31 Reserved */ 334 } bit; /*!< Structure used for bit access */ 335 uint32_t reg; /*!< Type used for register access */ 336 } TCC_FCTRLA_Type; 337 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 338 339 #define TCC_FCTRLA_OFFSET 0x0C /**< \brief (TCC_FCTRLA offset) Recoverable Fault A Configuration */ 340 #define TCC_FCTRLA_RESETVALUE _U_(0x00000000) /**< \brief (TCC_FCTRLA reset_value) Recoverable Fault A Configuration */ 341 342 #define TCC_FCTRLA_SRC_Pos 0 /**< \brief (TCC_FCTRLA) Fault A Source */ 343 #define TCC_FCTRLA_SRC_Msk (_U_(0x3) << TCC_FCTRLA_SRC_Pos) 344 #define TCC_FCTRLA_SRC(value) (TCC_FCTRLA_SRC_Msk & ((value) << TCC_FCTRLA_SRC_Pos)) 345 #define TCC_FCTRLA_SRC_DISABLE_Val _U_(0x0) /**< \brief (TCC_FCTRLA) Fault input disabled */ 346 #define TCC_FCTRLA_SRC_ENABLE_Val _U_(0x1) /**< \brief (TCC_FCTRLA) MCEx (x=0,1) event input */ 347 #define TCC_FCTRLA_SRC_INVERT_Val _U_(0x2) /**< \brief (TCC_FCTRLA) Inverted MCEx (x=0,1) event input */ 348 #define TCC_FCTRLA_SRC_ALTFAULT_Val _U_(0x3) /**< \brief (TCC_FCTRLA) Alternate fault (A or B) state at the end of the previous period */ 349 #define TCC_FCTRLA_SRC_DISABLE (TCC_FCTRLA_SRC_DISABLE_Val << TCC_FCTRLA_SRC_Pos) 350 #define TCC_FCTRLA_SRC_ENABLE (TCC_FCTRLA_SRC_ENABLE_Val << TCC_FCTRLA_SRC_Pos) 351 #define TCC_FCTRLA_SRC_INVERT (TCC_FCTRLA_SRC_INVERT_Val << TCC_FCTRLA_SRC_Pos) 352 #define TCC_FCTRLA_SRC_ALTFAULT (TCC_FCTRLA_SRC_ALTFAULT_Val << TCC_FCTRLA_SRC_Pos) 353 #define TCC_FCTRLA_KEEP_Pos 3 /**< \brief (TCC_FCTRLA) Fault A Keeper */ 354 #define TCC_FCTRLA_KEEP (_U_(0x1) << TCC_FCTRLA_KEEP_Pos) 355 #define TCC_FCTRLA_QUAL_Pos 4 /**< \brief (TCC_FCTRLA) Fault A Qualification */ 356 #define TCC_FCTRLA_QUAL (_U_(0x1) << TCC_FCTRLA_QUAL_Pos) 357 #define TCC_FCTRLA_BLANK_Pos 5 /**< \brief (TCC_FCTRLA) Fault A Blanking Mode */ 358 #define TCC_FCTRLA_BLANK_Msk (_U_(0x3) << TCC_FCTRLA_BLANK_Pos) 359 #define TCC_FCTRLA_BLANK(value) (TCC_FCTRLA_BLANK_Msk & ((value) << TCC_FCTRLA_BLANK_Pos)) 360 #define TCC_FCTRLA_BLANK_NONE_Val _U_(0x0) /**< \brief (TCC_FCTRLA) No blanking applied */ 361 #define TCC_FCTRLA_BLANK_RISE_Val _U_(0x1) /**< \brief (TCC_FCTRLA) Blanking applied from rising edge of the output waveform */ 362 #define TCC_FCTRLA_BLANK_FALL_Val _U_(0x2) /**< \brief (TCC_FCTRLA) Blanking applied from falling edge of the output waveform */ 363 #define TCC_FCTRLA_BLANK_BOTH_Val _U_(0x3) /**< \brief (TCC_FCTRLA) Blanking applied from each toggle of the output waveform */ 364 #define TCC_FCTRLA_BLANK_NONE (TCC_FCTRLA_BLANK_NONE_Val << TCC_FCTRLA_BLANK_Pos) 365 #define TCC_FCTRLA_BLANK_RISE (TCC_FCTRLA_BLANK_RISE_Val << TCC_FCTRLA_BLANK_Pos) 366 #define TCC_FCTRLA_BLANK_FALL (TCC_FCTRLA_BLANK_FALL_Val << TCC_FCTRLA_BLANK_Pos) 367 #define TCC_FCTRLA_BLANK_BOTH (TCC_FCTRLA_BLANK_BOTH_Val << TCC_FCTRLA_BLANK_Pos) 368 #define TCC_FCTRLA_RESTART_Pos 7 /**< \brief (TCC_FCTRLA) Fault A Restart */ 369 #define TCC_FCTRLA_RESTART (_U_(0x1) << TCC_FCTRLA_RESTART_Pos) 370 #define TCC_FCTRLA_HALT_Pos 8 /**< \brief (TCC_FCTRLA) Fault A Halt Mode */ 371 #define TCC_FCTRLA_HALT_Msk (_U_(0x3) << TCC_FCTRLA_HALT_Pos) 372 #define TCC_FCTRLA_HALT(value) (TCC_FCTRLA_HALT_Msk & ((value) << TCC_FCTRLA_HALT_Pos)) 373 #define TCC_FCTRLA_HALT_DISABLE_Val _U_(0x0) /**< \brief (TCC_FCTRLA) Halt action disabled */ 374 #define TCC_FCTRLA_HALT_HW_Val _U_(0x1) /**< \brief (TCC_FCTRLA) Hardware halt action */ 375 #define TCC_FCTRLA_HALT_SW_Val _U_(0x2) /**< \brief (TCC_FCTRLA) Software halt action */ 376 #define TCC_FCTRLA_HALT_NR_Val _U_(0x3) /**< \brief (TCC_FCTRLA) Non-recoverable fault */ 377 #define TCC_FCTRLA_HALT_DISABLE (TCC_FCTRLA_HALT_DISABLE_Val << TCC_FCTRLA_HALT_Pos) 378 #define TCC_FCTRLA_HALT_HW (TCC_FCTRLA_HALT_HW_Val << TCC_FCTRLA_HALT_Pos) 379 #define TCC_FCTRLA_HALT_SW (TCC_FCTRLA_HALT_SW_Val << TCC_FCTRLA_HALT_Pos) 380 #define TCC_FCTRLA_HALT_NR (TCC_FCTRLA_HALT_NR_Val << TCC_FCTRLA_HALT_Pos) 381 #define TCC_FCTRLA_CHSEL_Pos 10 /**< \brief (TCC_FCTRLA) Fault A Capture Channel */ 382 #define TCC_FCTRLA_CHSEL_Msk (_U_(0x3) << TCC_FCTRLA_CHSEL_Pos) 383 #define TCC_FCTRLA_CHSEL(value) (TCC_FCTRLA_CHSEL_Msk & ((value) << TCC_FCTRLA_CHSEL_Pos)) 384 #define TCC_FCTRLA_CHSEL_CC0_Val _U_(0x0) /**< \brief (TCC_FCTRLA) Capture value stored in channel 0 */ 385 #define TCC_FCTRLA_CHSEL_CC1_Val _U_(0x1) /**< \brief (TCC_FCTRLA) Capture value stored in channel 1 */ 386 #define TCC_FCTRLA_CHSEL_CC2_Val _U_(0x2) /**< \brief (TCC_FCTRLA) Capture value stored in channel 2 */ 387 #define TCC_FCTRLA_CHSEL_CC3_Val _U_(0x3) /**< \brief (TCC_FCTRLA) Capture value stored in channel 3 */ 388 #define TCC_FCTRLA_CHSEL_CC0 (TCC_FCTRLA_CHSEL_CC0_Val << TCC_FCTRLA_CHSEL_Pos) 389 #define TCC_FCTRLA_CHSEL_CC1 (TCC_FCTRLA_CHSEL_CC1_Val << TCC_FCTRLA_CHSEL_Pos) 390 #define TCC_FCTRLA_CHSEL_CC2 (TCC_FCTRLA_CHSEL_CC2_Val << TCC_FCTRLA_CHSEL_Pos) 391 #define TCC_FCTRLA_CHSEL_CC3 (TCC_FCTRLA_CHSEL_CC3_Val << TCC_FCTRLA_CHSEL_Pos) 392 #define TCC_FCTRLA_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLA) Fault A Capture Action */ 393 #define TCC_FCTRLA_CAPTURE_Msk (_U_(0x7) << TCC_FCTRLA_CAPTURE_Pos) 394 #define TCC_FCTRLA_CAPTURE(value) (TCC_FCTRLA_CAPTURE_Msk & ((value) << TCC_FCTRLA_CAPTURE_Pos)) 395 #define TCC_FCTRLA_CAPTURE_DISABLE_Val _U_(0x0) /**< \brief (TCC_FCTRLA) No capture */ 396 #define TCC_FCTRLA_CAPTURE_CAPT_Val _U_(0x1) /**< \brief (TCC_FCTRLA) Capture on fault */ 397 #define TCC_FCTRLA_CAPTURE_CAPTMIN_Val _U_(0x2) /**< \brief (TCC_FCTRLA) Minimum capture */ 398 #define TCC_FCTRLA_CAPTURE_CAPTMAX_Val _U_(0x3) /**< \brief (TCC_FCTRLA) Maximum capture */ 399 #define TCC_FCTRLA_CAPTURE_LOCMIN_Val _U_(0x4) /**< \brief (TCC_FCTRLA) Minimum local detection */ 400 #define TCC_FCTRLA_CAPTURE_LOCMAX_Val _U_(0x5) /**< \brief (TCC_FCTRLA) Maximum local detection */ 401 #define TCC_FCTRLA_CAPTURE_DERIV0_Val _U_(0x6) /**< \brief (TCC_FCTRLA) Minimum and maximum local detection */ 402 #define TCC_FCTRLA_CAPTURE_DISABLE (TCC_FCTRLA_CAPTURE_DISABLE_Val << TCC_FCTRLA_CAPTURE_Pos) 403 #define TCC_FCTRLA_CAPTURE_CAPT (TCC_FCTRLA_CAPTURE_CAPT_Val << TCC_FCTRLA_CAPTURE_Pos) 404 #define TCC_FCTRLA_CAPTURE_CAPTMIN (TCC_FCTRLA_CAPTURE_CAPTMIN_Val << TCC_FCTRLA_CAPTURE_Pos) 405 #define TCC_FCTRLA_CAPTURE_CAPTMAX (TCC_FCTRLA_CAPTURE_CAPTMAX_Val << TCC_FCTRLA_CAPTURE_Pos) 406 #define TCC_FCTRLA_CAPTURE_LOCMIN (TCC_FCTRLA_CAPTURE_LOCMIN_Val << TCC_FCTRLA_CAPTURE_Pos) 407 #define TCC_FCTRLA_CAPTURE_LOCMAX (TCC_FCTRLA_CAPTURE_LOCMAX_Val << TCC_FCTRLA_CAPTURE_Pos) 408 #define TCC_FCTRLA_CAPTURE_DERIV0 (TCC_FCTRLA_CAPTURE_DERIV0_Val << TCC_FCTRLA_CAPTURE_Pos) 409 #define TCC_FCTRLA_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLA) Fault A Blanking Time */ 410 #define TCC_FCTRLA_BLANKVAL_Msk (_U_(0xFF) << TCC_FCTRLA_BLANKVAL_Pos) 411 #define TCC_FCTRLA_BLANKVAL(value) (TCC_FCTRLA_BLANKVAL_Msk & ((value) << TCC_FCTRLA_BLANKVAL_Pos)) 412 #define TCC_FCTRLA_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLA) Fault A Filter Value */ 413 #define TCC_FCTRLA_FILTERVAL_Msk (_U_(0xF) << TCC_FCTRLA_FILTERVAL_Pos) 414 #define TCC_FCTRLA_FILTERVAL(value) (TCC_FCTRLA_FILTERVAL_Msk & ((value) << TCC_FCTRLA_FILTERVAL_Pos)) 415 #define TCC_FCTRLA_MASK _U_(0x0FFF7FFB) /**< \brief (TCC_FCTRLA) MASK Register */ 416 417 /* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */ 418 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 419 typedef union { 420 struct { 421 uint32_t SRC:2; /*!< bit: 0.. 1 Fault B Source */ 422 uint32_t :1; /*!< bit: 2 Reserved */ 423 uint32_t KEEP:1; /*!< bit: 3 Fault B Keeper */ 424 uint32_t QUAL:1; /*!< bit: 4 Fault B Qualification */ 425 uint32_t BLANK:2; /*!< bit: 5.. 6 Fault B Blanking Mode */ 426 uint32_t RESTART:1; /*!< bit: 7 Fault B Restart */ 427 uint32_t HALT:2; /*!< bit: 8.. 9 Fault B Halt Mode */ 428 uint32_t CHSEL:2; /*!< bit: 10..11 Fault B Capture Channel */ 429 uint32_t CAPTURE:3; /*!< bit: 12..14 Fault B Capture Action */ 430 uint32_t :1; /*!< bit: 15 Reserved */ 431 uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault B Blanking Time */ 432 uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault B Filter Value */ 433 uint32_t :4; /*!< bit: 28..31 Reserved */ 434 } bit; /*!< Structure used for bit access */ 435 uint32_t reg; /*!< Type used for register access */ 436 } TCC_FCTRLB_Type; 437 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 438 439 #define TCC_FCTRLB_OFFSET 0x10 /**< \brief (TCC_FCTRLB offset) Recoverable Fault B Configuration */ 440 #define TCC_FCTRLB_RESETVALUE _U_(0x00000000) /**< \brief (TCC_FCTRLB reset_value) Recoverable Fault B Configuration */ 441 442 #define TCC_FCTRLB_SRC_Pos 0 /**< \brief (TCC_FCTRLB) Fault B Source */ 443 #define TCC_FCTRLB_SRC_Msk (_U_(0x3) << TCC_FCTRLB_SRC_Pos) 444 #define TCC_FCTRLB_SRC(value) (TCC_FCTRLB_SRC_Msk & ((value) << TCC_FCTRLB_SRC_Pos)) 445 #define TCC_FCTRLB_SRC_DISABLE_Val _U_(0x0) /**< \brief (TCC_FCTRLB) Fault input disabled */ 446 #define TCC_FCTRLB_SRC_ENABLE_Val _U_(0x1) /**< \brief (TCC_FCTRLB) MCEx (x=0,1) event input */ 447 #define TCC_FCTRLB_SRC_INVERT_Val _U_(0x2) /**< \brief (TCC_FCTRLB) Inverted MCEx (x=0,1) event input */ 448 #define TCC_FCTRLB_SRC_ALTFAULT_Val _U_(0x3) /**< \brief (TCC_FCTRLB) Alternate fault (A or B) state at the end of the previous period */ 449 #define TCC_FCTRLB_SRC_DISABLE (TCC_FCTRLB_SRC_DISABLE_Val << TCC_FCTRLB_SRC_Pos) 450 #define TCC_FCTRLB_SRC_ENABLE (TCC_FCTRLB_SRC_ENABLE_Val << TCC_FCTRLB_SRC_Pos) 451 #define TCC_FCTRLB_SRC_INVERT (TCC_FCTRLB_SRC_INVERT_Val << TCC_FCTRLB_SRC_Pos) 452 #define TCC_FCTRLB_SRC_ALTFAULT (TCC_FCTRLB_SRC_ALTFAULT_Val << TCC_FCTRLB_SRC_Pos) 453 #define TCC_FCTRLB_KEEP_Pos 3 /**< \brief (TCC_FCTRLB) Fault B Keeper */ 454 #define TCC_FCTRLB_KEEP (_U_(0x1) << TCC_FCTRLB_KEEP_Pos) 455 #define TCC_FCTRLB_QUAL_Pos 4 /**< \brief (TCC_FCTRLB) Fault B Qualification */ 456 #define TCC_FCTRLB_QUAL (_U_(0x1) << TCC_FCTRLB_QUAL_Pos) 457 #define TCC_FCTRLB_BLANK_Pos 5 /**< \brief (TCC_FCTRLB) Fault B Blanking Mode */ 458 #define TCC_FCTRLB_BLANK_Msk (_U_(0x3) << TCC_FCTRLB_BLANK_Pos) 459 #define TCC_FCTRLB_BLANK(value) (TCC_FCTRLB_BLANK_Msk & ((value) << TCC_FCTRLB_BLANK_Pos)) 460 #define TCC_FCTRLB_BLANK_NONE_Val _U_(0x0) /**< \brief (TCC_FCTRLB) No blanking applied */ 461 #define TCC_FCTRLB_BLANK_RISE_Val _U_(0x1) /**< \brief (TCC_FCTRLB) Blanking applied from rising edge of the output waveform */ 462 #define TCC_FCTRLB_BLANK_FALL_Val _U_(0x2) /**< \brief (TCC_FCTRLB) Blanking applied from falling edge of the output waveform */ 463 #define TCC_FCTRLB_BLANK_BOTH_Val _U_(0x3) /**< \brief (TCC_FCTRLB) Blanking applied from each toggle of the output waveform */ 464 #define TCC_FCTRLB_BLANK_NONE (TCC_FCTRLB_BLANK_NONE_Val << TCC_FCTRLB_BLANK_Pos) 465 #define TCC_FCTRLB_BLANK_RISE (TCC_FCTRLB_BLANK_RISE_Val << TCC_FCTRLB_BLANK_Pos) 466 #define TCC_FCTRLB_BLANK_FALL (TCC_FCTRLB_BLANK_FALL_Val << TCC_FCTRLB_BLANK_Pos) 467 #define TCC_FCTRLB_BLANK_BOTH (TCC_FCTRLB_BLANK_BOTH_Val << TCC_FCTRLB_BLANK_Pos) 468 #define TCC_FCTRLB_RESTART_Pos 7 /**< \brief (TCC_FCTRLB) Fault B Restart */ 469 #define TCC_FCTRLB_RESTART (_U_(0x1) << TCC_FCTRLB_RESTART_Pos) 470 #define TCC_FCTRLB_HALT_Pos 8 /**< \brief (TCC_FCTRLB) Fault B Halt Mode */ 471 #define TCC_FCTRLB_HALT_Msk (_U_(0x3) << TCC_FCTRLB_HALT_Pos) 472 #define TCC_FCTRLB_HALT(value) (TCC_FCTRLB_HALT_Msk & ((value) << TCC_FCTRLB_HALT_Pos)) 473 #define TCC_FCTRLB_HALT_DISABLE_Val _U_(0x0) /**< \brief (TCC_FCTRLB) Halt action disabled */ 474 #define TCC_FCTRLB_HALT_HW_Val _U_(0x1) /**< \brief (TCC_FCTRLB) Hardware halt action */ 475 #define TCC_FCTRLB_HALT_SW_Val _U_(0x2) /**< \brief (TCC_FCTRLB) Software halt action */ 476 #define TCC_FCTRLB_HALT_NR_Val _U_(0x3) /**< \brief (TCC_FCTRLB) Non-recoverable fault */ 477 #define TCC_FCTRLB_HALT_DISABLE (TCC_FCTRLB_HALT_DISABLE_Val << TCC_FCTRLB_HALT_Pos) 478 #define TCC_FCTRLB_HALT_HW (TCC_FCTRLB_HALT_HW_Val << TCC_FCTRLB_HALT_Pos) 479 #define TCC_FCTRLB_HALT_SW (TCC_FCTRLB_HALT_SW_Val << TCC_FCTRLB_HALT_Pos) 480 #define TCC_FCTRLB_HALT_NR (TCC_FCTRLB_HALT_NR_Val << TCC_FCTRLB_HALT_Pos) 481 #define TCC_FCTRLB_CHSEL_Pos 10 /**< \brief (TCC_FCTRLB) Fault B Capture Channel */ 482 #define TCC_FCTRLB_CHSEL_Msk (_U_(0x3) << TCC_FCTRLB_CHSEL_Pos) 483 #define TCC_FCTRLB_CHSEL(value) (TCC_FCTRLB_CHSEL_Msk & ((value) << TCC_FCTRLB_CHSEL_Pos)) 484 #define TCC_FCTRLB_CHSEL_CC0_Val _U_(0x0) /**< \brief (TCC_FCTRLB) Capture value stored in channel 0 */ 485 #define TCC_FCTRLB_CHSEL_CC1_Val _U_(0x1) /**< \brief (TCC_FCTRLB) Capture value stored in channel 1 */ 486 #define TCC_FCTRLB_CHSEL_CC2_Val _U_(0x2) /**< \brief (TCC_FCTRLB) Capture value stored in channel 2 */ 487 #define TCC_FCTRLB_CHSEL_CC3_Val _U_(0x3) /**< \brief (TCC_FCTRLB) Capture value stored in channel 3 */ 488 #define TCC_FCTRLB_CHSEL_CC0 (TCC_FCTRLB_CHSEL_CC0_Val << TCC_FCTRLB_CHSEL_Pos) 489 #define TCC_FCTRLB_CHSEL_CC1 (TCC_FCTRLB_CHSEL_CC1_Val << TCC_FCTRLB_CHSEL_Pos) 490 #define TCC_FCTRLB_CHSEL_CC2 (TCC_FCTRLB_CHSEL_CC2_Val << TCC_FCTRLB_CHSEL_Pos) 491 #define TCC_FCTRLB_CHSEL_CC3 (TCC_FCTRLB_CHSEL_CC3_Val << TCC_FCTRLB_CHSEL_Pos) 492 #define TCC_FCTRLB_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLB) Fault B Capture Action */ 493 #define TCC_FCTRLB_CAPTURE_Msk (_U_(0x7) << TCC_FCTRLB_CAPTURE_Pos) 494 #define TCC_FCTRLB_CAPTURE(value) (TCC_FCTRLB_CAPTURE_Msk & ((value) << TCC_FCTRLB_CAPTURE_Pos)) 495 #define TCC_FCTRLB_CAPTURE_DISABLE_Val _U_(0x0) /**< \brief (TCC_FCTRLB) No capture */ 496 #define TCC_FCTRLB_CAPTURE_CAPT_Val _U_(0x1) /**< \brief (TCC_FCTRLB) Capture on fault */ 497 #define TCC_FCTRLB_CAPTURE_CAPTMIN_Val _U_(0x2) /**< \brief (TCC_FCTRLB) Minimum capture */ 498 #define TCC_FCTRLB_CAPTURE_CAPTMAX_Val _U_(0x3) /**< \brief (TCC_FCTRLB) Maximum capture */ 499 #define TCC_FCTRLB_CAPTURE_LOCMIN_Val _U_(0x4) /**< \brief (TCC_FCTRLB) Minimum local detection */ 500 #define TCC_FCTRLB_CAPTURE_LOCMAX_Val _U_(0x5) /**< \brief (TCC_FCTRLB) Maximum local detection */ 501 #define TCC_FCTRLB_CAPTURE_DERIV0_Val _U_(0x6) /**< \brief (TCC_FCTRLB) Minimum and maximum local detection */ 502 #define TCC_FCTRLB_CAPTURE_DISABLE (TCC_FCTRLB_CAPTURE_DISABLE_Val << TCC_FCTRLB_CAPTURE_Pos) 503 #define TCC_FCTRLB_CAPTURE_CAPT (TCC_FCTRLB_CAPTURE_CAPT_Val << TCC_FCTRLB_CAPTURE_Pos) 504 #define TCC_FCTRLB_CAPTURE_CAPTMIN (TCC_FCTRLB_CAPTURE_CAPTMIN_Val << TCC_FCTRLB_CAPTURE_Pos) 505 #define TCC_FCTRLB_CAPTURE_CAPTMAX (TCC_FCTRLB_CAPTURE_CAPTMAX_Val << TCC_FCTRLB_CAPTURE_Pos) 506 #define TCC_FCTRLB_CAPTURE_LOCMIN (TCC_FCTRLB_CAPTURE_LOCMIN_Val << TCC_FCTRLB_CAPTURE_Pos) 507 #define TCC_FCTRLB_CAPTURE_LOCMAX (TCC_FCTRLB_CAPTURE_LOCMAX_Val << TCC_FCTRLB_CAPTURE_Pos) 508 #define TCC_FCTRLB_CAPTURE_DERIV0 (TCC_FCTRLB_CAPTURE_DERIV0_Val << TCC_FCTRLB_CAPTURE_Pos) 509 #define TCC_FCTRLB_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLB) Fault B Blanking Time */ 510 #define TCC_FCTRLB_BLANKVAL_Msk (_U_(0xFF) << TCC_FCTRLB_BLANKVAL_Pos) 511 #define TCC_FCTRLB_BLANKVAL(value) (TCC_FCTRLB_BLANKVAL_Msk & ((value) << TCC_FCTRLB_BLANKVAL_Pos)) 512 #define TCC_FCTRLB_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLB) Fault B Filter Value */ 513 #define TCC_FCTRLB_FILTERVAL_Msk (_U_(0xF) << TCC_FCTRLB_FILTERVAL_Pos) 514 #define TCC_FCTRLB_FILTERVAL(value) (TCC_FCTRLB_FILTERVAL_Msk & ((value) << TCC_FCTRLB_FILTERVAL_Pos)) 515 #define TCC_FCTRLB_MASK _U_(0x0FFF7FFB) /**< \brief (TCC_FCTRLB) MASK Register */ 516 517 /* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */ 518 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 519 typedef union { 520 struct { 521 uint32_t OTMX:2; /*!< bit: 0.. 1 Output Matrix */ 522 uint32_t :6; /*!< bit: 2.. 7 Reserved */ 523 uint32_t DTIEN0:1; /*!< bit: 8 Dead-time Insertion Generator 0 Enable */ 524 uint32_t DTIEN1:1; /*!< bit: 9 Dead-time Insertion Generator 1 Enable */ 525 uint32_t DTIEN2:1; /*!< bit: 10 Dead-time Insertion Generator 2 Enable */ 526 uint32_t DTIEN3:1; /*!< bit: 11 Dead-time Insertion Generator 3 Enable */ 527 uint32_t :4; /*!< bit: 12..15 Reserved */ 528 uint32_t DTLS:8; /*!< bit: 16..23 Dead-time Low Side Outputs Value */ 529 uint32_t DTHS:8; /*!< bit: 24..31 Dead-time High Side Outputs Value */ 530 } bit; /*!< Structure used for bit access */ 531 struct { 532 uint32_t :8; /*!< bit: 0.. 7 Reserved */ 533 uint32_t DTIEN:4; /*!< bit: 8..11 Dead-time Insertion Generator x Enable */ 534 uint32_t :20; /*!< bit: 12..31 Reserved */ 535 } vec; /*!< Structure used for vec access */ 536 uint32_t reg; /*!< Type used for register access */ 537 } TCC_WEXCTRL_Type; 538 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 539 540 #define TCC_WEXCTRL_OFFSET 0x14 /**< \brief (TCC_WEXCTRL offset) Waveform Extension Configuration */ 541 #define TCC_WEXCTRL_RESETVALUE _U_(0x00000000) /**< \brief (TCC_WEXCTRL reset_value) Waveform Extension Configuration */ 542 543 #define TCC_WEXCTRL_OTMX_Pos 0 /**< \brief (TCC_WEXCTRL) Output Matrix */ 544 #define TCC_WEXCTRL_OTMX_Msk (_U_(0x3) << TCC_WEXCTRL_OTMX_Pos) 545 #define TCC_WEXCTRL_OTMX(value) (TCC_WEXCTRL_OTMX_Msk & ((value) << TCC_WEXCTRL_OTMX_Pos)) 546 #define TCC_WEXCTRL_DTIEN0_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 0 Enable */ 547 #define TCC_WEXCTRL_DTIEN0 (1 << TCC_WEXCTRL_DTIEN0_Pos) 548 #define TCC_WEXCTRL_DTIEN1_Pos 9 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 1 Enable */ 549 #define TCC_WEXCTRL_DTIEN1 (1 << TCC_WEXCTRL_DTIEN1_Pos) 550 #define TCC_WEXCTRL_DTIEN2_Pos 10 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 2 Enable */ 551 #define TCC_WEXCTRL_DTIEN2 (1 << TCC_WEXCTRL_DTIEN2_Pos) 552 #define TCC_WEXCTRL_DTIEN3_Pos 11 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 3 Enable */ 553 #define TCC_WEXCTRL_DTIEN3 (1 << TCC_WEXCTRL_DTIEN3_Pos) 554 #define TCC_WEXCTRL_DTIEN_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator x Enable */ 555 #define TCC_WEXCTRL_DTIEN_Msk (_U_(0xF) << TCC_WEXCTRL_DTIEN_Pos) 556 #define TCC_WEXCTRL_DTIEN(value) (TCC_WEXCTRL_DTIEN_Msk & ((value) << TCC_WEXCTRL_DTIEN_Pos)) 557 #define TCC_WEXCTRL_DTLS_Pos 16 /**< \brief (TCC_WEXCTRL) Dead-time Low Side Outputs Value */ 558 #define TCC_WEXCTRL_DTLS_Msk (_U_(0xFF) << TCC_WEXCTRL_DTLS_Pos) 559 #define TCC_WEXCTRL_DTLS(value) (TCC_WEXCTRL_DTLS_Msk & ((value) << TCC_WEXCTRL_DTLS_Pos)) 560 #define TCC_WEXCTRL_DTHS_Pos 24 /**< \brief (TCC_WEXCTRL) Dead-time High Side Outputs Value */ 561 #define TCC_WEXCTRL_DTHS_Msk (_U_(0xFF) << TCC_WEXCTRL_DTHS_Pos) 562 #define TCC_WEXCTRL_DTHS(value) (TCC_WEXCTRL_DTHS_Msk & ((value) << TCC_WEXCTRL_DTHS_Pos)) 563 #define TCC_WEXCTRL_MASK _U_(0xFFFF0F03) /**< \brief (TCC_WEXCTRL) MASK Register */ 564 565 /* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */ 566 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 567 typedef union { 568 struct { 569 uint32_t NRE0:1; /*!< bit: 0 Non-Recoverable State 0 Output Enable */ 570 uint32_t NRE1:1; /*!< bit: 1 Non-Recoverable State 1 Output Enable */ 571 uint32_t NRE2:1; /*!< bit: 2 Non-Recoverable State 2 Output Enable */ 572 uint32_t NRE3:1; /*!< bit: 3 Non-Recoverable State 3 Output Enable */ 573 uint32_t NRE4:1; /*!< bit: 4 Non-Recoverable State 4 Output Enable */ 574 uint32_t NRE5:1; /*!< bit: 5 Non-Recoverable State 5 Output Enable */ 575 uint32_t NRE6:1; /*!< bit: 6 Non-Recoverable State 6 Output Enable */ 576 uint32_t NRE7:1; /*!< bit: 7 Non-Recoverable State 7 Output Enable */ 577 uint32_t NRV0:1; /*!< bit: 8 Non-Recoverable State 0 Output Value */ 578 uint32_t NRV1:1; /*!< bit: 9 Non-Recoverable State 1 Output Value */ 579 uint32_t NRV2:1; /*!< bit: 10 Non-Recoverable State 2 Output Value */ 580 uint32_t NRV3:1; /*!< bit: 11 Non-Recoverable State 3 Output Value */ 581 uint32_t NRV4:1; /*!< bit: 12 Non-Recoverable State 4 Output Value */ 582 uint32_t NRV5:1; /*!< bit: 13 Non-Recoverable State 5 Output Value */ 583 uint32_t NRV6:1; /*!< bit: 14 Non-Recoverable State 6 Output Value */ 584 uint32_t NRV7:1; /*!< bit: 15 Non-Recoverable State 7 Output Value */ 585 uint32_t INVEN0:1; /*!< bit: 16 Output Waveform 0 Inversion */ 586 uint32_t INVEN1:1; /*!< bit: 17 Output Waveform 1 Inversion */ 587 uint32_t INVEN2:1; /*!< bit: 18 Output Waveform 2 Inversion */ 588 uint32_t INVEN3:1; /*!< bit: 19 Output Waveform 3 Inversion */ 589 uint32_t INVEN4:1; /*!< bit: 20 Output Waveform 4 Inversion */ 590 uint32_t INVEN5:1; /*!< bit: 21 Output Waveform 5 Inversion */ 591 uint32_t INVEN6:1; /*!< bit: 22 Output Waveform 6 Inversion */ 592 uint32_t INVEN7:1; /*!< bit: 23 Output Waveform 7 Inversion */ 593 uint32_t FILTERVAL0:4; /*!< bit: 24..27 Non-Recoverable Fault Input 0 Filter Value */ 594 uint32_t FILTERVAL1:4; /*!< bit: 28..31 Non-Recoverable Fault Input 1 Filter Value */ 595 } bit; /*!< Structure used for bit access */ 596 struct { 597 uint32_t NRE:8; /*!< bit: 0.. 7 Non-Recoverable State x Output Enable */ 598 uint32_t NRV:8; /*!< bit: 8..15 Non-Recoverable State x Output Value */ 599 uint32_t INVEN:8; /*!< bit: 16..23 Output Waveform x Inversion */ 600 uint32_t :8; /*!< bit: 24..31 Reserved */ 601 } vec; /*!< Structure used for vec access */ 602 uint32_t reg; /*!< Type used for register access */ 603 } TCC_DRVCTRL_Type; 604 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 605 606 #define TCC_DRVCTRL_OFFSET 0x18 /**< \brief (TCC_DRVCTRL offset) Driver Control */ 607 #define TCC_DRVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (TCC_DRVCTRL reset_value) Driver Control */ 608 609 #define TCC_DRVCTRL_NRE0_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Enable */ 610 #define TCC_DRVCTRL_NRE0 (1 << TCC_DRVCTRL_NRE0_Pos) 611 #define TCC_DRVCTRL_NRE1_Pos 1 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Enable */ 612 #define TCC_DRVCTRL_NRE1 (1 << TCC_DRVCTRL_NRE1_Pos) 613 #define TCC_DRVCTRL_NRE2_Pos 2 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Enable */ 614 #define TCC_DRVCTRL_NRE2 (1 << TCC_DRVCTRL_NRE2_Pos) 615 #define TCC_DRVCTRL_NRE3_Pos 3 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Enable */ 616 #define TCC_DRVCTRL_NRE3 (1 << TCC_DRVCTRL_NRE3_Pos) 617 #define TCC_DRVCTRL_NRE4_Pos 4 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Enable */ 618 #define TCC_DRVCTRL_NRE4 (1 << TCC_DRVCTRL_NRE4_Pos) 619 #define TCC_DRVCTRL_NRE5_Pos 5 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Enable */ 620 #define TCC_DRVCTRL_NRE5 (1 << TCC_DRVCTRL_NRE5_Pos) 621 #define TCC_DRVCTRL_NRE6_Pos 6 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Enable */ 622 #define TCC_DRVCTRL_NRE6 (1 << TCC_DRVCTRL_NRE6_Pos) 623 #define TCC_DRVCTRL_NRE7_Pos 7 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Enable */ 624 #define TCC_DRVCTRL_NRE7 (1 << TCC_DRVCTRL_NRE7_Pos) 625 #define TCC_DRVCTRL_NRE_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Enable */ 626 #define TCC_DRVCTRL_NRE_Msk (_U_(0xFF) << TCC_DRVCTRL_NRE_Pos) 627 #define TCC_DRVCTRL_NRE(value) (TCC_DRVCTRL_NRE_Msk & ((value) << TCC_DRVCTRL_NRE_Pos)) 628 #define TCC_DRVCTRL_NRV0_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Value */ 629 #define TCC_DRVCTRL_NRV0 (1 << TCC_DRVCTRL_NRV0_Pos) 630 #define TCC_DRVCTRL_NRV1_Pos 9 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Value */ 631 #define TCC_DRVCTRL_NRV1 (1 << TCC_DRVCTRL_NRV1_Pos) 632 #define TCC_DRVCTRL_NRV2_Pos 10 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Value */ 633 #define TCC_DRVCTRL_NRV2 (1 << TCC_DRVCTRL_NRV2_Pos) 634 #define TCC_DRVCTRL_NRV3_Pos 11 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Value */ 635 #define TCC_DRVCTRL_NRV3 (1 << TCC_DRVCTRL_NRV3_Pos) 636 #define TCC_DRVCTRL_NRV4_Pos 12 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Value */ 637 #define TCC_DRVCTRL_NRV4 (1 << TCC_DRVCTRL_NRV4_Pos) 638 #define TCC_DRVCTRL_NRV5_Pos 13 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Value */ 639 #define TCC_DRVCTRL_NRV5 (1 << TCC_DRVCTRL_NRV5_Pos) 640 #define TCC_DRVCTRL_NRV6_Pos 14 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Value */ 641 #define TCC_DRVCTRL_NRV6 (1 << TCC_DRVCTRL_NRV6_Pos) 642 #define TCC_DRVCTRL_NRV7_Pos 15 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Value */ 643 #define TCC_DRVCTRL_NRV7 (1 << TCC_DRVCTRL_NRV7_Pos) 644 #define TCC_DRVCTRL_NRV_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Value */ 645 #define TCC_DRVCTRL_NRV_Msk (_U_(0xFF) << TCC_DRVCTRL_NRV_Pos) 646 #define TCC_DRVCTRL_NRV(value) (TCC_DRVCTRL_NRV_Msk & ((value) << TCC_DRVCTRL_NRV_Pos)) 647 #define TCC_DRVCTRL_INVEN0_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform 0 Inversion */ 648 #define TCC_DRVCTRL_INVEN0 (1 << TCC_DRVCTRL_INVEN0_Pos) 649 #define TCC_DRVCTRL_INVEN1_Pos 17 /**< \brief (TCC_DRVCTRL) Output Waveform 1 Inversion */ 650 #define TCC_DRVCTRL_INVEN1 (1 << TCC_DRVCTRL_INVEN1_Pos) 651 #define TCC_DRVCTRL_INVEN2_Pos 18 /**< \brief (TCC_DRVCTRL) Output Waveform 2 Inversion */ 652 #define TCC_DRVCTRL_INVEN2 (1 << TCC_DRVCTRL_INVEN2_Pos) 653 #define TCC_DRVCTRL_INVEN3_Pos 19 /**< \brief (TCC_DRVCTRL) Output Waveform 3 Inversion */ 654 #define TCC_DRVCTRL_INVEN3 (1 << TCC_DRVCTRL_INVEN3_Pos) 655 #define TCC_DRVCTRL_INVEN4_Pos 20 /**< \brief (TCC_DRVCTRL) Output Waveform 4 Inversion */ 656 #define TCC_DRVCTRL_INVEN4 (1 << TCC_DRVCTRL_INVEN4_Pos) 657 #define TCC_DRVCTRL_INVEN5_Pos 21 /**< \brief (TCC_DRVCTRL) Output Waveform 5 Inversion */ 658 #define TCC_DRVCTRL_INVEN5 (1 << TCC_DRVCTRL_INVEN5_Pos) 659 #define TCC_DRVCTRL_INVEN6_Pos 22 /**< \brief (TCC_DRVCTRL) Output Waveform 6 Inversion */ 660 #define TCC_DRVCTRL_INVEN6 (1 << TCC_DRVCTRL_INVEN6_Pos) 661 #define TCC_DRVCTRL_INVEN7_Pos 23 /**< \brief (TCC_DRVCTRL) Output Waveform 7 Inversion */ 662 #define TCC_DRVCTRL_INVEN7 (1 << TCC_DRVCTRL_INVEN7_Pos) 663 #define TCC_DRVCTRL_INVEN_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform x Inversion */ 664 #define TCC_DRVCTRL_INVEN_Msk (_U_(0xFF) << TCC_DRVCTRL_INVEN_Pos) 665 #define TCC_DRVCTRL_INVEN(value) (TCC_DRVCTRL_INVEN_Msk & ((value) << TCC_DRVCTRL_INVEN_Pos)) 666 #define TCC_DRVCTRL_FILTERVAL0_Pos 24 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 0 Filter Value */ 667 #define TCC_DRVCTRL_FILTERVAL0_Msk (_U_(0xF) << TCC_DRVCTRL_FILTERVAL0_Pos) 668 #define TCC_DRVCTRL_FILTERVAL0(value) (TCC_DRVCTRL_FILTERVAL0_Msk & ((value) << TCC_DRVCTRL_FILTERVAL0_Pos)) 669 #define TCC_DRVCTRL_FILTERVAL1_Pos 28 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 1 Filter Value */ 670 #define TCC_DRVCTRL_FILTERVAL1_Msk (_U_(0xF) << TCC_DRVCTRL_FILTERVAL1_Pos) 671 #define TCC_DRVCTRL_FILTERVAL1(value) (TCC_DRVCTRL_FILTERVAL1_Msk & ((value) << TCC_DRVCTRL_FILTERVAL1_Pos)) 672 #define TCC_DRVCTRL_MASK _U_(0xFFFFFFFF) /**< \brief (TCC_DRVCTRL) MASK Register */ 673 674 /* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W 8) Debug Control -------- */ 675 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 676 typedef union { 677 struct { 678 uint8_t DBGRUN:1; /*!< bit: 0 Debug Running Mode */ 679 uint8_t :1; /*!< bit: 1 Reserved */ 680 uint8_t FDDBD:1; /*!< bit: 2 Fault Detection on Debug Break Detection */ 681 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 682 } bit; /*!< Structure used for bit access */ 683 uint8_t reg; /*!< Type used for register access */ 684 } TCC_DBGCTRL_Type; 685 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 686 687 #define TCC_DBGCTRL_OFFSET 0x1E /**< \brief (TCC_DBGCTRL offset) Debug Control */ 688 #define TCC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (TCC_DBGCTRL reset_value) Debug Control */ 689 690 #define TCC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TCC_DBGCTRL) Debug Running Mode */ 691 #define TCC_DBGCTRL_DBGRUN (_U_(0x1) << TCC_DBGCTRL_DBGRUN_Pos) 692 #define TCC_DBGCTRL_FDDBD_Pos 2 /**< \brief (TCC_DBGCTRL) Fault Detection on Debug Break Detection */ 693 #define TCC_DBGCTRL_FDDBD (_U_(0x1) << TCC_DBGCTRL_FDDBD_Pos) 694 #define TCC_DBGCTRL_MASK _U_(0x05) /**< \brief (TCC_DBGCTRL) MASK Register */ 695 696 /* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */ 697 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 698 typedef union { 699 struct { 700 uint32_t EVACT0:3; /*!< bit: 0.. 2 Timer/counter Input Event0 Action */ 701 uint32_t EVACT1:3; /*!< bit: 3.. 5 Timer/counter Input Event1 Action */ 702 uint32_t CNTSEL:2; /*!< bit: 6.. 7 Timer/counter Output Event Mode */ 703 uint32_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */ 704 uint32_t TRGEO:1; /*!< bit: 9 Retrigger Output Event Enable */ 705 uint32_t CNTEO:1; /*!< bit: 10 Timer/counter Output Event Enable */ 706 uint32_t :1; /*!< bit: 11 Reserved */ 707 uint32_t TCINV0:1; /*!< bit: 12 Inverted Event 0 Input Enable */ 708 uint32_t TCINV1:1; /*!< bit: 13 Inverted Event 1 Input Enable */ 709 uint32_t TCEI0:1; /*!< bit: 14 Timer/counter Event 0 Input Enable */ 710 uint32_t TCEI1:1; /*!< bit: 15 Timer/counter Event 1 Input Enable */ 711 uint32_t MCEI0:1; /*!< bit: 16 Match or Capture Channel 0 Event Input Enable */ 712 uint32_t MCEI1:1; /*!< bit: 17 Match or Capture Channel 1 Event Input Enable */ 713 uint32_t MCEI2:1; /*!< bit: 18 Match or Capture Channel 2 Event Input Enable */ 714 uint32_t MCEI3:1; /*!< bit: 19 Match or Capture Channel 3 Event Input Enable */ 715 uint32_t :4; /*!< bit: 20..23 Reserved */ 716 uint32_t MCEO0:1; /*!< bit: 24 Match or Capture Channel 0 Event Output Enable */ 717 uint32_t MCEO1:1; /*!< bit: 25 Match or Capture Channel 1 Event Output Enable */ 718 uint32_t MCEO2:1; /*!< bit: 26 Match or Capture Channel 2 Event Output Enable */ 719 uint32_t MCEO3:1; /*!< bit: 27 Match or Capture Channel 3 Event Output Enable */ 720 uint32_t :4; /*!< bit: 28..31 Reserved */ 721 } bit; /*!< Structure used for bit access */ 722 struct { 723 uint32_t :12; /*!< bit: 0..11 Reserved */ 724 uint32_t TCINV:2; /*!< bit: 12..13 Inverted Event x Input Enable */ 725 uint32_t TCEI:2; /*!< bit: 14..15 Timer/counter Event x Input Enable */ 726 uint32_t MCEI:4; /*!< bit: 16..19 Match or Capture Channel x Event Input Enable */ 727 uint32_t :4; /*!< bit: 20..23 Reserved */ 728 uint32_t MCEO:4; /*!< bit: 24..27 Match or Capture Channel x Event Output Enable */ 729 uint32_t :4; /*!< bit: 28..31 Reserved */ 730 } vec; /*!< Structure used for vec access */ 731 uint32_t reg; /*!< Type used for register access */ 732 } TCC_EVCTRL_Type; 733 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 734 735 #define TCC_EVCTRL_OFFSET 0x20 /**< \brief (TCC_EVCTRL offset) Event Control */ 736 #define TCC_EVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (TCC_EVCTRL reset_value) Event Control */ 737 738 #define TCC_EVCTRL_EVACT0_Pos 0 /**< \brief (TCC_EVCTRL) Timer/counter Input Event0 Action */ 739 #define TCC_EVCTRL_EVACT0_Msk (_U_(0x7) << TCC_EVCTRL_EVACT0_Pos) 740 #define TCC_EVCTRL_EVACT0(value) (TCC_EVCTRL_EVACT0_Msk & ((value) << TCC_EVCTRL_EVACT0_Pos)) 741 #define TCC_EVCTRL_EVACT0_OFF_Val _U_(0x0) /**< \brief (TCC_EVCTRL) Event action disabled */ 742 #define TCC_EVCTRL_EVACT0_RETRIGGER_Val _U_(0x1) /**< \brief (TCC_EVCTRL) Start, restart or re-trigger counter on event */ 743 #define TCC_EVCTRL_EVACT0_COUNTEV_Val _U_(0x2) /**< \brief (TCC_EVCTRL) Count on event */ 744 #define TCC_EVCTRL_EVACT0_START_Val _U_(0x3) /**< \brief (TCC_EVCTRL) Start counter on event */ 745 #define TCC_EVCTRL_EVACT0_INC_Val _U_(0x4) /**< \brief (TCC_EVCTRL) Increment counter on event */ 746 #define TCC_EVCTRL_EVACT0_COUNT_Val _U_(0x5) /**< \brief (TCC_EVCTRL) Count on active state of asynchronous event */ 747 #define TCC_EVCTRL_EVACT0_FAULT_Val _U_(0x7) /**< \brief (TCC_EVCTRL) Non-recoverable fault */ 748 #define TCC_EVCTRL_EVACT0_OFF (TCC_EVCTRL_EVACT0_OFF_Val << TCC_EVCTRL_EVACT0_Pos) 749 #define TCC_EVCTRL_EVACT0_RETRIGGER (TCC_EVCTRL_EVACT0_RETRIGGER_Val << TCC_EVCTRL_EVACT0_Pos) 750 #define TCC_EVCTRL_EVACT0_COUNTEV (TCC_EVCTRL_EVACT0_COUNTEV_Val << TCC_EVCTRL_EVACT0_Pos) 751 #define TCC_EVCTRL_EVACT0_START (TCC_EVCTRL_EVACT0_START_Val << TCC_EVCTRL_EVACT0_Pos) 752 #define TCC_EVCTRL_EVACT0_INC (TCC_EVCTRL_EVACT0_INC_Val << TCC_EVCTRL_EVACT0_Pos) 753 #define TCC_EVCTRL_EVACT0_COUNT (TCC_EVCTRL_EVACT0_COUNT_Val << TCC_EVCTRL_EVACT0_Pos) 754 #define TCC_EVCTRL_EVACT0_FAULT (TCC_EVCTRL_EVACT0_FAULT_Val << TCC_EVCTRL_EVACT0_Pos) 755 #define TCC_EVCTRL_EVACT1_Pos 3 /**< \brief (TCC_EVCTRL) Timer/counter Input Event1 Action */ 756 #define TCC_EVCTRL_EVACT1_Msk (_U_(0x7) << TCC_EVCTRL_EVACT1_Pos) 757 #define TCC_EVCTRL_EVACT1(value) (TCC_EVCTRL_EVACT1_Msk & ((value) << TCC_EVCTRL_EVACT1_Pos)) 758 #define TCC_EVCTRL_EVACT1_OFF_Val _U_(0x0) /**< \brief (TCC_EVCTRL) Event action disabled */ 759 #define TCC_EVCTRL_EVACT1_RETRIGGER_Val _U_(0x1) /**< \brief (TCC_EVCTRL) Re-trigger counter on event */ 760 #define TCC_EVCTRL_EVACT1_DIR_Val _U_(0x2) /**< \brief (TCC_EVCTRL) Direction control */ 761 #define TCC_EVCTRL_EVACT1_STOP_Val _U_(0x3) /**< \brief (TCC_EVCTRL) Stop counter on event */ 762 #define TCC_EVCTRL_EVACT1_DEC_Val _U_(0x4) /**< \brief (TCC_EVCTRL) Decrement counter on event */ 763 #define TCC_EVCTRL_EVACT1_PPW_Val _U_(0x5) /**< \brief (TCC_EVCTRL) Period capture value in CC0 register, pulse width capture value in CC1 register */ 764 #define TCC_EVCTRL_EVACT1_PWP_Val _U_(0x6) /**< \brief (TCC_EVCTRL) Period capture value in CC1 register, pulse width capture value in CC0 register */ 765 #define TCC_EVCTRL_EVACT1_FAULT_Val _U_(0x7) /**< \brief (TCC_EVCTRL) Non-recoverable fault */ 766 #define TCC_EVCTRL_EVACT1_OFF (TCC_EVCTRL_EVACT1_OFF_Val << TCC_EVCTRL_EVACT1_Pos) 767 #define TCC_EVCTRL_EVACT1_RETRIGGER (TCC_EVCTRL_EVACT1_RETRIGGER_Val << TCC_EVCTRL_EVACT1_Pos) 768 #define TCC_EVCTRL_EVACT1_DIR (TCC_EVCTRL_EVACT1_DIR_Val << TCC_EVCTRL_EVACT1_Pos) 769 #define TCC_EVCTRL_EVACT1_STOP (TCC_EVCTRL_EVACT1_STOP_Val << TCC_EVCTRL_EVACT1_Pos) 770 #define TCC_EVCTRL_EVACT1_DEC (TCC_EVCTRL_EVACT1_DEC_Val << TCC_EVCTRL_EVACT1_Pos) 771 #define TCC_EVCTRL_EVACT1_PPW (TCC_EVCTRL_EVACT1_PPW_Val << TCC_EVCTRL_EVACT1_Pos) 772 #define TCC_EVCTRL_EVACT1_PWP (TCC_EVCTRL_EVACT1_PWP_Val << TCC_EVCTRL_EVACT1_Pos) 773 #define TCC_EVCTRL_EVACT1_FAULT (TCC_EVCTRL_EVACT1_FAULT_Val << TCC_EVCTRL_EVACT1_Pos) 774 #define TCC_EVCTRL_CNTSEL_Pos 6 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Mode */ 775 #define TCC_EVCTRL_CNTSEL_Msk (_U_(0x3) << TCC_EVCTRL_CNTSEL_Pos) 776 #define TCC_EVCTRL_CNTSEL(value) (TCC_EVCTRL_CNTSEL_Msk & ((value) << TCC_EVCTRL_CNTSEL_Pos)) 777 #define TCC_EVCTRL_CNTSEL_START_Val _U_(0x0) /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts */ 778 #define TCC_EVCTRL_CNTSEL_END_Val _U_(0x1) /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends */ 779 #define TCC_EVCTRL_CNTSEL_BETWEEN_Val _U_(0x2) /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends, except for the first and last cycles */ 780 #define TCC_EVCTRL_CNTSEL_BOUNDARY_Val _U_(0x3) /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts or a counter cycle ends */ 781 #define TCC_EVCTRL_CNTSEL_START (TCC_EVCTRL_CNTSEL_START_Val << TCC_EVCTRL_CNTSEL_Pos) 782 #define TCC_EVCTRL_CNTSEL_END (TCC_EVCTRL_CNTSEL_END_Val << TCC_EVCTRL_CNTSEL_Pos) 783 #define TCC_EVCTRL_CNTSEL_BETWEEN (TCC_EVCTRL_CNTSEL_BETWEEN_Val << TCC_EVCTRL_CNTSEL_Pos) 784 #define TCC_EVCTRL_CNTSEL_BOUNDARY (TCC_EVCTRL_CNTSEL_BOUNDARY_Val << TCC_EVCTRL_CNTSEL_Pos) 785 #define TCC_EVCTRL_OVFEO_Pos 8 /**< \brief (TCC_EVCTRL) Overflow/Underflow Output Event Enable */ 786 #define TCC_EVCTRL_OVFEO (_U_(0x1) << TCC_EVCTRL_OVFEO_Pos) 787 #define TCC_EVCTRL_TRGEO_Pos 9 /**< \brief (TCC_EVCTRL) Retrigger Output Event Enable */ 788 #define TCC_EVCTRL_TRGEO (_U_(0x1) << TCC_EVCTRL_TRGEO_Pos) 789 #define TCC_EVCTRL_CNTEO_Pos 10 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Enable */ 790 #define TCC_EVCTRL_CNTEO (_U_(0x1) << TCC_EVCTRL_CNTEO_Pos) 791 #define TCC_EVCTRL_TCINV0_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event 0 Input Enable */ 792 #define TCC_EVCTRL_TCINV0 (1 << TCC_EVCTRL_TCINV0_Pos) 793 #define TCC_EVCTRL_TCINV1_Pos 13 /**< \brief (TCC_EVCTRL) Inverted Event 1 Input Enable */ 794 #define TCC_EVCTRL_TCINV1 (1 << TCC_EVCTRL_TCINV1_Pos) 795 #define TCC_EVCTRL_TCINV_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event x Input Enable */ 796 #define TCC_EVCTRL_TCINV_Msk (_U_(0x3) << TCC_EVCTRL_TCINV_Pos) 797 #define TCC_EVCTRL_TCINV(value) (TCC_EVCTRL_TCINV_Msk & ((value) << TCC_EVCTRL_TCINV_Pos)) 798 #define TCC_EVCTRL_TCEI0_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event 0 Input Enable */ 799 #define TCC_EVCTRL_TCEI0 (1 << TCC_EVCTRL_TCEI0_Pos) 800 #define TCC_EVCTRL_TCEI1_Pos 15 /**< \brief (TCC_EVCTRL) Timer/counter Event 1 Input Enable */ 801 #define TCC_EVCTRL_TCEI1 (1 << TCC_EVCTRL_TCEI1_Pos) 802 #define TCC_EVCTRL_TCEI_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event x Input Enable */ 803 #define TCC_EVCTRL_TCEI_Msk (_U_(0x3) << TCC_EVCTRL_TCEI_Pos) 804 #define TCC_EVCTRL_TCEI(value) (TCC_EVCTRL_TCEI_Msk & ((value) << TCC_EVCTRL_TCEI_Pos)) 805 #define TCC_EVCTRL_MCEI0_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Input Enable */ 806 #define TCC_EVCTRL_MCEI0 (1 << TCC_EVCTRL_MCEI0_Pos) 807 #define TCC_EVCTRL_MCEI1_Pos 17 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Input Enable */ 808 #define TCC_EVCTRL_MCEI1 (1 << TCC_EVCTRL_MCEI1_Pos) 809 #define TCC_EVCTRL_MCEI2_Pos 18 /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Input Enable */ 810 #define TCC_EVCTRL_MCEI2 (1 << TCC_EVCTRL_MCEI2_Pos) 811 #define TCC_EVCTRL_MCEI3_Pos 19 /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Input Enable */ 812 #define TCC_EVCTRL_MCEI3 (1 << TCC_EVCTRL_MCEI3_Pos) 813 #define TCC_EVCTRL_MCEI_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Input Enable */ 814 #define TCC_EVCTRL_MCEI_Msk (_U_(0xF) << TCC_EVCTRL_MCEI_Pos) 815 #define TCC_EVCTRL_MCEI(value) (TCC_EVCTRL_MCEI_Msk & ((value) << TCC_EVCTRL_MCEI_Pos)) 816 #define TCC_EVCTRL_MCEO0_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Output Enable */ 817 #define TCC_EVCTRL_MCEO0 (1 << TCC_EVCTRL_MCEO0_Pos) 818 #define TCC_EVCTRL_MCEO1_Pos 25 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Output Enable */ 819 #define TCC_EVCTRL_MCEO1 (1 << TCC_EVCTRL_MCEO1_Pos) 820 #define TCC_EVCTRL_MCEO2_Pos 26 /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Output Enable */ 821 #define TCC_EVCTRL_MCEO2 (1 << TCC_EVCTRL_MCEO2_Pos) 822 #define TCC_EVCTRL_MCEO3_Pos 27 /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Output Enable */ 823 #define TCC_EVCTRL_MCEO3 (1 << TCC_EVCTRL_MCEO3_Pos) 824 #define TCC_EVCTRL_MCEO_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Output Enable */ 825 #define TCC_EVCTRL_MCEO_Msk (_U_(0xF) << TCC_EVCTRL_MCEO_Pos) 826 #define TCC_EVCTRL_MCEO(value) (TCC_EVCTRL_MCEO_Msk & ((value) << TCC_EVCTRL_MCEO_Pos)) 827 #define TCC_EVCTRL_MASK _U_(0x0F0FF7FF) /**< \brief (TCC_EVCTRL) MASK Register */ 828 829 /* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */ 830 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 831 typedef union { 832 struct { 833 uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ 834 uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */ 835 uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */ 836 uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */ 837 uint32_t :7; /*!< bit: 4..10 Reserved */ 838 uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */ 839 uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */ 840 uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */ 841 uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */ 842 uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */ 843 uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */ 844 uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */ 845 uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */ 846 uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */ 847 uint32_t :12; /*!< bit: 20..31 Reserved */ 848 } bit; /*!< Structure used for bit access */ 849 struct { 850 uint32_t :16; /*!< bit: 0..15 Reserved */ 851 uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */ 852 uint32_t :12; /*!< bit: 20..31 Reserved */ 853 } vec; /*!< Structure used for vec access */ 854 uint32_t reg; /*!< Type used for register access */ 855 } TCC_INTENCLR_Type; 856 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 857 858 #define TCC_INTENCLR_OFFSET 0x24 /**< \brief (TCC_INTENCLR offset) Interrupt Enable Clear */ 859 #define TCC_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (TCC_INTENCLR reset_value) Interrupt Enable Clear */ 860 861 #define TCC_INTENCLR_OVF_Pos 0 /**< \brief (TCC_INTENCLR) Overflow Interrupt Enable */ 862 #define TCC_INTENCLR_OVF (_U_(0x1) << TCC_INTENCLR_OVF_Pos) 863 #define TCC_INTENCLR_TRG_Pos 1 /**< \brief (TCC_INTENCLR) Retrigger Interrupt Enable */ 864 #define TCC_INTENCLR_TRG (_U_(0x1) << TCC_INTENCLR_TRG_Pos) 865 #define TCC_INTENCLR_CNT_Pos 2 /**< \brief (TCC_INTENCLR) Counter Interrupt Enable */ 866 #define TCC_INTENCLR_CNT (_U_(0x1) << TCC_INTENCLR_CNT_Pos) 867 #define TCC_INTENCLR_ERR_Pos 3 /**< \brief (TCC_INTENCLR) Error Interrupt Enable */ 868 #define TCC_INTENCLR_ERR (_U_(0x1) << TCC_INTENCLR_ERR_Pos) 869 #define TCC_INTENCLR_DFS_Pos 11 /**< \brief (TCC_INTENCLR) Non-Recoverable Debug Fault Interrupt Enable */ 870 #define TCC_INTENCLR_DFS (_U_(0x1) << TCC_INTENCLR_DFS_Pos) 871 #define TCC_INTENCLR_FAULTA_Pos 12 /**< \brief (TCC_INTENCLR) Recoverable Fault A Interrupt Enable */ 872 #define TCC_INTENCLR_FAULTA (_U_(0x1) << TCC_INTENCLR_FAULTA_Pos) 873 #define TCC_INTENCLR_FAULTB_Pos 13 /**< \brief (TCC_INTENCLR) Recoverable Fault B Interrupt Enable */ 874 #define TCC_INTENCLR_FAULTB (_U_(0x1) << TCC_INTENCLR_FAULTB_Pos) 875 #define TCC_INTENCLR_FAULT0_Pos 14 /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 0 Interrupt Enable */ 876 #define TCC_INTENCLR_FAULT0 (_U_(0x1) << TCC_INTENCLR_FAULT0_Pos) 877 #define TCC_INTENCLR_FAULT1_Pos 15 /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 1 Interrupt Enable */ 878 #define TCC_INTENCLR_FAULT1 (_U_(0x1) << TCC_INTENCLR_FAULT1_Pos) 879 #define TCC_INTENCLR_MC0_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */ 880 #define TCC_INTENCLR_MC0 (1 << TCC_INTENCLR_MC0_Pos) 881 #define TCC_INTENCLR_MC1_Pos 17 /**< \brief (TCC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */ 882 #define TCC_INTENCLR_MC1 (1 << TCC_INTENCLR_MC1_Pos) 883 #define TCC_INTENCLR_MC2_Pos 18 /**< \brief (TCC_INTENCLR) Match or Capture Channel 2 Interrupt Enable */ 884 #define TCC_INTENCLR_MC2 (1 << TCC_INTENCLR_MC2_Pos) 885 #define TCC_INTENCLR_MC3_Pos 19 /**< \brief (TCC_INTENCLR) Match or Capture Channel 3 Interrupt Enable */ 886 #define TCC_INTENCLR_MC3 (1 << TCC_INTENCLR_MC3_Pos) 887 #define TCC_INTENCLR_MC_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel x Interrupt Enable */ 888 #define TCC_INTENCLR_MC_Msk (_U_(0xF) << TCC_INTENCLR_MC_Pos) 889 #define TCC_INTENCLR_MC(value) (TCC_INTENCLR_MC_Msk & ((value) << TCC_INTENCLR_MC_Pos)) 890 #define TCC_INTENCLR_MASK _U_(0x000FF80F) /**< \brief (TCC_INTENCLR) MASK Register */ 891 892 /* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */ 893 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 894 typedef union { 895 struct { 896 uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ 897 uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */ 898 uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */ 899 uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */ 900 uint32_t :7; /*!< bit: 4..10 Reserved */ 901 uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */ 902 uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */ 903 uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */ 904 uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */ 905 uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */ 906 uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */ 907 uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */ 908 uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */ 909 uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */ 910 uint32_t :12; /*!< bit: 20..31 Reserved */ 911 } bit; /*!< Structure used for bit access */ 912 struct { 913 uint32_t :16; /*!< bit: 0..15 Reserved */ 914 uint32_t MC:4; /*!< bit: 16..19 Match or Capture Channel x Interrupt Enable */ 915 uint32_t :12; /*!< bit: 20..31 Reserved */ 916 } vec; /*!< Structure used for vec access */ 917 uint32_t reg; /*!< Type used for register access */ 918 } TCC_INTENSET_Type; 919 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 920 921 #define TCC_INTENSET_OFFSET 0x28 /**< \brief (TCC_INTENSET offset) Interrupt Enable Set */ 922 #define TCC_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (TCC_INTENSET reset_value) Interrupt Enable Set */ 923 924 #define TCC_INTENSET_OVF_Pos 0 /**< \brief (TCC_INTENSET) Overflow Interrupt Enable */ 925 #define TCC_INTENSET_OVF (_U_(0x1) << TCC_INTENSET_OVF_Pos) 926 #define TCC_INTENSET_TRG_Pos 1 /**< \brief (TCC_INTENSET) Retrigger Interrupt Enable */ 927 #define TCC_INTENSET_TRG (_U_(0x1) << TCC_INTENSET_TRG_Pos) 928 #define TCC_INTENSET_CNT_Pos 2 /**< \brief (TCC_INTENSET) Counter Interrupt Enable */ 929 #define TCC_INTENSET_CNT (_U_(0x1) << TCC_INTENSET_CNT_Pos) 930 #define TCC_INTENSET_ERR_Pos 3 /**< \brief (TCC_INTENSET) Error Interrupt Enable */ 931 #define TCC_INTENSET_ERR (_U_(0x1) << TCC_INTENSET_ERR_Pos) 932 #define TCC_INTENSET_DFS_Pos 11 /**< \brief (TCC_INTENSET) Non-Recoverable Debug Fault Interrupt Enable */ 933 #define TCC_INTENSET_DFS (_U_(0x1) << TCC_INTENSET_DFS_Pos) 934 #define TCC_INTENSET_FAULTA_Pos 12 /**< \brief (TCC_INTENSET) Recoverable Fault A Interrupt Enable */ 935 #define TCC_INTENSET_FAULTA (_U_(0x1) << TCC_INTENSET_FAULTA_Pos) 936 #define TCC_INTENSET_FAULTB_Pos 13 /**< \brief (TCC_INTENSET) Recoverable Fault B Interrupt Enable */ 937 #define TCC_INTENSET_FAULTB (_U_(0x1) << TCC_INTENSET_FAULTB_Pos) 938 #define TCC_INTENSET_FAULT0_Pos 14 /**< \brief (TCC_INTENSET) Non-Recoverable Fault 0 Interrupt Enable */ 939 #define TCC_INTENSET_FAULT0 (_U_(0x1) << TCC_INTENSET_FAULT0_Pos) 940 #define TCC_INTENSET_FAULT1_Pos 15 /**< \brief (TCC_INTENSET) Non-Recoverable Fault 1 Interrupt Enable */ 941 #define TCC_INTENSET_FAULT1 (_U_(0x1) << TCC_INTENSET_FAULT1_Pos) 942 #define TCC_INTENSET_MC0_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel 0 Interrupt Enable */ 943 #define TCC_INTENSET_MC0 (1 << TCC_INTENSET_MC0_Pos) 944 #define TCC_INTENSET_MC1_Pos 17 /**< \brief (TCC_INTENSET) Match or Capture Channel 1 Interrupt Enable */ 945 #define TCC_INTENSET_MC1 (1 << TCC_INTENSET_MC1_Pos) 946 #define TCC_INTENSET_MC2_Pos 18 /**< \brief (TCC_INTENSET) Match or Capture Channel 2 Interrupt Enable */ 947 #define TCC_INTENSET_MC2 (1 << TCC_INTENSET_MC2_Pos) 948 #define TCC_INTENSET_MC3_Pos 19 /**< \brief (TCC_INTENSET) Match or Capture Channel 3 Interrupt Enable */ 949 #define TCC_INTENSET_MC3 (1 << TCC_INTENSET_MC3_Pos) 950 #define TCC_INTENSET_MC_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel x Interrupt Enable */ 951 #define TCC_INTENSET_MC_Msk (_U_(0xF) << TCC_INTENSET_MC_Pos) 952 #define TCC_INTENSET_MC(value) (TCC_INTENSET_MC_Msk & ((value) << TCC_INTENSET_MC_Pos)) 953 #define TCC_INTENSET_MASK _U_(0x000FF80F) /**< \brief (TCC_INTENSET) MASK Register */ 954 955 /* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */ 956 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 957 typedef union { // __I to avoid read-modify-write on write-to-clear register 958 struct { 959 __I uint32_t OVF:1; /*!< bit: 0 Overflow */ 960 __I uint32_t TRG:1; /*!< bit: 1 Retrigger */ 961 __I uint32_t CNT:1; /*!< bit: 2 Counter */ 962 __I uint32_t ERR:1; /*!< bit: 3 Error */ 963 __I uint32_t Reserved1:7; /*!< bit: 4..10 Reserved */ 964 __I uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */ 965 __I uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */ 966 __I uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */ 967 __I uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */ 968 __I uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */ 969 __I uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */ 970 __I uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */ 971 __I uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */ 972 __I uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */ 973 __I uint32_t Reserved2:12; /*!< bit: 20..31 Reserved */ 974 } bit; /*!< Structure used for bit access */ 975 struct { 976 __I uint32_t Reserved1:16; /*!< bit: 0..15 Reserved */ 977 __I uint32_t MC:4; /*!< bit: 16..19 Match or Capture x */ 978 __I uint32_t Reserved2:12; /*!< bit: 20..31 Reserved */ 979 } vec; /*!< Structure used for vec access */ 980 uint32_t reg; /*!< Type used for register access */ 981 } TCC_INTFLAG_Type; 982 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 983 984 #define TCC_INTFLAG_OFFSET 0x2C /**< \brief (TCC_INTFLAG offset) Interrupt Flag Status and Clear */ 985 #define TCC_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (TCC_INTFLAG reset_value) Interrupt Flag Status and Clear */ 986 987 #define TCC_INTFLAG_OVF_Pos 0 /**< \brief (TCC_INTFLAG) Overflow */ 988 #define TCC_INTFLAG_OVF (_U_(0x1) << TCC_INTFLAG_OVF_Pos) 989 #define TCC_INTFLAG_TRG_Pos 1 /**< \brief (TCC_INTFLAG) Retrigger */ 990 #define TCC_INTFLAG_TRG (_U_(0x1) << TCC_INTFLAG_TRG_Pos) 991 #define TCC_INTFLAG_CNT_Pos 2 /**< \brief (TCC_INTFLAG) Counter */ 992 #define TCC_INTFLAG_CNT (_U_(0x1) << TCC_INTFLAG_CNT_Pos) 993 #define TCC_INTFLAG_ERR_Pos 3 /**< \brief (TCC_INTFLAG) Error */ 994 #define TCC_INTFLAG_ERR (_U_(0x1) << TCC_INTFLAG_ERR_Pos) 995 #define TCC_INTFLAG_DFS_Pos 11 /**< \brief (TCC_INTFLAG) Non-Recoverable Debug Fault */ 996 #define TCC_INTFLAG_DFS (_U_(0x1) << TCC_INTFLAG_DFS_Pos) 997 #define TCC_INTFLAG_FAULTA_Pos 12 /**< \brief (TCC_INTFLAG) Recoverable Fault A */ 998 #define TCC_INTFLAG_FAULTA (_U_(0x1) << TCC_INTFLAG_FAULTA_Pos) 999 #define TCC_INTFLAG_FAULTB_Pos 13 /**< \brief (TCC_INTFLAG) Recoverable Fault B */ 1000 #define TCC_INTFLAG_FAULTB (_U_(0x1) << TCC_INTFLAG_FAULTB_Pos) 1001 #define TCC_INTFLAG_FAULT0_Pos 14 /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 0 */ 1002 #define TCC_INTFLAG_FAULT0 (_U_(0x1) << TCC_INTFLAG_FAULT0_Pos) 1003 #define TCC_INTFLAG_FAULT1_Pos 15 /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 1 */ 1004 #define TCC_INTFLAG_FAULT1 (_U_(0x1) << TCC_INTFLAG_FAULT1_Pos) 1005 #define TCC_INTFLAG_MC0_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture 0 */ 1006 #define TCC_INTFLAG_MC0 (1 << TCC_INTFLAG_MC0_Pos) 1007 #define TCC_INTFLAG_MC1_Pos 17 /**< \brief (TCC_INTFLAG) Match or Capture 1 */ 1008 #define TCC_INTFLAG_MC1 (1 << TCC_INTFLAG_MC1_Pos) 1009 #define TCC_INTFLAG_MC2_Pos 18 /**< \brief (TCC_INTFLAG) Match or Capture 2 */ 1010 #define TCC_INTFLAG_MC2 (1 << TCC_INTFLAG_MC2_Pos) 1011 #define TCC_INTFLAG_MC3_Pos 19 /**< \brief (TCC_INTFLAG) Match or Capture 3 */ 1012 #define TCC_INTFLAG_MC3 (1 << TCC_INTFLAG_MC3_Pos) 1013 #define TCC_INTFLAG_MC_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture x */ 1014 #define TCC_INTFLAG_MC_Msk (_U_(0xF) << TCC_INTFLAG_MC_Pos) 1015 #define TCC_INTFLAG_MC(value) (TCC_INTFLAG_MC_Msk & ((value) << TCC_INTFLAG_MC_Pos)) 1016 #define TCC_INTFLAG_MASK _U_(0x000FF80F) /**< \brief (TCC_INTFLAG) MASK Register */ 1017 1018 /* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */ 1019 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1020 typedef union { 1021 struct { 1022 uint32_t STOP:1; /*!< bit: 0 Stop */ 1023 uint32_t IDX:1; /*!< bit: 1 Ramp */ 1024 uint32_t :1; /*!< bit: 2 Reserved */ 1025 uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */ 1026 uint32_t SLAVE:1; /*!< bit: 4 Slave */ 1027 uint32_t PATTBV:1; /*!< bit: 5 Pattern Buffer Valid */ 1028 uint32_t WAVEBV:1; /*!< bit: 6 Wave Buffer Valid */ 1029 uint32_t PERBV:1; /*!< bit: 7 Period Buffer Valid */ 1030 uint32_t FAULTAIN:1; /*!< bit: 8 Recoverable Fault A Input */ 1031 uint32_t FAULTBIN:1; /*!< bit: 9 Recoverable Fault B Input */ 1032 uint32_t FAULT0IN:1; /*!< bit: 10 Non-Recoverable Fault0 Input */ 1033 uint32_t FAULT1IN:1; /*!< bit: 11 Non-Recoverable Fault1 Input */ 1034 uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A State */ 1035 uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B State */ 1036 uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 State */ 1037 uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 State */ 1038 uint32_t CCBV0:1; /*!< bit: 16 Compare Channel 0 Buffer Valid */ 1039 uint32_t CCBV1:1; /*!< bit: 17 Compare Channel 1 Buffer Valid */ 1040 uint32_t CCBV2:1; /*!< bit: 18 Compare Channel 2 Buffer Valid */ 1041 uint32_t CCBV3:1; /*!< bit: 19 Compare Channel 3 Buffer Valid */ 1042 uint32_t :4; /*!< bit: 20..23 Reserved */ 1043 uint32_t CMP0:1; /*!< bit: 24 Compare Channel 0 Value */ 1044 uint32_t CMP1:1; /*!< bit: 25 Compare Channel 1 Value */ 1045 uint32_t CMP2:1; /*!< bit: 26 Compare Channel 2 Value */ 1046 uint32_t CMP3:1; /*!< bit: 27 Compare Channel 3 Value */ 1047 uint32_t :4; /*!< bit: 28..31 Reserved */ 1048 } bit; /*!< Structure used for bit access */ 1049 struct { 1050 uint32_t :16; /*!< bit: 0..15 Reserved */ 1051 uint32_t CCBV:4; /*!< bit: 16..19 Compare Channel x Buffer Valid */ 1052 uint32_t :4; /*!< bit: 20..23 Reserved */ 1053 uint32_t CMP:4; /*!< bit: 24..27 Compare Channel x Value */ 1054 uint32_t :4; /*!< bit: 28..31 Reserved */ 1055 } vec; /*!< Structure used for vec access */ 1056 uint32_t reg; /*!< Type used for register access */ 1057 } TCC_STATUS_Type; 1058 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1059 1060 #define TCC_STATUS_OFFSET 0x30 /**< \brief (TCC_STATUS offset) Status */ 1061 #define TCC_STATUS_RESETVALUE _U_(0x00000001) /**< \brief (TCC_STATUS reset_value) Status */ 1062 1063 #define TCC_STATUS_STOP_Pos 0 /**< \brief (TCC_STATUS) Stop */ 1064 #define TCC_STATUS_STOP (_U_(0x1) << TCC_STATUS_STOP_Pos) 1065 #define TCC_STATUS_IDX_Pos 1 /**< \brief (TCC_STATUS) Ramp */ 1066 #define TCC_STATUS_IDX (_U_(0x1) << TCC_STATUS_IDX_Pos) 1067 #define TCC_STATUS_DFS_Pos 3 /**< \brief (TCC_STATUS) Non-Recoverable Debug Fault State */ 1068 #define TCC_STATUS_DFS (_U_(0x1) << TCC_STATUS_DFS_Pos) 1069 #define TCC_STATUS_SLAVE_Pos 4 /**< \brief (TCC_STATUS) Slave */ 1070 #define TCC_STATUS_SLAVE (_U_(0x1) << TCC_STATUS_SLAVE_Pos) 1071 #define TCC_STATUS_PATTBV_Pos 5 /**< \brief (TCC_STATUS) Pattern Buffer Valid */ 1072 #define TCC_STATUS_PATTBV (_U_(0x1) << TCC_STATUS_PATTBV_Pos) 1073 #define TCC_STATUS_WAVEBV_Pos 6 /**< \brief (TCC_STATUS) Wave Buffer Valid */ 1074 #define TCC_STATUS_WAVEBV (_U_(0x1) << TCC_STATUS_WAVEBV_Pos) 1075 #define TCC_STATUS_PERBV_Pos 7 /**< \brief (TCC_STATUS) Period Buffer Valid */ 1076 #define TCC_STATUS_PERBV (_U_(0x1) << TCC_STATUS_PERBV_Pos) 1077 #define TCC_STATUS_FAULTAIN_Pos 8 /**< \brief (TCC_STATUS) Recoverable Fault A Input */ 1078 #define TCC_STATUS_FAULTAIN (_U_(0x1) << TCC_STATUS_FAULTAIN_Pos) 1079 #define TCC_STATUS_FAULTBIN_Pos 9 /**< \brief (TCC_STATUS) Recoverable Fault B Input */ 1080 #define TCC_STATUS_FAULTBIN (_U_(0x1) << TCC_STATUS_FAULTBIN_Pos) 1081 #define TCC_STATUS_FAULT0IN_Pos 10 /**< \brief (TCC_STATUS) Non-Recoverable Fault0 Input */ 1082 #define TCC_STATUS_FAULT0IN (_U_(0x1) << TCC_STATUS_FAULT0IN_Pos) 1083 #define TCC_STATUS_FAULT1IN_Pos 11 /**< \brief (TCC_STATUS) Non-Recoverable Fault1 Input */ 1084 #define TCC_STATUS_FAULT1IN (_U_(0x1) << TCC_STATUS_FAULT1IN_Pos) 1085 #define TCC_STATUS_FAULTA_Pos 12 /**< \brief (TCC_STATUS) Recoverable Fault A State */ 1086 #define TCC_STATUS_FAULTA (_U_(0x1) << TCC_STATUS_FAULTA_Pos) 1087 #define TCC_STATUS_FAULTB_Pos 13 /**< \brief (TCC_STATUS) Recoverable Fault B State */ 1088 #define TCC_STATUS_FAULTB (_U_(0x1) << TCC_STATUS_FAULTB_Pos) 1089 #define TCC_STATUS_FAULT0_Pos 14 /**< \brief (TCC_STATUS) Non-Recoverable Fault 0 State */ 1090 #define TCC_STATUS_FAULT0 (_U_(0x1) << TCC_STATUS_FAULT0_Pos) 1091 #define TCC_STATUS_FAULT1_Pos 15 /**< \brief (TCC_STATUS) Non-Recoverable Fault 1 State */ 1092 #define TCC_STATUS_FAULT1 (_U_(0x1) << TCC_STATUS_FAULT1_Pos) 1093 #define TCC_STATUS_CCBV0_Pos 16 /**< \brief (TCC_STATUS) Compare Channel 0 Buffer Valid */ 1094 #define TCC_STATUS_CCBV0 (1 << TCC_STATUS_CCBV0_Pos) 1095 #define TCC_STATUS_CCBV1_Pos 17 /**< \brief (TCC_STATUS) Compare Channel 1 Buffer Valid */ 1096 #define TCC_STATUS_CCBV1 (1 << TCC_STATUS_CCBV1_Pos) 1097 #define TCC_STATUS_CCBV2_Pos 18 /**< \brief (TCC_STATUS) Compare Channel 2 Buffer Valid */ 1098 #define TCC_STATUS_CCBV2 (1 << TCC_STATUS_CCBV2_Pos) 1099 #define TCC_STATUS_CCBV3_Pos 19 /**< \brief (TCC_STATUS) Compare Channel 3 Buffer Valid */ 1100 #define TCC_STATUS_CCBV3 (1 << TCC_STATUS_CCBV3_Pos) 1101 #define TCC_STATUS_CCBV_Pos 16 /**< \brief (TCC_STATUS) Compare Channel x Buffer Valid */ 1102 #define TCC_STATUS_CCBV_Msk (_U_(0xF) << TCC_STATUS_CCBV_Pos) 1103 #define TCC_STATUS_CCBV(value) (TCC_STATUS_CCBV_Msk & ((value) << TCC_STATUS_CCBV_Pos)) 1104 #define TCC_STATUS_CMP0_Pos 24 /**< \brief (TCC_STATUS) Compare Channel 0 Value */ 1105 #define TCC_STATUS_CMP0 (1 << TCC_STATUS_CMP0_Pos) 1106 #define TCC_STATUS_CMP1_Pos 25 /**< \brief (TCC_STATUS) Compare Channel 1 Value */ 1107 #define TCC_STATUS_CMP1 (1 << TCC_STATUS_CMP1_Pos) 1108 #define TCC_STATUS_CMP2_Pos 26 /**< \brief (TCC_STATUS) Compare Channel 2 Value */ 1109 #define TCC_STATUS_CMP2 (1 << TCC_STATUS_CMP2_Pos) 1110 #define TCC_STATUS_CMP3_Pos 27 /**< \brief (TCC_STATUS) Compare Channel 3 Value */ 1111 #define TCC_STATUS_CMP3 (1 << TCC_STATUS_CMP3_Pos) 1112 #define TCC_STATUS_CMP_Pos 24 /**< \brief (TCC_STATUS) Compare Channel x Value */ 1113 #define TCC_STATUS_CMP_Msk (_U_(0xF) << TCC_STATUS_CMP_Pos) 1114 #define TCC_STATUS_CMP(value) (TCC_STATUS_CMP_Msk & ((value) << TCC_STATUS_CMP_Pos)) 1115 #define TCC_STATUS_MASK _U_(0x0F0FFFFB) /**< \brief (TCC_STATUS) MASK Register */ 1116 1117 /* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */ 1118 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1119 typedef union { 1120 struct { // DITH4 mode 1121 uint32_t :4; /*!< bit: 0.. 3 Reserved */ 1122 uint32_t COUNT:20; /*!< bit: 4..23 Counter Value */ 1123 uint32_t :8; /*!< bit: 24..31 Reserved */ 1124 } DITH4; /*!< Structure used for DITH4 */ 1125 struct { // DITH5 mode 1126 uint32_t :5; /*!< bit: 0.. 4 Reserved */ 1127 uint32_t COUNT:19; /*!< bit: 5..23 Counter Value */ 1128 uint32_t :8; /*!< bit: 24..31 Reserved */ 1129 } DITH5; /*!< Structure used for DITH5 */ 1130 struct { // DITH6 mode 1131 uint32_t :6; /*!< bit: 0.. 5 Reserved */ 1132 uint32_t COUNT:18; /*!< bit: 6..23 Counter Value */ 1133 uint32_t :8; /*!< bit: 24..31 Reserved */ 1134 } DITH6; /*!< Structure used for DITH6 */ 1135 struct { 1136 uint32_t COUNT:24; /*!< bit: 0..23 Counter Value */ 1137 uint32_t :8; /*!< bit: 24..31 Reserved */ 1138 } bit; /*!< Structure used for bit access */ 1139 uint32_t reg; /*!< Type used for register access */ 1140 } TCC_COUNT_Type; 1141 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1142 1143 #define TCC_COUNT_OFFSET 0x34 /**< \brief (TCC_COUNT offset) Count */ 1144 #define TCC_COUNT_RESETVALUE _U_(0x00000000) /**< \brief (TCC_COUNT reset_value) Count */ 1145 1146 // DITH4 mode 1147 #define TCC_COUNT_DITH4_COUNT_Pos 4 /**< \brief (TCC_COUNT_DITH4) Counter Value */ 1148 #define TCC_COUNT_DITH4_COUNT_Msk (_U_(0xFFFFF) << TCC_COUNT_DITH4_COUNT_Pos) 1149 #define TCC_COUNT_DITH4_COUNT(value) (TCC_COUNT_DITH4_COUNT_Msk & ((value) << TCC_COUNT_DITH4_COUNT_Pos)) 1150 #define TCC_COUNT_DITH4_MASK _U_(0x00FFFFF0) /**< \brief (TCC_COUNT_DITH4) MASK Register */ 1151 1152 // DITH5 mode 1153 #define TCC_COUNT_DITH5_COUNT_Pos 5 /**< \brief (TCC_COUNT_DITH5) Counter Value */ 1154 #define TCC_COUNT_DITH5_COUNT_Msk (_U_(0x7FFFF) << TCC_COUNT_DITH5_COUNT_Pos) 1155 #define TCC_COUNT_DITH5_COUNT(value) (TCC_COUNT_DITH5_COUNT_Msk & ((value) << TCC_COUNT_DITH5_COUNT_Pos)) 1156 #define TCC_COUNT_DITH5_MASK _U_(0x00FFFFE0) /**< \brief (TCC_COUNT_DITH5) MASK Register */ 1157 1158 // DITH6 mode 1159 #define TCC_COUNT_DITH6_COUNT_Pos 6 /**< \brief (TCC_COUNT_DITH6) Counter Value */ 1160 #define TCC_COUNT_DITH6_COUNT_Msk (_U_(0x3FFFF) << TCC_COUNT_DITH6_COUNT_Pos) 1161 #define TCC_COUNT_DITH6_COUNT(value) (TCC_COUNT_DITH6_COUNT_Msk & ((value) << TCC_COUNT_DITH6_COUNT_Pos)) 1162 #define TCC_COUNT_DITH6_MASK _U_(0x00FFFFC0) /**< \brief (TCC_COUNT_DITH6) MASK Register */ 1163 1164 #define TCC_COUNT_COUNT_Pos 0 /**< \brief (TCC_COUNT) Counter Value */ 1165 #define TCC_COUNT_COUNT_Msk (_U_(0xFFFFFF) << TCC_COUNT_COUNT_Pos) 1166 #define TCC_COUNT_COUNT(value) (TCC_COUNT_COUNT_Msk & ((value) << TCC_COUNT_COUNT_Pos)) 1167 #define TCC_COUNT_MASK _U_(0x00FFFFFF) /**< \brief (TCC_COUNT) MASK Register */ 1168 1169 /* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */ 1170 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1171 typedef union { 1172 struct { 1173 uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */ 1174 uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */ 1175 uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */ 1176 uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */ 1177 uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */ 1178 uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */ 1179 uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */ 1180 uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */ 1181 uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */ 1182 uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */ 1183 uint16_t PGV2:1; /*!< bit: 10 Pattern Generator 2 Output Value */ 1184 uint16_t PGV3:1; /*!< bit: 11 Pattern Generator 3 Output Value */ 1185 uint16_t PGV4:1; /*!< bit: 12 Pattern Generator 4 Output Value */ 1186 uint16_t PGV5:1; /*!< bit: 13 Pattern Generator 5 Output Value */ 1187 uint16_t PGV6:1; /*!< bit: 14 Pattern Generator 6 Output Value */ 1188 uint16_t PGV7:1; /*!< bit: 15 Pattern Generator 7 Output Value */ 1189 } bit; /*!< Structure used for bit access */ 1190 struct { 1191 uint16_t PGE:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable */ 1192 uint16_t PGV:8; /*!< bit: 8..15 Pattern Generator x Output Value */ 1193 } vec; /*!< Structure used for vec access */ 1194 uint16_t reg; /*!< Type used for register access */ 1195 } TCC_PATT_Type; 1196 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1197 1198 #define TCC_PATT_OFFSET 0x38 /**< \brief (TCC_PATT offset) Pattern */ 1199 #define TCC_PATT_RESETVALUE _U_(0x0000) /**< \brief (TCC_PATT reset_value) Pattern */ 1200 1201 #define TCC_PATT_PGE0_Pos 0 /**< \brief (TCC_PATT) Pattern Generator 0 Output Enable */ 1202 #define TCC_PATT_PGE0 (1 << TCC_PATT_PGE0_Pos) 1203 #define TCC_PATT_PGE1_Pos 1 /**< \brief (TCC_PATT) Pattern Generator 1 Output Enable */ 1204 #define TCC_PATT_PGE1 (1 << TCC_PATT_PGE1_Pos) 1205 #define TCC_PATT_PGE2_Pos 2 /**< \brief (TCC_PATT) Pattern Generator 2 Output Enable */ 1206 #define TCC_PATT_PGE2 (1 << TCC_PATT_PGE2_Pos) 1207 #define TCC_PATT_PGE3_Pos 3 /**< \brief (TCC_PATT) Pattern Generator 3 Output Enable */ 1208 #define TCC_PATT_PGE3 (1 << TCC_PATT_PGE3_Pos) 1209 #define TCC_PATT_PGE4_Pos 4 /**< \brief (TCC_PATT) Pattern Generator 4 Output Enable */ 1210 #define TCC_PATT_PGE4 (1 << TCC_PATT_PGE4_Pos) 1211 #define TCC_PATT_PGE5_Pos 5 /**< \brief (TCC_PATT) Pattern Generator 5 Output Enable */ 1212 #define TCC_PATT_PGE5 (1 << TCC_PATT_PGE5_Pos) 1213 #define TCC_PATT_PGE6_Pos 6 /**< \brief (TCC_PATT) Pattern Generator 6 Output Enable */ 1214 #define TCC_PATT_PGE6 (1 << TCC_PATT_PGE6_Pos) 1215 #define TCC_PATT_PGE7_Pos 7 /**< \brief (TCC_PATT) Pattern Generator 7 Output Enable */ 1216 #define TCC_PATT_PGE7 (1 << TCC_PATT_PGE7_Pos) 1217 #define TCC_PATT_PGE_Pos 0 /**< \brief (TCC_PATT) Pattern Generator x Output Enable */ 1218 #define TCC_PATT_PGE_Msk (_U_(0xFF) << TCC_PATT_PGE_Pos) 1219 #define TCC_PATT_PGE(value) (TCC_PATT_PGE_Msk & ((value) << TCC_PATT_PGE_Pos)) 1220 #define TCC_PATT_PGV0_Pos 8 /**< \brief (TCC_PATT) Pattern Generator 0 Output Value */ 1221 #define TCC_PATT_PGV0 (1 << TCC_PATT_PGV0_Pos) 1222 #define TCC_PATT_PGV1_Pos 9 /**< \brief (TCC_PATT) Pattern Generator 1 Output Value */ 1223 #define TCC_PATT_PGV1 (1 << TCC_PATT_PGV1_Pos) 1224 #define TCC_PATT_PGV2_Pos 10 /**< \brief (TCC_PATT) Pattern Generator 2 Output Value */ 1225 #define TCC_PATT_PGV2 (1 << TCC_PATT_PGV2_Pos) 1226 #define TCC_PATT_PGV3_Pos 11 /**< \brief (TCC_PATT) Pattern Generator 3 Output Value */ 1227 #define TCC_PATT_PGV3 (1 << TCC_PATT_PGV3_Pos) 1228 #define TCC_PATT_PGV4_Pos 12 /**< \brief (TCC_PATT) Pattern Generator 4 Output Value */ 1229 #define TCC_PATT_PGV4 (1 << TCC_PATT_PGV4_Pos) 1230 #define TCC_PATT_PGV5_Pos 13 /**< \brief (TCC_PATT) Pattern Generator 5 Output Value */ 1231 #define TCC_PATT_PGV5 (1 << TCC_PATT_PGV5_Pos) 1232 #define TCC_PATT_PGV6_Pos 14 /**< \brief (TCC_PATT) Pattern Generator 6 Output Value */ 1233 #define TCC_PATT_PGV6 (1 << TCC_PATT_PGV6_Pos) 1234 #define TCC_PATT_PGV7_Pos 15 /**< \brief (TCC_PATT) Pattern Generator 7 Output Value */ 1235 #define TCC_PATT_PGV7 (1 << TCC_PATT_PGV7_Pos) 1236 #define TCC_PATT_PGV_Pos 8 /**< \brief (TCC_PATT) Pattern Generator x Output Value */ 1237 #define TCC_PATT_PGV_Msk (_U_(0xFF) << TCC_PATT_PGV_Pos) 1238 #define TCC_PATT_PGV(value) (TCC_PATT_PGV_Msk & ((value) << TCC_PATT_PGV_Pos)) 1239 #define TCC_PATT_MASK _U_(0xFFFF) /**< \brief (TCC_PATT) MASK Register */ 1240 1241 /* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */ 1242 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1243 typedef union { 1244 struct { 1245 uint32_t WAVEGEN:3; /*!< bit: 0.. 2 Waveform Generation */ 1246 uint32_t :1; /*!< bit: 3 Reserved */ 1247 uint32_t RAMP:2; /*!< bit: 4.. 5 Ramp Mode */ 1248 uint32_t :1; /*!< bit: 6 Reserved */ 1249 uint32_t CIPEREN:1; /*!< bit: 7 Circular period Enable */ 1250 uint32_t CICCEN0:1; /*!< bit: 8 Circular Channel 0 Enable */ 1251 uint32_t CICCEN1:1; /*!< bit: 9 Circular Channel 1 Enable */ 1252 uint32_t CICCEN2:1; /*!< bit: 10 Circular Channel 2 Enable */ 1253 uint32_t CICCEN3:1; /*!< bit: 11 Circular Channel 3 Enable */ 1254 uint32_t :4; /*!< bit: 12..15 Reserved */ 1255 uint32_t POL0:1; /*!< bit: 16 Channel 0 Polarity */ 1256 uint32_t POL1:1; /*!< bit: 17 Channel 1 Polarity */ 1257 uint32_t POL2:1; /*!< bit: 18 Channel 2 Polarity */ 1258 uint32_t POL3:1; /*!< bit: 19 Channel 3 Polarity */ 1259 uint32_t :4; /*!< bit: 20..23 Reserved */ 1260 uint32_t SWAP0:1; /*!< bit: 24 Swap DTI Output Pair 0 */ 1261 uint32_t SWAP1:1; /*!< bit: 25 Swap DTI Output Pair 1 */ 1262 uint32_t SWAP2:1; /*!< bit: 26 Swap DTI Output Pair 2 */ 1263 uint32_t SWAP3:1; /*!< bit: 27 Swap DTI Output Pair 3 */ 1264 uint32_t :4; /*!< bit: 28..31 Reserved */ 1265 } bit; /*!< Structure used for bit access */ 1266 struct { 1267 uint32_t :8; /*!< bit: 0.. 7 Reserved */ 1268 uint32_t CICCEN:4; /*!< bit: 8..11 Circular Channel x Enable */ 1269 uint32_t :4; /*!< bit: 12..15 Reserved */ 1270 uint32_t POL:4; /*!< bit: 16..19 Channel x Polarity */ 1271 uint32_t :4; /*!< bit: 20..23 Reserved */ 1272 uint32_t SWAP:4; /*!< bit: 24..27 Swap DTI Output Pair x */ 1273 uint32_t :4; /*!< bit: 28..31 Reserved */ 1274 } vec; /*!< Structure used for vec access */ 1275 uint32_t reg; /*!< Type used for register access */ 1276 } TCC_WAVE_Type; 1277 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1278 1279 #define TCC_WAVE_OFFSET 0x3C /**< \brief (TCC_WAVE offset) Waveform Control */ 1280 #define TCC_WAVE_RESETVALUE _U_(0x00000000) /**< \brief (TCC_WAVE reset_value) Waveform Control */ 1281 1282 #define TCC_WAVE_WAVEGEN_Pos 0 /**< \brief (TCC_WAVE) Waveform Generation */ 1283 #define TCC_WAVE_WAVEGEN_Msk (_U_(0x7) << TCC_WAVE_WAVEGEN_Pos) 1284 #define TCC_WAVE_WAVEGEN(value) (TCC_WAVE_WAVEGEN_Msk & ((value) << TCC_WAVE_WAVEGEN_Pos)) 1285 #define TCC_WAVE_WAVEGEN_NFRQ_Val _U_(0x0) /**< \brief (TCC_WAVE) Normal frequency */ 1286 #define TCC_WAVE_WAVEGEN_MFRQ_Val _U_(0x1) /**< \brief (TCC_WAVE) Match frequency */ 1287 #define TCC_WAVE_WAVEGEN_NPWM_Val _U_(0x2) /**< \brief (TCC_WAVE) Normal PWM */ 1288 #define TCC_WAVE_WAVEGEN_DSCRITICAL_Val _U_(0x4) /**< \brief (TCC_WAVE) Dual-slope critical */ 1289 #define TCC_WAVE_WAVEGEN_DSBOTTOM_Val _U_(0x5) /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO */ 1290 #define TCC_WAVE_WAVEGEN_DSBOTH_Val _U_(0x6) /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */ 1291 #define TCC_WAVE_WAVEGEN_DSTOP_Val _U_(0x7) /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches TOP */ 1292 #define TCC_WAVE_WAVEGEN_NFRQ (TCC_WAVE_WAVEGEN_NFRQ_Val << TCC_WAVE_WAVEGEN_Pos) 1293 #define TCC_WAVE_WAVEGEN_MFRQ (TCC_WAVE_WAVEGEN_MFRQ_Val << TCC_WAVE_WAVEGEN_Pos) 1294 #define TCC_WAVE_WAVEGEN_NPWM (TCC_WAVE_WAVEGEN_NPWM_Val << TCC_WAVE_WAVEGEN_Pos) 1295 #define TCC_WAVE_WAVEGEN_DSCRITICAL (TCC_WAVE_WAVEGEN_DSCRITICAL_Val << TCC_WAVE_WAVEGEN_Pos) 1296 #define TCC_WAVE_WAVEGEN_DSBOTTOM (TCC_WAVE_WAVEGEN_DSBOTTOM_Val << TCC_WAVE_WAVEGEN_Pos) 1297 #define TCC_WAVE_WAVEGEN_DSBOTH (TCC_WAVE_WAVEGEN_DSBOTH_Val << TCC_WAVE_WAVEGEN_Pos) 1298 #define TCC_WAVE_WAVEGEN_DSTOP (TCC_WAVE_WAVEGEN_DSTOP_Val << TCC_WAVE_WAVEGEN_Pos) 1299 #define TCC_WAVE_RAMP_Pos 4 /**< \brief (TCC_WAVE) Ramp Mode */ 1300 #define TCC_WAVE_RAMP_Msk (_U_(0x3) << TCC_WAVE_RAMP_Pos) 1301 #define TCC_WAVE_RAMP(value) (TCC_WAVE_RAMP_Msk & ((value) << TCC_WAVE_RAMP_Pos)) 1302 #define TCC_WAVE_RAMP_RAMP1_Val _U_(0x0) /**< \brief (TCC_WAVE) RAMP1 operation */ 1303 #define TCC_WAVE_RAMP_RAMP2A_Val _U_(0x1) /**< \brief (TCC_WAVE) Alternative RAMP2 operation */ 1304 #define TCC_WAVE_RAMP_RAMP2_Val _U_(0x2) /**< \brief (TCC_WAVE) RAMP2 operation */ 1305 #define TCC_WAVE_RAMP_RAMP1 (TCC_WAVE_RAMP_RAMP1_Val << TCC_WAVE_RAMP_Pos) 1306 #define TCC_WAVE_RAMP_RAMP2A (TCC_WAVE_RAMP_RAMP2A_Val << TCC_WAVE_RAMP_Pos) 1307 #define TCC_WAVE_RAMP_RAMP2 (TCC_WAVE_RAMP_RAMP2_Val << TCC_WAVE_RAMP_Pos) 1308 #define TCC_WAVE_CIPEREN_Pos 7 /**< \brief (TCC_WAVE) Circular period Enable */ 1309 #define TCC_WAVE_CIPEREN (_U_(0x1) << TCC_WAVE_CIPEREN_Pos) 1310 #define TCC_WAVE_CICCEN0_Pos 8 /**< \brief (TCC_WAVE) Circular Channel 0 Enable */ 1311 #define TCC_WAVE_CICCEN0 (1 << TCC_WAVE_CICCEN0_Pos) 1312 #define TCC_WAVE_CICCEN1_Pos 9 /**< \brief (TCC_WAVE) Circular Channel 1 Enable */ 1313 #define TCC_WAVE_CICCEN1 (1 << TCC_WAVE_CICCEN1_Pos) 1314 #define TCC_WAVE_CICCEN2_Pos 10 /**< \brief (TCC_WAVE) Circular Channel 2 Enable */ 1315 #define TCC_WAVE_CICCEN2 (1 << TCC_WAVE_CICCEN2_Pos) 1316 #define TCC_WAVE_CICCEN3_Pos 11 /**< \brief (TCC_WAVE) Circular Channel 3 Enable */ 1317 #define TCC_WAVE_CICCEN3 (1 << TCC_WAVE_CICCEN3_Pos) 1318 #define TCC_WAVE_CICCEN_Pos 8 /**< \brief (TCC_WAVE) Circular Channel x Enable */ 1319 #define TCC_WAVE_CICCEN_Msk (_U_(0xF) << TCC_WAVE_CICCEN_Pos) 1320 #define TCC_WAVE_CICCEN(value) (TCC_WAVE_CICCEN_Msk & ((value) << TCC_WAVE_CICCEN_Pos)) 1321 #define TCC_WAVE_POL0_Pos 16 /**< \brief (TCC_WAVE) Channel 0 Polarity */ 1322 #define TCC_WAVE_POL0 (1 << TCC_WAVE_POL0_Pos) 1323 #define TCC_WAVE_POL1_Pos 17 /**< \brief (TCC_WAVE) Channel 1 Polarity */ 1324 #define TCC_WAVE_POL1 (1 << TCC_WAVE_POL1_Pos) 1325 #define TCC_WAVE_POL2_Pos 18 /**< \brief (TCC_WAVE) Channel 2 Polarity */ 1326 #define TCC_WAVE_POL2 (1 << TCC_WAVE_POL2_Pos) 1327 #define TCC_WAVE_POL3_Pos 19 /**< \brief (TCC_WAVE) Channel 3 Polarity */ 1328 #define TCC_WAVE_POL3 (1 << TCC_WAVE_POL3_Pos) 1329 #define TCC_WAVE_POL_Pos 16 /**< \brief (TCC_WAVE) Channel x Polarity */ 1330 #define TCC_WAVE_POL_Msk (_U_(0xF) << TCC_WAVE_POL_Pos) 1331 #define TCC_WAVE_POL(value) (TCC_WAVE_POL_Msk & ((value) << TCC_WAVE_POL_Pos)) 1332 #define TCC_WAVE_SWAP0_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair 0 */ 1333 #define TCC_WAVE_SWAP0 (1 << TCC_WAVE_SWAP0_Pos) 1334 #define TCC_WAVE_SWAP1_Pos 25 /**< \brief (TCC_WAVE) Swap DTI Output Pair 1 */ 1335 #define TCC_WAVE_SWAP1 (1 << TCC_WAVE_SWAP1_Pos) 1336 #define TCC_WAVE_SWAP2_Pos 26 /**< \brief (TCC_WAVE) Swap DTI Output Pair 2 */ 1337 #define TCC_WAVE_SWAP2 (1 << TCC_WAVE_SWAP2_Pos) 1338 #define TCC_WAVE_SWAP3_Pos 27 /**< \brief (TCC_WAVE) Swap DTI Output Pair 3 */ 1339 #define TCC_WAVE_SWAP3 (1 << TCC_WAVE_SWAP3_Pos) 1340 #define TCC_WAVE_SWAP_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair x */ 1341 #define TCC_WAVE_SWAP_Msk (_U_(0xF) << TCC_WAVE_SWAP_Pos) 1342 #define TCC_WAVE_SWAP(value) (TCC_WAVE_SWAP_Msk & ((value) << TCC_WAVE_SWAP_Pos)) 1343 #define TCC_WAVE_MASK _U_(0x0F0F0FB7) /**< \brief (TCC_WAVE) MASK Register */ 1344 1345 /* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */ 1346 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1347 typedef union { 1348 struct { // DITH4 mode 1349 uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */ 1350 uint32_t PER:20; /*!< bit: 4..23 Period Value */ 1351 uint32_t :8; /*!< bit: 24..31 Reserved */ 1352 } DITH4; /*!< Structure used for DITH4 */ 1353 struct { // DITH5 mode 1354 uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */ 1355 uint32_t PER:19; /*!< bit: 5..23 Period Value */ 1356 uint32_t :8; /*!< bit: 24..31 Reserved */ 1357 } DITH5; /*!< Structure used for DITH5 */ 1358 struct { // DITH6 mode 1359 uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */ 1360 uint32_t PER:18; /*!< bit: 6..23 Period Value */ 1361 uint32_t :8; /*!< bit: 24..31 Reserved */ 1362 } DITH6; /*!< Structure used for DITH6 */ 1363 struct { 1364 uint32_t PER:24; /*!< bit: 0..23 Period Value */ 1365 uint32_t :8; /*!< bit: 24..31 Reserved */ 1366 } bit; /*!< Structure used for bit access */ 1367 uint32_t reg; /*!< Type used for register access */ 1368 } TCC_PER_Type; 1369 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1370 1371 #define TCC_PER_OFFSET 0x40 /**< \brief (TCC_PER offset) Period */ 1372 #define TCC_PER_RESETVALUE _U_(0xFFFFFFFF) /**< \brief (TCC_PER reset_value) Period */ 1373 1374 // DITH4 mode 1375 #define TCC_PER_DITH4_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH4) Dithering Cycle Number */ 1376 #define TCC_PER_DITH4_DITHERCY_Msk (_U_(0xF) << TCC_PER_DITH4_DITHERCY_Pos) 1377 #define TCC_PER_DITH4_DITHERCY(value) (TCC_PER_DITH4_DITHERCY_Msk & ((value) << TCC_PER_DITH4_DITHERCY_Pos)) 1378 #define TCC_PER_DITH4_PER_Pos 4 /**< \brief (TCC_PER_DITH4) Period Value */ 1379 #define TCC_PER_DITH4_PER_Msk (_U_(0xFFFFF) << TCC_PER_DITH4_PER_Pos) 1380 #define TCC_PER_DITH4_PER(value) (TCC_PER_DITH4_PER_Msk & ((value) << TCC_PER_DITH4_PER_Pos)) 1381 #define TCC_PER_DITH4_MASK _U_(0x00FFFFFF) /**< \brief (TCC_PER_DITH4) MASK Register */ 1382 1383 // DITH5 mode 1384 #define TCC_PER_DITH5_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH5) Dithering Cycle Number */ 1385 #define TCC_PER_DITH5_DITHERCY_Msk (_U_(0x1F) << TCC_PER_DITH5_DITHERCY_Pos) 1386 #define TCC_PER_DITH5_DITHERCY(value) (TCC_PER_DITH5_DITHERCY_Msk & ((value) << TCC_PER_DITH5_DITHERCY_Pos)) 1387 #define TCC_PER_DITH5_PER_Pos 5 /**< \brief (TCC_PER_DITH5) Period Value */ 1388 #define TCC_PER_DITH5_PER_Msk (_U_(0x7FFFF) << TCC_PER_DITH5_PER_Pos) 1389 #define TCC_PER_DITH5_PER(value) (TCC_PER_DITH5_PER_Msk & ((value) << TCC_PER_DITH5_PER_Pos)) 1390 #define TCC_PER_DITH5_MASK _U_(0x00FFFFFF) /**< \brief (TCC_PER_DITH5) MASK Register */ 1391 1392 // DITH6 mode 1393 #define TCC_PER_DITH6_DITHERCY_Pos 0 /**< \brief (TCC_PER_DITH6) Dithering Cycle Number */ 1394 #define TCC_PER_DITH6_DITHERCY_Msk (_U_(0x3F) << TCC_PER_DITH6_DITHERCY_Pos) 1395 #define TCC_PER_DITH6_DITHERCY(value) (TCC_PER_DITH6_DITHERCY_Msk & ((value) << TCC_PER_DITH6_DITHERCY_Pos)) 1396 #define TCC_PER_DITH6_PER_Pos 6 /**< \brief (TCC_PER_DITH6) Period Value */ 1397 #define TCC_PER_DITH6_PER_Msk (_U_(0x3FFFF) << TCC_PER_DITH6_PER_Pos) 1398 #define TCC_PER_DITH6_PER(value) (TCC_PER_DITH6_PER_Msk & ((value) << TCC_PER_DITH6_PER_Pos)) 1399 #define TCC_PER_DITH6_MASK _U_(0x00FFFFFF) /**< \brief (TCC_PER_DITH6) MASK Register */ 1400 1401 #define TCC_PER_PER_Pos 0 /**< \brief (TCC_PER) Period Value */ 1402 #define TCC_PER_PER_Msk (_U_(0xFFFFFF) << TCC_PER_PER_Pos) 1403 #define TCC_PER_PER(value) (TCC_PER_PER_Msk & ((value) << TCC_PER_PER_Pos)) 1404 #define TCC_PER_MASK _U_(0x00FFFFFF) /**< \brief (TCC_PER) MASK Register */ 1405 1406 /* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */ 1407 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1408 typedef union { 1409 struct { // DITH4 mode 1410 uint32_t DITHERCY:4; /*!< bit: 0.. 3 Dithering Cycle Number */ 1411 uint32_t CC:20; /*!< bit: 4..23 Channel Compare/Capture Value */ 1412 uint32_t :8; /*!< bit: 24..31 Reserved */ 1413 } DITH4; /*!< Structure used for DITH4 */ 1414 struct { // DITH5 mode 1415 uint32_t DITHERCY:5; /*!< bit: 0.. 4 Dithering Cycle Number */ 1416 uint32_t CC:19; /*!< bit: 5..23 Channel Compare/Capture Value */ 1417 uint32_t :8; /*!< bit: 24..31 Reserved */ 1418 } DITH5; /*!< Structure used for DITH5 */ 1419 struct { // DITH6 mode 1420 uint32_t DITHERCY:6; /*!< bit: 0.. 5 Dithering Cycle Number */ 1421 uint32_t CC:18; /*!< bit: 6..23 Channel Compare/Capture Value */ 1422 uint32_t :8; /*!< bit: 24..31 Reserved */ 1423 } DITH6; /*!< Structure used for DITH6 */ 1424 struct { 1425 uint32_t CC:24; /*!< bit: 0..23 Channel Compare/Capture Value */ 1426 uint32_t :8; /*!< bit: 24..31 Reserved */ 1427 } bit; /*!< Structure used for bit access */ 1428 uint32_t reg; /*!< Type used for register access */ 1429 } TCC_CC_Type; 1430 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1431 1432 #define TCC_CC_OFFSET 0x44 /**< \brief (TCC_CC offset) Compare and Capture */ 1433 #define TCC_CC_RESETVALUE _U_(0x00000000) /**< \brief (TCC_CC reset_value) Compare and Capture */ 1434 1435 // DITH4 mode 1436 #define TCC_CC_DITH4_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH4) Dithering Cycle Number */ 1437 #define TCC_CC_DITH4_DITHERCY_Msk (_U_(0xF) << TCC_CC_DITH4_DITHERCY_Pos) 1438 #define TCC_CC_DITH4_DITHERCY(value) (TCC_CC_DITH4_DITHERCY_Msk & ((value) << TCC_CC_DITH4_DITHERCY_Pos)) 1439 #define TCC_CC_DITH4_CC_Pos 4 /**< \brief (TCC_CC_DITH4) Channel Compare/Capture Value */ 1440 #define TCC_CC_DITH4_CC_Msk (_U_(0xFFFFF) << TCC_CC_DITH4_CC_Pos) 1441 #define TCC_CC_DITH4_CC(value) (TCC_CC_DITH4_CC_Msk & ((value) << TCC_CC_DITH4_CC_Pos)) 1442 #define TCC_CC_DITH4_MASK _U_(0x00FFFFFF) /**< \brief (TCC_CC_DITH4) MASK Register */ 1443 1444 // DITH5 mode 1445 #define TCC_CC_DITH5_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH5) Dithering Cycle Number */ 1446 #define TCC_CC_DITH5_DITHERCY_Msk (_U_(0x1F) << TCC_CC_DITH5_DITHERCY_Pos) 1447 #define TCC_CC_DITH5_DITHERCY(value) (TCC_CC_DITH5_DITHERCY_Msk & ((value) << TCC_CC_DITH5_DITHERCY_Pos)) 1448 #define TCC_CC_DITH5_CC_Pos 5 /**< \brief (TCC_CC_DITH5) Channel Compare/Capture Value */ 1449 #define TCC_CC_DITH5_CC_Msk (_U_(0x7FFFF) << TCC_CC_DITH5_CC_Pos) 1450 #define TCC_CC_DITH5_CC(value) (TCC_CC_DITH5_CC_Msk & ((value) << TCC_CC_DITH5_CC_Pos)) 1451 #define TCC_CC_DITH5_MASK _U_(0x00FFFFFF) /**< \brief (TCC_CC_DITH5) MASK Register */ 1452 1453 // DITH6 mode 1454 #define TCC_CC_DITH6_DITHERCY_Pos 0 /**< \brief (TCC_CC_DITH6) Dithering Cycle Number */ 1455 #define TCC_CC_DITH6_DITHERCY_Msk (_U_(0x3F) << TCC_CC_DITH6_DITHERCY_Pos) 1456 #define TCC_CC_DITH6_DITHERCY(value) (TCC_CC_DITH6_DITHERCY_Msk & ((value) << TCC_CC_DITH6_DITHERCY_Pos)) 1457 #define TCC_CC_DITH6_CC_Pos 6 /**< \brief (TCC_CC_DITH6) Channel Compare/Capture Value */ 1458 #define TCC_CC_DITH6_CC_Msk (_U_(0x3FFFF) << TCC_CC_DITH6_CC_Pos) 1459 #define TCC_CC_DITH6_CC(value) (TCC_CC_DITH6_CC_Msk & ((value) << TCC_CC_DITH6_CC_Pos)) 1460 #define TCC_CC_DITH6_MASK _U_(0x00FFFFFF) /**< \brief (TCC_CC_DITH6) MASK Register */ 1461 1462 #define TCC_CC_CC_Pos 0 /**< \brief (TCC_CC) Channel Compare/Capture Value */ 1463 #define TCC_CC_CC_Msk (_U_(0xFFFFFF) << TCC_CC_CC_Pos) 1464 #define TCC_CC_CC(value) (TCC_CC_CC_Msk & ((value) << TCC_CC_CC_Pos)) 1465 #define TCC_CC_MASK _U_(0x00FFFFFF) /**< \brief (TCC_CC) MASK Register */ 1466 1467 /* -------- TCC_PATTB : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */ 1468 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1469 typedef union { 1470 struct { 1471 uint16_t PGEB0:1; /*!< bit: 0 Pattern Generator 0 Output Enable Buffer */ 1472 uint16_t PGEB1:1; /*!< bit: 1 Pattern Generator 1 Output Enable Buffer */ 1473 uint16_t PGEB2:1; /*!< bit: 2 Pattern Generator 2 Output Enable Buffer */ 1474 uint16_t PGEB3:1; /*!< bit: 3 Pattern Generator 3 Output Enable Buffer */ 1475 uint16_t PGEB4:1; /*!< bit: 4 Pattern Generator 4 Output Enable Buffer */ 1476 uint16_t PGEB5:1; /*!< bit: 5 Pattern Generator 5 Output Enable Buffer */ 1477 uint16_t PGEB6:1; /*!< bit: 6 Pattern Generator 6 Output Enable Buffer */ 1478 uint16_t PGEB7:1; /*!< bit: 7 Pattern Generator 7 Output Enable Buffer */ 1479 uint16_t PGVB0:1; /*!< bit: 8 Pattern Generator 0 Output Enable */ 1480 uint16_t PGVB1:1; /*!< bit: 9 Pattern Generator 1 Output Enable */ 1481 uint16_t PGVB2:1; /*!< bit: 10 Pattern Generator 2 Output Enable */ 1482 uint16_t PGVB3:1; /*!< bit: 11 Pattern Generator 3 Output Enable */ 1483 uint16_t PGVB4:1; /*!< bit: 12 Pattern Generator 4 Output Enable */ 1484 uint16_t PGVB5:1; /*!< bit: 13 Pattern Generator 5 Output Enable */ 1485 uint16_t PGVB6:1; /*!< bit: 14 Pattern Generator 6 Output Enable */ 1486 uint16_t PGVB7:1; /*!< bit: 15 Pattern Generator 7 Output Enable */ 1487 } bit; /*!< Structure used for bit access */ 1488 struct { 1489 uint16_t PGEB:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable Buffer */ 1490 uint16_t PGVB:8; /*!< bit: 8..15 Pattern Generator x Output Enable */ 1491 } vec; /*!< Structure used for vec access */ 1492 uint16_t reg; /*!< Type used for register access */ 1493 } TCC_PATTB_Type; 1494 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1495 1496 #define TCC_PATTB_OFFSET 0x64 /**< \brief (TCC_PATTB offset) Pattern Buffer */ 1497 #define TCC_PATTB_RESETVALUE _U_(0x0000) /**< \brief (TCC_PATTB reset_value) Pattern Buffer */ 1498 1499 #define TCC_PATTB_PGEB0_Pos 0 /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable Buffer */ 1500 #define TCC_PATTB_PGEB0 (1 << TCC_PATTB_PGEB0_Pos) 1501 #define TCC_PATTB_PGEB1_Pos 1 /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable Buffer */ 1502 #define TCC_PATTB_PGEB1 (1 << TCC_PATTB_PGEB1_Pos) 1503 #define TCC_PATTB_PGEB2_Pos 2 /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable Buffer */ 1504 #define TCC_PATTB_PGEB2 (1 << TCC_PATTB_PGEB2_Pos) 1505 #define TCC_PATTB_PGEB3_Pos 3 /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable Buffer */ 1506 #define TCC_PATTB_PGEB3 (1 << TCC_PATTB_PGEB3_Pos) 1507 #define TCC_PATTB_PGEB4_Pos 4 /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable Buffer */ 1508 #define TCC_PATTB_PGEB4 (1 << TCC_PATTB_PGEB4_Pos) 1509 #define TCC_PATTB_PGEB5_Pos 5 /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable Buffer */ 1510 #define TCC_PATTB_PGEB5 (1 << TCC_PATTB_PGEB5_Pos) 1511 #define TCC_PATTB_PGEB6_Pos 6 /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable Buffer */ 1512 #define TCC_PATTB_PGEB6 (1 << TCC_PATTB_PGEB6_Pos) 1513 #define TCC_PATTB_PGEB7_Pos 7 /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable Buffer */ 1514 #define TCC_PATTB_PGEB7 (1 << TCC_PATTB_PGEB7_Pos) 1515 #define TCC_PATTB_PGEB_Pos 0 /**< \brief (TCC_PATTB) Pattern Generator x Output Enable Buffer */ 1516 #define TCC_PATTB_PGEB_Msk (_U_(0xFF) << TCC_PATTB_PGEB_Pos) 1517 #define TCC_PATTB_PGEB(value) (TCC_PATTB_PGEB_Msk & ((value) << TCC_PATTB_PGEB_Pos)) 1518 #define TCC_PATTB_PGVB0_Pos 8 /**< \brief (TCC_PATTB) Pattern Generator 0 Output Enable */ 1519 #define TCC_PATTB_PGVB0 (1 << TCC_PATTB_PGVB0_Pos) 1520 #define TCC_PATTB_PGVB1_Pos 9 /**< \brief (TCC_PATTB) Pattern Generator 1 Output Enable */ 1521 #define TCC_PATTB_PGVB1 (1 << TCC_PATTB_PGVB1_Pos) 1522 #define TCC_PATTB_PGVB2_Pos 10 /**< \brief (TCC_PATTB) Pattern Generator 2 Output Enable */ 1523 #define TCC_PATTB_PGVB2 (1 << TCC_PATTB_PGVB2_Pos) 1524 #define TCC_PATTB_PGVB3_Pos 11 /**< \brief (TCC_PATTB) Pattern Generator 3 Output Enable */ 1525 #define TCC_PATTB_PGVB3 (1 << TCC_PATTB_PGVB3_Pos) 1526 #define TCC_PATTB_PGVB4_Pos 12 /**< \brief (TCC_PATTB) Pattern Generator 4 Output Enable */ 1527 #define TCC_PATTB_PGVB4 (1 << TCC_PATTB_PGVB4_Pos) 1528 #define TCC_PATTB_PGVB5_Pos 13 /**< \brief (TCC_PATTB) Pattern Generator 5 Output Enable */ 1529 #define TCC_PATTB_PGVB5 (1 << TCC_PATTB_PGVB5_Pos) 1530 #define TCC_PATTB_PGVB6_Pos 14 /**< \brief (TCC_PATTB) Pattern Generator 6 Output Enable */ 1531 #define TCC_PATTB_PGVB6 (1 << TCC_PATTB_PGVB6_Pos) 1532 #define TCC_PATTB_PGVB7_Pos 15 /**< \brief (TCC_PATTB) Pattern Generator 7 Output Enable */ 1533 #define TCC_PATTB_PGVB7 (1 << TCC_PATTB_PGVB7_Pos) 1534 #define TCC_PATTB_PGVB_Pos 8 /**< \brief (TCC_PATTB) Pattern Generator x Output Enable */ 1535 #define TCC_PATTB_PGVB_Msk (_U_(0xFF) << TCC_PATTB_PGVB_Pos) 1536 #define TCC_PATTB_PGVB(value) (TCC_PATTB_PGVB_Msk & ((value) << TCC_PATTB_PGVB_Pos)) 1537 #define TCC_PATTB_MASK _U_(0xFFFF) /**< \brief (TCC_PATTB) MASK Register */ 1538 1539 /* -------- TCC_WAVEB : (TCC Offset: 0x68) (R/W 32) Waveform Control Buffer -------- */ 1540 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1541 typedef union { 1542 struct { 1543 uint32_t WAVEGENB:3; /*!< bit: 0.. 2 Waveform Generation Buffer */ 1544 uint32_t :1; /*!< bit: 3 Reserved */ 1545 uint32_t RAMPB:2; /*!< bit: 4.. 5 Ramp Mode Buffer */ 1546 uint32_t :1; /*!< bit: 6 Reserved */ 1547 uint32_t CIPERENB:1; /*!< bit: 7 Circular Period Enable Buffer */ 1548 uint32_t CICCENB0:1; /*!< bit: 8 Circular Channel 0 Enable Buffer */ 1549 uint32_t CICCENB1:1; /*!< bit: 9 Circular Channel 1 Enable Buffer */ 1550 uint32_t CICCENB2:1; /*!< bit: 10 Circular Channel 2 Enable Buffer */ 1551 uint32_t CICCENB3:1; /*!< bit: 11 Circular Channel 3 Enable Buffer */ 1552 uint32_t :4; /*!< bit: 12..15 Reserved */ 1553 uint32_t POLB0:1; /*!< bit: 16 Channel 0 Polarity Buffer */ 1554 uint32_t POLB1:1; /*!< bit: 17 Channel 1 Polarity Buffer */ 1555 uint32_t POLB2:1; /*!< bit: 18 Channel 2 Polarity Buffer */ 1556 uint32_t POLB3:1; /*!< bit: 19 Channel 3 Polarity Buffer */ 1557 uint32_t :4; /*!< bit: 20..23 Reserved */ 1558 uint32_t SWAPB0:1; /*!< bit: 24 Swap DTI Output Pair 0 Buffer */ 1559 uint32_t SWAPB1:1; /*!< bit: 25 Swap DTI Output Pair 1 Buffer */ 1560 uint32_t SWAPB2:1; /*!< bit: 26 Swap DTI Output Pair 2 Buffer */ 1561 uint32_t SWAPB3:1; /*!< bit: 27 Swap DTI Output Pair 3 Buffer */ 1562 uint32_t :4; /*!< bit: 28..31 Reserved */ 1563 } bit; /*!< Structure used for bit access */ 1564 struct { 1565 uint32_t :8; /*!< bit: 0.. 7 Reserved */ 1566 uint32_t CICCENB:4; /*!< bit: 8..11 Circular Channel x Enable Buffer */ 1567 uint32_t :4; /*!< bit: 12..15 Reserved */ 1568 uint32_t POLB:4; /*!< bit: 16..19 Channel x Polarity Buffer */ 1569 uint32_t :4; /*!< bit: 20..23 Reserved */ 1570 uint32_t SWAPB:4; /*!< bit: 24..27 Swap DTI Output Pair x Buffer */ 1571 uint32_t :4; /*!< bit: 28..31 Reserved */ 1572 } vec; /*!< Structure used for vec access */ 1573 uint32_t reg; /*!< Type used for register access */ 1574 } TCC_WAVEB_Type; 1575 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1576 1577 #define TCC_WAVEB_OFFSET 0x68 /**< \brief (TCC_WAVEB offset) Waveform Control Buffer */ 1578 #define TCC_WAVEB_RESETVALUE _U_(0x00000000) /**< \brief (TCC_WAVEB reset_value) Waveform Control Buffer */ 1579 1580 #define TCC_WAVEB_WAVEGENB_Pos 0 /**< \brief (TCC_WAVEB) Waveform Generation Buffer */ 1581 #define TCC_WAVEB_WAVEGENB_Msk (_U_(0x7) << TCC_WAVEB_WAVEGENB_Pos) 1582 #define TCC_WAVEB_WAVEGENB(value) (TCC_WAVEB_WAVEGENB_Msk & ((value) << TCC_WAVEB_WAVEGENB_Pos)) 1583 #define TCC_WAVEB_WAVEGENB_NFRQ_Val _U_(0x0) /**< \brief (TCC_WAVEB) Normal frequency */ 1584 #define TCC_WAVEB_WAVEGENB_MFRQ_Val _U_(0x1) /**< \brief (TCC_WAVEB) Match frequency */ 1585 #define TCC_WAVEB_WAVEGENB_NPWM_Val _U_(0x2) /**< \brief (TCC_WAVEB) Normal PWM */ 1586 #define TCC_WAVEB_WAVEGENB_DSCRITICAL_Val _U_(0x4) /**< \brief (TCC_WAVEB) Dual-slope critical */ 1587 #define TCC_WAVEB_WAVEGENB_DSBOTTOM_Val _U_(0x5) /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches ZERO */ 1588 #define TCC_WAVEB_WAVEGENB_DSBOTH_Val _U_(0x6) /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */ 1589 #define TCC_WAVEB_WAVEGENB_DSTOP_Val _U_(0x7) /**< \brief (TCC_WAVEB) Dual-slope with interrupt/event condition when COUNT reaches TOP */ 1590 #define TCC_WAVEB_WAVEGENB_NFRQ (TCC_WAVEB_WAVEGENB_NFRQ_Val << TCC_WAVEB_WAVEGENB_Pos) 1591 #define TCC_WAVEB_WAVEGENB_MFRQ (TCC_WAVEB_WAVEGENB_MFRQ_Val << TCC_WAVEB_WAVEGENB_Pos) 1592 #define TCC_WAVEB_WAVEGENB_NPWM (TCC_WAVEB_WAVEGENB_NPWM_Val << TCC_WAVEB_WAVEGENB_Pos) 1593 #define TCC_WAVEB_WAVEGENB_DSCRITICAL (TCC_WAVEB_WAVEGENB_DSCRITICAL_Val << TCC_WAVEB_WAVEGENB_Pos) 1594 #define TCC_WAVEB_WAVEGENB_DSBOTTOM (TCC_WAVEB_WAVEGENB_DSBOTTOM_Val << TCC_WAVEB_WAVEGENB_Pos) 1595 #define TCC_WAVEB_WAVEGENB_DSBOTH (TCC_WAVEB_WAVEGENB_DSBOTH_Val << TCC_WAVEB_WAVEGENB_Pos) 1596 #define TCC_WAVEB_WAVEGENB_DSTOP (TCC_WAVEB_WAVEGENB_DSTOP_Val << TCC_WAVEB_WAVEGENB_Pos) 1597 #define TCC_WAVEB_RAMPB_Pos 4 /**< \brief (TCC_WAVEB) Ramp Mode Buffer */ 1598 #define TCC_WAVEB_RAMPB_Msk (_U_(0x3) << TCC_WAVEB_RAMPB_Pos) 1599 #define TCC_WAVEB_RAMPB(value) (TCC_WAVEB_RAMPB_Msk & ((value) << TCC_WAVEB_RAMPB_Pos)) 1600 #define TCC_WAVEB_RAMPB_RAMP1_Val _U_(0x0) /**< \brief (TCC_WAVEB) RAMP1 operation */ 1601 #define TCC_WAVEB_RAMPB_RAMP2A_Val _U_(0x1) /**< \brief (TCC_WAVEB) Alternative RAMP2 operation */ 1602 #define TCC_WAVEB_RAMPB_RAMP2_Val _U_(0x2) /**< \brief (TCC_WAVEB) RAMP2 operation */ 1603 #define TCC_WAVEB_RAMPB_RAMP1 (TCC_WAVEB_RAMPB_RAMP1_Val << TCC_WAVEB_RAMPB_Pos) 1604 #define TCC_WAVEB_RAMPB_RAMP2A (TCC_WAVEB_RAMPB_RAMP2A_Val << TCC_WAVEB_RAMPB_Pos) 1605 #define TCC_WAVEB_RAMPB_RAMP2 (TCC_WAVEB_RAMPB_RAMP2_Val << TCC_WAVEB_RAMPB_Pos) 1606 #define TCC_WAVEB_CIPERENB_Pos 7 /**< \brief (TCC_WAVEB) Circular Period Enable Buffer */ 1607 #define TCC_WAVEB_CIPERENB (_U_(0x1) << TCC_WAVEB_CIPERENB_Pos) 1608 #define TCC_WAVEB_CICCENB0_Pos 8 /**< \brief (TCC_WAVEB) Circular Channel 0 Enable Buffer */ 1609 #define TCC_WAVEB_CICCENB0 (1 << TCC_WAVEB_CICCENB0_Pos) 1610 #define TCC_WAVEB_CICCENB1_Pos 9 /**< \brief (TCC_WAVEB) Circular Channel 1 Enable Buffer */ 1611 #define TCC_WAVEB_CICCENB1 (1 << TCC_WAVEB_CICCENB1_Pos) 1612 #define TCC_WAVEB_CICCENB2_Pos 10 /**< \brief (TCC_WAVEB) Circular Channel 2 Enable Buffer */ 1613 #define TCC_WAVEB_CICCENB2 (1 << TCC_WAVEB_CICCENB2_Pos) 1614 #define TCC_WAVEB_CICCENB3_Pos 11 /**< \brief (TCC_WAVEB) Circular Channel 3 Enable Buffer */ 1615 #define TCC_WAVEB_CICCENB3 (1 << TCC_WAVEB_CICCENB3_Pos) 1616 #define TCC_WAVEB_CICCENB_Pos 8 /**< \brief (TCC_WAVEB) Circular Channel x Enable Buffer */ 1617 #define TCC_WAVEB_CICCENB_Msk (_U_(0xF) << TCC_WAVEB_CICCENB_Pos) 1618 #define TCC_WAVEB_CICCENB(value) (TCC_WAVEB_CICCENB_Msk & ((value) << TCC_WAVEB_CICCENB_Pos)) 1619 #define TCC_WAVEB_POLB0_Pos 16 /**< \brief (TCC_WAVEB) Channel 0 Polarity Buffer */ 1620 #define TCC_WAVEB_POLB0 (1 << TCC_WAVEB_POLB0_Pos) 1621 #define TCC_WAVEB_POLB1_Pos 17 /**< \brief (TCC_WAVEB) Channel 1 Polarity Buffer */ 1622 #define TCC_WAVEB_POLB1 (1 << TCC_WAVEB_POLB1_Pos) 1623 #define TCC_WAVEB_POLB2_Pos 18 /**< \brief (TCC_WAVEB) Channel 2 Polarity Buffer */ 1624 #define TCC_WAVEB_POLB2 (1 << TCC_WAVEB_POLB2_Pos) 1625 #define TCC_WAVEB_POLB3_Pos 19 /**< \brief (TCC_WAVEB) Channel 3 Polarity Buffer */ 1626 #define TCC_WAVEB_POLB3 (1 << TCC_WAVEB_POLB3_Pos) 1627 #define TCC_WAVEB_POLB_Pos 16 /**< \brief (TCC_WAVEB) Channel x Polarity Buffer */ 1628 #define TCC_WAVEB_POLB_Msk (_U_(0xF) << TCC_WAVEB_POLB_Pos) 1629 #define TCC_WAVEB_POLB(value) (TCC_WAVEB_POLB_Msk & ((value) << TCC_WAVEB_POLB_Pos)) 1630 #define TCC_WAVEB_SWAPB0_Pos 24 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 0 Buffer */ 1631 #define TCC_WAVEB_SWAPB0 (1 << TCC_WAVEB_SWAPB0_Pos) 1632 #define TCC_WAVEB_SWAPB1_Pos 25 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 1 Buffer */ 1633 #define TCC_WAVEB_SWAPB1 (1 << TCC_WAVEB_SWAPB1_Pos) 1634 #define TCC_WAVEB_SWAPB2_Pos 26 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 2 Buffer */ 1635 #define TCC_WAVEB_SWAPB2 (1 << TCC_WAVEB_SWAPB2_Pos) 1636 #define TCC_WAVEB_SWAPB3_Pos 27 /**< \brief (TCC_WAVEB) Swap DTI Output Pair 3 Buffer */ 1637 #define TCC_WAVEB_SWAPB3 (1 << TCC_WAVEB_SWAPB3_Pos) 1638 #define TCC_WAVEB_SWAPB_Pos 24 /**< \brief (TCC_WAVEB) Swap DTI Output Pair x Buffer */ 1639 #define TCC_WAVEB_SWAPB_Msk (_U_(0xF) << TCC_WAVEB_SWAPB_Pos) 1640 #define TCC_WAVEB_SWAPB(value) (TCC_WAVEB_SWAPB_Msk & ((value) << TCC_WAVEB_SWAPB_Pos)) 1641 #define TCC_WAVEB_MASK _U_(0x0F0F0FB7) /**< \brief (TCC_WAVEB) MASK Register */ 1642 1643 /* -------- TCC_PERB : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */ 1644 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1645 typedef union { 1646 struct { // DITH4 mode 1647 uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */ 1648 uint32_t PERB:20; /*!< bit: 4..23 Period Buffer Value */ 1649 uint32_t :8; /*!< bit: 24..31 Reserved */ 1650 } DITH4; /*!< Structure used for DITH4 */ 1651 struct { // DITH5 mode 1652 uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */ 1653 uint32_t PERB:19; /*!< bit: 5..23 Period Buffer Value */ 1654 uint32_t :8; /*!< bit: 24..31 Reserved */ 1655 } DITH5; /*!< Structure used for DITH5 */ 1656 struct { // DITH6 mode 1657 uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */ 1658 uint32_t PERB:18; /*!< bit: 6..23 Period Buffer Value */ 1659 uint32_t :8; /*!< bit: 24..31 Reserved */ 1660 } DITH6; /*!< Structure used for DITH6 */ 1661 struct { 1662 uint32_t PERB:24; /*!< bit: 0..23 Period Buffer Value */ 1663 uint32_t :8; /*!< bit: 24..31 Reserved */ 1664 } bit; /*!< Structure used for bit access */ 1665 uint32_t reg; /*!< Type used for register access */ 1666 } TCC_PERB_Type; 1667 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1668 1669 #define TCC_PERB_OFFSET 0x6C /**< \brief (TCC_PERB offset) Period Buffer */ 1670 #define TCC_PERB_RESETVALUE _U_(0xFFFFFFFF) /**< \brief (TCC_PERB reset_value) Period Buffer */ 1671 1672 // DITH4 mode 1673 #define TCC_PERB_DITH4_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH4) Dithering Buffer Cycle Number */ 1674 #define TCC_PERB_DITH4_DITHERCYB_Msk (_U_(0xF) << TCC_PERB_DITH4_DITHERCYB_Pos) 1675 #define TCC_PERB_DITH4_DITHERCYB(value) (TCC_PERB_DITH4_DITHERCYB_Msk & ((value) << TCC_PERB_DITH4_DITHERCYB_Pos)) 1676 #define TCC_PERB_DITH4_PERB_Pos 4 /**< \brief (TCC_PERB_DITH4) Period Buffer Value */ 1677 #define TCC_PERB_DITH4_PERB_Msk (_U_(0xFFFFF) << TCC_PERB_DITH4_PERB_Pos) 1678 #define TCC_PERB_DITH4_PERB(value) (TCC_PERB_DITH4_PERB_Msk & ((value) << TCC_PERB_DITH4_PERB_Pos)) 1679 #define TCC_PERB_DITH4_MASK _U_(0x00FFFFFF) /**< \brief (TCC_PERB_DITH4) MASK Register */ 1680 1681 // DITH5 mode 1682 #define TCC_PERB_DITH5_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH5) Dithering Buffer Cycle Number */ 1683 #define TCC_PERB_DITH5_DITHERCYB_Msk (_U_(0x1F) << TCC_PERB_DITH5_DITHERCYB_Pos) 1684 #define TCC_PERB_DITH5_DITHERCYB(value) (TCC_PERB_DITH5_DITHERCYB_Msk & ((value) << TCC_PERB_DITH5_DITHERCYB_Pos)) 1685 #define TCC_PERB_DITH5_PERB_Pos 5 /**< \brief (TCC_PERB_DITH5) Period Buffer Value */ 1686 #define TCC_PERB_DITH5_PERB_Msk (_U_(0x7FFFF) << TCC_PERB_DITH5_PERB_Pos) 1687 #define TCC_PERB_DITH5_PERB(value) (TCC_PERB_DITH5_PERB_Msk & ((value) << TCC_PERB_DITH5_PERB_Pos)) 1688 #define TCC_PERB_DITH5_MASK _U_(0x00FFFFFF) /**< \brief (TCC_PERB_DITH5) MASK Register */ 1689 1690 // DITH6 mode 1691 #define TCC_PERB_DITH6_DITHERCYB_Pos 0 /**< \brief (TCC_PERB_DITH6) Dithering Buffer Cycle Number */ 1692 #define TCC_PERB_DITH6_DITHERCYB_Msk (_U_(0x3F) << TCC_PERB_DITH6_DITHERCYB_Pos) 1693 #define TCC_PERB_DITH6_DITHERCYB(value) (TCC_PERB_DITH6_DITHERCYB_Msk & ((value) << TCC_PERB_DITH6_DITHERCYB_Pos)) 1694 #define TCC_PERB_DITH6_PERB_Pos 6 /**< \brief (TCC_PERB_DITH6) Period Buffer Value */ 1695 #define TCC_PERB_DITH6_PERB_Msk (_U_(0x3FFFF) << TCC_PERB_DITH6_PERB_Pos) 1696 #define TCC_PERB_DITH6_PERB(value) (TCC_PERB_DITH6_PERB_Msk & ((value) << TCC_PERB_DITH6_PERB_Pos)) 1697 #define TCC_PERB_DITH6_MASK _U_(0x00FFFFFF) /**< \brief (TCC_PERB_DITH6) MASK Register */ 1698 1699 #define TCC_PERB_PERB_Pos 0 /**< \brief (TCC_PERB) Period Buffer Value */ 1700 #define TCC_PERB_PERB_Msk (_U_(0xFFFFFF) << TCC_PERB_PERB_Pos) 1701 #define TCC_PERB_PERB(value) (TCC_PERB_PERB_Msk & ((value) << TCC_PERB_PERB_Pos)) 1702 #define TCC_PERB_MASK _U_(0x00FFFFFF) /**< \brief (TCC_PERB) MASK Register */ 1703 1704 /* -------- TCC_CCB : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */ 1705 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1706 typedef union { 1707 struct { // DITH4 mode 1708 uint32_t DITHERCYB:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */ 1709 uint32_t CCB:20; /*!< bit: 4..23 Channel Compare/Capture Buffer Value */ 1710 uint32_t :8; /*!< bit: 24..31 Reserved */ 1711 } DITH4; /*!< Structure used for DITH4 */ 1712 struct { // DITH5 mode 1713 uint32_t DITHERCYB:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */ 1714 uint32_t CCB:19; /*!< bit: 5..23 Channel Compare/Capture Buffer Value */ 1715 uint32_t :8; /*!< bit: 24..31 Reserved */ 1716 } DITH5; /*!< Structure used for DITH5 */ 1717 struct { // DITH6 mode 1718 uint32_t DITHERCYB:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */ 1719 uint32_t CCB:18; /*!< bit: 6..23 Channel Compare/Capture Buffer Value */ 1720 uint32_t :8; /*!< bit: 24..31 Reserved */ 1721 } DITH6; /*!< Structure used for DITH6 */ 1722 struct { 1723 uint32_t CCB:24; /*!< bit: 0..23 Channel Compare/Capture Buffer Value */ 1724 uint32_t :8; /*!< bit: 24..31 Reserved */ 1725 } bit; /*!< Structure used for bit access */ 1726 uint32_t reg; /*!< Type used for register access */ 1727 } TCC_CCB_Type; 1728 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1729 1730 #define TCC_CCB_OFFSET 0x70 /**< \brief (TCC_CCB offset) Compare and Capture Buffer */ 1731 #define TCC_CCB_RESETVALUE _U_(0x00000000) /**< \brief (TCC_CCB reset_value) Compare and Capture Buffer */ 1732 1733 // DITH4 mode 1734 #define TCC_CCB_DITH4_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH4) Dithering Buffer Cycle Number */ 1735 #define TCC_CCB_DITH4_DITHERCYB_Msk (_U_(0xF) << TCC_CCB_DITH4_DITHERCYB_Pos) 1736 #define TCC_CCB_DITH4_DITHERCYB(value) (TCC_CCB_DITH4_DITHERCYB_Msk & ((value) << TCC_CCB_DITH4_DITHERCYB_Pos)) 1737 #define TCC_CCB_DITH4_CCB_Pos 4 /**< \brief (TCC_CCB_DITH4) Channel Compare/Capture Buffer Value */ 1738 #define TCC_CCB_DITH4_CCB_Msk (_U_(0xFFFFF) << TCC_CCB_DITH4_CCB_Pos) 1739 #define TCC_CCB_DITH4_CCB(value) (TCC_CCB_DITH4_CCB_Msk & ((value) << TCC_CCB_DITH4_CCB_Pos)) 1740 #define TCC_CCB_DITH4_MASK _U_(0x00FFFFFF) /**< \brief (TCC_CCB_DITH4) MASK Register */ 1741 1742 // DITH5 mode 1743 #define TCC_CCB_DITH5_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH5) Dithering Buffer Cycle Number */ 1744 #define TCC_CCB_DITH5_DITHERCYB_Msk (_U_(0x1F) << TCC_CCB_DITH5_DITHERCYB_Pos) 1745 #define TCC_CCB_DITH5_DITHERCYB(value) (TCC_CCB_DITH5_DITHERCYB_Msk & ((value) << TCC_CCB_DITH5_DITHERCYB_Pos)) 1746 #define TCC_CCB_DITH5_CCB_Pos 5 /**< \brief (TCC_CCB_DITH5) Channel Compare/Capture Buffer Value */ 1747 #define TCC_CCB_DITH5_CCB_Msk (_U_(0x7FFFF) << TCC_CCB_DITH5_CCB_Pos) 1748 #define TCC_CCB_DITH5_CCB(value) (TCC_CCB_DITH5_CCB_Msk & ((value) << TCC_CCB_DITH5_CCB_Pos)) 1749 #define TCC_CCB_DITH5_MASK _U_(0x00FFFFFF) /**< \brief (TCC_CCB_DITH5) MASK Register */ 1750 1751 // DITH6 mode 1752 #define TCC_CCB_DITH6_DITHERCYB_Pos 0 /**< \brief (TCC_CCB_DITH6) Dithering Buffer Cycle Number */ 1753 #define TCC_CCB_DITH6_DITHERCYB_Msk (_U_(0x3F) << TCC_CCB_DITH6_DITHERCYB_Pos) 1754 #define TCC_CCB_DITH6_DITHERCYB(value) (TCC_CCB_DITH6_DITHERCYB_Msk & ((value) << TCC_CCB_DITH6_DITHERCYB_Pos)) 1755 #define TCC_CCB_DITH6_CCB_Pos 6 /**< \brief (TCC_CCB_DITH6) Channel Compare/Capture Buffer Value */ 1756 #define TCC_CCB_DITH6_CCB_Msk (_U_(0x3FFFF) << TCC_CCB_DITH6_CCB_Pos) 1757 #define TCC_CCB_DITH6_CCB(value) (TCC_CCB_DITH6_CCB_Msk & ((value) << TCC_CCB_DITH6_CCB_Pos)) 1758 #define TCC_CCB_DITH6_MASK _U_(0x00FFFFFF) /**< \brief (TCC_CCB_DITH6) MASK Register */ 1759 1760 #define TCC_CCB_CCB_Pos 0 /**< \brief (TCC_CCB) Channel Compare/Capture Buffer Value */ 1761 #define TCC_CCB_CCB_Msk (_U_(0xFFFFFF) << TCC_CCB_CCB_Pos) 1762 #define TCC_CCB_CCB(value) (TCC_CCB_CCB_Msk & ((value) << TCC_CCB_CCB_Pos)) 1763 #define TCC_CCB_MASK _U_(0x00FFFFFF) /**< \brief (TCC_CCB) MASK Register */ 1764 1765 /** \brief TCC hardware registers */ 1766 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1767 typedef struct { 1768 __IO TCC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ 1769 __IO TCC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ 1770 __IO TCC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ 1771 RoReg8 Reserved1[0x2]; 1772 __I TCC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */ 1773 __IO TCC_FCTRLA_Type FCTRLA; /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */ 1774 __IO TCC_FCTRLB_Type FCTRLB; /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */ 1775 __IO TCC_WEXCTRL_Type WEXCTRL; /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */ 1776 __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */ 1777 RoReg8 Reserved2[0x2]; 1778 __IO TCC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1E (R/W 8) Debug Control */ 1779 RoReg8 Reserved3[0x1]; 1780 __IO TCC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x20 (R/W 32) Event Control */ 1781 __IO TCC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */ 1782 __IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */ 1783 __IO TCC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */ 1784 __IO TCC_STATUS_Type STATUS; /**< \brief Offset: 0x30 (R/W 32) Status */ 1785 __IO TCC_COUNT_Type COUNT; /**< \brief Offset: 0x34 (R/W 32) Count */ 1786 __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */ 1787 RoReg8 Reserved4[0x2]; 1788 __IO TCC_WAVE_Type WAVE; /**< \brief Offset: 0x3C (R/W 32) Waveform Control */ 1789 __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */ 1790 __IO TCC_CC_Type CC[4]; /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */ 1791 RoReg8 Reserved5[0x10]; 1792 __IO TCC_PATTB_Type PATTB; /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */ 1793 RoReg8 Reserved6[0x2]; 1794 __IO TCC_WAVEB_Type WAVEB; /**< \brief Offset: 0x68 (R/W 32) Waveform Control Buffer */ 1795 __IO TCC_PERB_Type PERB; /**< \brief Offset: 0x6C (R/W 32) Period Buffer */ 1796 __IO TCC_CCB_Type CCB[4]; /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */ 1797 } Tcc; 1798 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1799 1800 /*@}*/ 1801 1802 #endif /* _SAMR21_TCC_COMPONENT_ */ 1803
