1 /** 2 * \file 3 * 4 * \brief Component description for SERCOM 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAMR21_SERCOM_COMPONENT_ 30 #define _SAMR21_SERCOM_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR SERCOM */ 34 /* ========================================================================== */ 35 /** \addtogroup SAMR21_SERCOM Serial Communication Interface */ 36 /*@{*/ 37 38 #define SERCOM_U2201 39 #define REV_SERCOM 0x200 40 41 /* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM I2CM Control A -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t SWRST:1; /*!< bit: 0 Software Reset */ 46 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 47 uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ 48 uint32_t :2; /*!< bit: 5.. 6 Reserved */ 49 uint32_t RUNSTDBY:1; /*!< bit: 7 Run in Standby */ 50 uint32_t :8; /*!< bit: 8..15 Reserved */ 51 uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */ 52 uint32_t :3; /*!< bit: 17..19 Reserved */ 53 uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */ 54 uint32_t MEXTTOEN:1; /*!< bit: 22 Master SCL Low Extend Timeout */ 55 uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */ 56 uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */ 57 uint32_t :1; /*!< bit: 26 Reserved */ 58 uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */ 59 uint32_t INACTOUT:2; /*!< bit: 28..29 Inactive Time-Out */ 60 uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */ 61 uint32_t :1; /*!< bit: 31 Reserved */ 62 } bit; /*!< Structure used for bit access */ 63 uint32_t reg; /*!< Type used for register access */ 64 } SERCOM_I2CM_CTRLA_Type; 65 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 66 67 #define SERCOM_I2CM_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CM_CTRLA offset) I2CM Control A */ 68 #define SERCOM_I2CM_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_CTRLA reset_value) I2CM Control A */ 69 70 #define SERCOM_I2CM_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_CTRLA) Software Reset */ 71 #define SERCOM_I2CM_CTRLA_SWRST (_U_(0x1) << SERCOM_I2CM_CTRLA_SWRST_Pos) 72 #define SERCOM_I2CM_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_CTRLA) Enable */ 73 #define SERCOM_I2CM_CTRLA_ENABLE (_U_(0x1) << SERCOM_I2CM_CTRLA_ENABLE_Pos) 74 #define SERCOM_I2CM_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CM_CTRLA) Operating Mode */ 75 #define SERCOM_I2CM_CTRLA_MODE_Msk (_U_(0x7) << SERCOM_I2CM_CTRLA_MODE_Pos) 76 #define SERCOM_I2CM_CTRLA_MODE(value) (SERCOM_I2CM_CTRLA_MODE_Msk & ((value) << SERCOM_I2CM_CTRLA_MODE_Pos)) 77 #define SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val _U_(0x0) /**< \brief (SERCOM_I2CM_CTRLA) USART mode with external clock */ 78 #define SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val _U_(0x1) /**< \brief (SERCOM_I2CM_CTRLA) USART mode with internal clock */ 79 #define SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val _U_(0x2) /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with external clock */ 80 #define SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val _U_(0x3) /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with internal clock */ 81 #define SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val _U_(0x4) /**< \brief (SERCOM_I2CM_CTRLA) I2C mode with external clock */ 82 #define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val _U_(0x5) /**< \brief (SERCOM_I2CM_CTRLA) I2C mode with internal clock */ 83 #define SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK (SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos) 84 #define SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK (SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos) 85 #define SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE (SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos) 86 #define SERCOM_I2CM_CTRLA_MODE_SPI_MASTER (SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos) 87 #define SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE (SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos) 88 #define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos) 89 #define SERCOM_I2CM_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CM_CTRLA) Run in Standby */ 90 #define SERCOM_I2CM_CTRLA_RUNSTDBY (_U_(0x1) << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos) 91 #define SERCOM_I2CM_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CM_CTRLA) Pin Usage */ 92 #define SERCOM_I2CM_CTRLA_PINOUT (_U_(0x1) << SERCOM_I2CM_CTRLA_PINOUT_Pos) 93 #define SERCOM_I2CM_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CM_CTRLA) SDA Hold Time */ 94 #define SERCOM_I2CM_CTRLA_SDAHOLD_Msk (_U_(0x3) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos) 95 #define SERCOM_I2CM_CTRLA_SDAHOLD(value) (SERCOM_I2CM_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)) 96 #define SERCOM_I2CM_CTRLA_MEXTTOEN_Pos 22 /**< \brief (SERCOM_I2CM_CTRLA) Master SCL Low Extend Timeout */ 97 #define SERCOM_I2CM_CTRLA_MEXTTOEN (_U_(0x1) << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos) 98 #define SERCOM_I2CM_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CM_CTRLA) Slave SCL Low Extend Timeout */ 99 #define SERCOM_I2CM_CTRLA_SEXTTOEN (_U_(0x1) << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos) 100 #define SERCOM_I2CM_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CM_CTRLA) Transfer Speed */ 101 #define SERCOM_I2CM_CTRLA_SPEED_Msk (_U_(0x3) << SERCOM_I2CM_CTRLA_SPEED_Pos) 102 #define SERCOM_I2CM_CTRLA_SPEED(value) (SERCOM_I2CM_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CM_CTRLA_SPEED_Pos)) 103 #define SERCOM_I2CM_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CM_CTRLA) SCL Clock Stretch Mode */ 104 #define SERCOM_I2CM_CTRLA_SCLSM (_U_(0x1) << SERCOM_I2CM_CTRLA_SCLSM_Pos) 105 #define SERCOM_I2CM_CTRLA_INACTOUT_Pos 28 /**< \brief (SERCOM_I2CM_CTRLA) Inactive Time-Out */ 106 #define SERCOM_I2CM_CTRLA_INACTOUT_Msk (_U_(0x3) << SERCOM_I2CM_CTRLA_INACTOUT_Pos) 107 #define SERCOM_I2CM_CTRLA_INACTOUT(value) (SERCOM_I2CM_CTRLA_INACTOUT_Msk & ((value) << SERCOM_I2CM_CTRLA_INACTOUT_Pos)) 108 #define SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CM_CTRLA) SCL Low Timeout Enable */ 109 #define SERCOM_I2CM_CTRLA_LOWTOUTEN (_U_(0x1) << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos) 110 #define SERCOM_I2CM_CTRLA_MASK _U_(0x7BF1009F) /**< \brief (SERCOM_I2CM_CTRLA) MASK Register */ 111 112 /* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS I2CS Control A -------- */ 113 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 114 typedef union { 115 struct { 116 uint32_t SWRST:1; /*!< bit: 0 Software Reset */ 117 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 118 uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ 119 uint32_t :2; /*!< bit: 5.. 6 Reserved */ 120 uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ 121 uint32_t :8; /*!< bit: 8..15 Reserved */ 122 uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */ 123 uint32_t :3; /*!< bit: 17..19 Reserved */ 124 uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */ 125 uint32_t :1; /*!< bit: 22 Reserved */ 126 uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */ 127 uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */ 128 uint32_t :1; /*!< bit: 26 Reserved */ 129 uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */ 130 uint32_t :2; /*!< bit: 28..29 Reserved */ 131 uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */ 132 uint32_t :1; /*!< bit: 31 Reserved */ 133 } bit; /*!< Structure used for bit access */ 134 uint32_t reg; /*!< Type used for register access */ 135 } SERCOM_I2CS_CTRLA_Type; 136 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 137 138 #define SERCOM_I2CS_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CS_CTRLA offset) I2CS Control A */ 139 #define SERCOM_I2CS_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_CTRLA reset_value) I2CS Control A */ 140 141 #define SERCOM_I2CS_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_CTRLA) Software Reset */ 142 #define SERCOM_I2CS_CTRLA_SWRST (_U_(0x1) << SERCOM_I2CS_CTRLA_SWRST_Pos) 143 #define SERCOM_I2CS_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_CTRLA) Enable */ 144 #define SERCOM_I2CS_CTRLA_ENABLE (_U_(0x1) << SERCOM_I2CS_CTRLA_ENABLE_Pos) 145 #define SERCOM_I2CS_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CS_CTRLA) Operating Mode */ 146 #define SERCOM_I2CS_CTRLA_MODE_Msk (_U_(0x7) << SERCOM_I2CS_CTRLA_MODE_Pos) 147 #define SERCOM_I2CS_CTRLA_MODE(value) (SERCOM_I2CS_CTRLA_MODE_Msk & ((value) << SERCOM_I2CS_CTRLA_MODE_Pos)) 148 #define SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val _U_(0x0) /**< \brief (SERCOM_I2CS_CTRLA) USART mode with external clock */ 149 #define SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val _U_(0x1) /**< \brief (SERCOM_I2CS_CTRLA) USART mode with internal clock */ 150 #define SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val _U_(0x2) /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with external clock */ 151 #define SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val _U_(0x3) /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with internal clock */ 152 #define SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val _U_(0x4) /**< \brief (SERCOM_I2CS_CTRLA) I2C mode with external clock */ 153 #define SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val _U_(0x5) /**< \brief (SERCOM_I2CS_CTRLA) I2C mode with internal clock */ 154 #define SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK (SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos) 155 #define SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK (SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos) 156 #define SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE (SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos) 157 #define SERCOM_I2CS_CTRLA_MODE_SPI_MASTER (SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos) 158 #define SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE (SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos) 159 #define SERCOM_I2CS_CTRLA_MODE_I2C_MASTER (SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos) 160 #define SERCOM_I2CS_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CS_CTRLA) Run during Standby */ 161 #define SERCOM_I2CS_CTRLA_RUNSTDBY (_U_(0x1) << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos) 162 #define SERCOM_I2CS_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CS_CTRLA) Pin Usage */ 163 #define SERCOM_I2CS_CTRLA_PINOUT (_U_(0x1) << SERCOM_I2CS_CTRLA_PINOUT_Pos) 164 #define SERCOM_I2CS_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CS_CTRLA) SDA Hold Time */ 165 #define SERCOM_I2CS_CTRLA_SDAHOLD_Msk (_U_(0x3) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos) 166 #define SERCOM_I2CS_CTRLA_SDAHOLD(value) (SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)) 167 #define SERCOM_I2CS_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CS_CTRLA) Slave SCL Low Extend Timeout */ 168 #define SERCOM_I2CS_CTRLA_SEXTTOEN (_U_(0x1) << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos) 169 #define SERCOM_I2CS_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CS_CTRLA) Transfer Speed */ 170 #define SERCOM_I2CS_CTRLA_SPEED_Msk (_U_(0x3) << SERCOM_I2CS_CTRLA_SPEED_Pos) 171 #define SERCOM_I2CS_CTRLA_SPEED(value) (SERCOM_I2CS_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CS_CTRLA_SPEED_Pos)) 172 #define SERCOM_I2CS_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CS_CTRLA) SCL Clock Stretch Mode */ 173 #define SERCOM_I2CS_CTRLA_SCLSM (_U_(0x1) << SERCOM_I2CS_CTRLA_SCLSM_Pos) 174 #define SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CS_CTRLA) SCL Low Timeout Enable */ 175 #define SERCOM_I2CS_CTRLA_LOWTOUTEN (_U_(0x1) << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos) 176 #define SERCOM_I2CS_CTRLA_MASK _U_(0x4BB1009F) /**< \brief (SERCOM_I2CS_CTRLA) MASK Register */ 177 178 /* -------- SERCOM_SPI_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPI SPI Control A -------- */ 179 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 180 typedef union { 181 struct { 182 uint32_t SWRST:1; /*!< bit: 0 Software Reset */ 183 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 184 uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ 185 uint32_t :2; /*!< bit: 5.. 6 Reserved */ 186 uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ 187 uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */ 188 uint32_t :7; /*!< bit: 9..15 Reserved */ 189 uint32_t DOPO:2; /*!< bit: 16..17 Data Out Pinout */ 190 uint32_t :2; /*!< bit: 18..19 Reserved */ 191 uint32_t DIPO:2; /*!< bit: 20..21 Data In Pinout */ 192 uint32_t :2; /*!< bit: 22..23 Reserved */ 193 uint32_t FORM:4; /*!< bit: 24..27 Frame Format */ 194 uint32_t CPHA:1; /*!< bit: 28 Clock Phase */ 195 uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */ 196 uint32_t DORD:1; /*!< bit: 30 Data Order */ 197 uint32_t :1; /*!< bit: 31 Reserved */ 198 } bit; /*!< Structure used for bit access */ 199 uint32_t reg; /*!< Type used for register access */ 200 } SERCOM_SPI_CTRLA_Type; 201 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 202 203 #define SERCOM_SPI_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_SPI_CTRLA offset) SPI Control A */ 204 #define SERCOM_SPI_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_CTRLA reset_value) SPI Control A */ 205 206 #define SERCOM_SPI_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_SPI_CTRLA) Software Reset */ 207 #define SERCOM_SPI_CTRLA_SWRST (_U_(0x1) << SERCOM_SPI_CTRLA_SWRST_Pos) 208 #define SERCOM_SPI_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_CTRLA) Enable */ 209 #define SERCOM_SPI_CTRLA_ENABLE (_U_(0x1) << SERCOM_SPI_CTRLA_ENABLE_Pos) 210 #define SERCOM_SPI_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_SPI_CTRLA) Operating Mode */ 211 #define SERCOM_SPI_CTRLA_MODE_Msk (_U_(0x7) << SERCOM_SPI_CTRLA_MODE_Pos) 212 #define SERCOM_SPI_CTRLA_MODE(value) (SERCOM_SPI_CTRLA_MODE_Msk & ((value) << SERCOM_SPI_CTRLA_MODE_Pos)) 213 #define SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK_Val _U_(0x0) /**< \brief (SERCOM_SPI_CTRLA) USART mode with external clock */ 214 #define SERCOM_SPI_CTRLA_MODE_USART_INT_CLK_Val _U_(0x1) /**< \brief (SERCOM_SPI_CTRLA) USART mode with internal clock */ 215 #define SERCOM_SPI_CTRLA_MODE_SPI_SLAVE_Val _U_(0x2) /**< \brief (SERCOM_SPI_CTRLA) SPI mode with external clock */ 216 #define SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val _U_(0x3) /**< \brief (SERCOM_SPI_CTRLA) SPI mode with internal clock */ 217 #define SERCOM_SPI_CTRLA_MODE_I2C_SLAVE_Val _U_(0x4) /**< \brief (SERCOM_SPI_CTRLA) I2C mode with external clock */ 218 #define SERCOM_SPI_CTRLA_MODE_I2C_MASTER_Val _U_(0x5) /**< \brief (SERCOM_SPI_CTRLA) I2C mode with internal clock */ 219 #define SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK (SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_SPI_CTRLA_MODE_Pos) 220 #define SERCOM_SPI_CTRLA_MODE_USART_INT_CLK (SERCOM_SPI_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_SPI_CTRLA_MODE_Pos) 221 #define SERCOM_SPI_CTRLA_MODE_SPI_SLAVE (SERCOM_SPI_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_SPI_CTRLA_MODE_Pos) 222 #define SERCOM_SPI_CTRLA_MODE_SPI_MASTER (SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val << SERCOM_SPI_CTRLA_MODE_Pos) 223 #define SERCOM_SPI_CTRLA_MODE_I2C_SLAVE (SERCOM_SPI_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_SPI_CTRLA_MODE_Pos) 224 #define SERCOM_SPI_CTRLA_MODE_I2C_MASTER (SERCOM_SPI_CTRLA_MODE_I2C_MASTER_Val << SERCOM_SPI_CTRLA_MODE_Pos) 225 #define SERCOM_SPI_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_SPI_CTRLA) Run during Standby */ 226 #define SERCOM_SPI_CTRLA_RUNSTDBY (_U_(0x1) << SERCOM_SPI_CTRLA_RUNSTDBY_Pos) 227 #define SERCOM_SPI_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_SPI_CTRLA) Immediate Buffer Overflow Notification */ 228 #define SERCOM_SPI_CTRLA_IBON (_U_(0x1) << SERCOM_SPI_CTRLA_IBON_Pos) 229 #define SERCOM_SPI_CTRLA_DOPO_Pos 16 /**< \brief (SERCOM_SPI_CTRLA) Data Out Pinout */ 230 #define SERCOM_SPI_CTRLA_DOPO_Msk (_U_(0x3) << SERCOM_SPI_CTRLA_DOPO_Pos) 231 #define SERCOM_SPI_CTRLA_DOPO(value) (SERCOM_SPI_CTRLA_DOPO_Msk & ((value) << SERCOM_SPI_CTRLA_DOPO_Pos)) 232 #define SERCOM_SPI_CTRLA_DIPO_Pos 20 /**< \brief (SERCOM_SPI_CTRLA) Data In Pinout */ 233 #define SERCOM_SPI_CTRLA_DIPO_Msk (_U_(0x3) << SERCOM_SPI_CTRLA_DIPO_Pos) 234 #define SERCOM_SPI_CTRLA_DIPO(value) (SERCOM_SPI_CTRLA_DIPO_Msk & ((value) << SERCOM_SPI_CTRLA_DIPO_Pos)) 235 #define SERCOM_SPI_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_SPI_CTRLA) Frame Format */ 236 #define SERCOM_SPI_CTRLA_FORM_Msk (_U_(0xF) << SERCOM_SPI_CTRLA_FORM_Pos) 237 #define SERCOM_SPI_CTRLA_FORM(value) (SERCOM_SPI_CTRLA_FORM_Msk & ((value) << SERCOM_SPI_CTRLA_FORM_Pos)) 238 #define SERCOM_SPI_CTRLA_CPHA_Pos 28 /**< \brief (SERCOM_SPI_CTRLA) Clock Phase */ 239 #define SERCOM_SPI_CTRLA_CPHA (_U_(0x1) << SERCOM_SPI_CTRLA_CPHA_Pos) 240 #define SERCOM_SPI_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_SPI_CTRLA) Clock Polarity */ 241 #define SERCOM_SPI_CTRLA_CPOL (_U_(0x1) << SERCOM_SPI_CTRLA_CPOL_Pos) 242 #define SERCOM_SPI_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_SPI_CTRLA) Data Order */ 243 #define SERCOM_SPI_CTRLA_DORD (_U_(0x1) << SERCOM_SPI_CTRLA_DORD_Pos) 244 #define SERCOM_SPI_CTRLA_MASK _U_(0x7F33019F) /**< \brief (SERCOM_SPI_CTRLA) MASK Register */ 245 246 /* -------- SERCOM_USART_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART USART Control A -------- */ 247 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 248 typedef union { 249 struct { 250 uint32_t SWRST:1; /*!< bit: 0 Software Reset */ 251 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 252 uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ 253 uint32_t :2; /*!< bit: 5.. 6 Reserved */ 254 uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ 255 uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */ 256 uint32_t :4; /*!< bit: 9..12 Reserved */ 257 uint32_t SAMPR:3; /*!< bit: 13..15 Sample */ 258 uint32_t TXPO:2; /*!< bit: 16..17 Transmit Data Pinout */ 259 uint32_t :2; /*!< bit: 18..19 Reserved */ 260 uint32_t RXPO:2; /*!< bit: 20..21 Receive Data Pinout */ 261 uint32_t SAMPA:2; /*!< bit: 22..23 Sample Adjustment */ 262 uint32_t FORM:4; /*!< bit: 24..27 Frame Format */ 263 uint32_t CMODE:1; /*!< bit: 28 Communication Mode */ 264 uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */ 265 uint32_t DORD:1; /*!< bit: 30 Data Order */ 266 uint32_t :1; /*!< bit: 31 Reserved */ 267 } bit; /*!< Structure used for bit access */ 268 uint32_t reg; /*!< Type used for register access */ 269 } SERCOM_USART_CTRLA_Type; 270 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 271 272 #define SERCOM_USART_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_USART_CTRLA offset) USART Control A */ 273 #define SERCOM_USART_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_CTRLA reset_value) USART Control A */ 274 275 #define SERCOM_USART_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_USART_CTRLA) Software Reset */ 276 #define SERCOM_USART_CTRLA_SWRST (_U_(0x1) << SERCOM_USART_CTRLA_SWRST_Pos) 277 #define SERCOM_USART_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_USART_CTRLA) Enable */ 278 #define SERCOM_USART_CTRLA_ENABLE (_U_(0x1) << SERCOM_USART_CTRLA_ENABLE_Pos) 279 #define SERCOM_USART_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_USART_CTRLA) Operating Mode */ 280 #define SERCOM_USART_CTRLA_MODE_Msk (_U_(0x7) << SERCOM_USART_CTRLA_MODE_Pos) 281 #define SERCOM_USART_CTRLA_MODE(value) (SERCOM_USART_CTRLA_MODE_Msk & ((value) << SERCOM_USART_CTRLA_MODE_Pos)) 282 #define SERCOM_USART_CTRLA_MODE_USART_EXT_CLK_Val _U_(0x0) /**< \brief (SERCOM_USART_CTRLA) USART mode with external clock */ 283 #define SERCOM_USART_CTRLA_MODE_USART_INT_CLK_Val _U_(0x1) /**< \brief (SERCOM_USART_CTRLA) USART mode with internal clock */ 284 #define SERCOM_USART_CTRLA_MODE_SPI_SLAVE_Val _U_(0x2) /**< \brief (SERCOM_USART_CTRLA) SPI mode with external clock */ 285 #define SERCOM_USART_CTRLA_MODE_SPI_MASTER_Val _U_(0x3) /**< \brief (SERCOM_USART_CTRLA) SPI mode with internal clock */ 286 #define SERCOM_USART_CTRLA_MODE_I2C_SLAVE_Val _U_(0x4) /**< \brief (SERCOM_USART_CTRLA) I2C mode with external clock */ 287 #define SERCOM_USART_CTRLA_MODE_I2C_MASTER_Val _U_(0x5) /**< \brief (SERCOM_USART_CTRLA) I2C mode with internal clock */ 288 #define SERCOM_USART_CTRLA_MODE_USART_EXT_CLK (SERCOM_USART_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_USART_CTRLA_MODE_Pos) 289 #define SERCOM_USART_CTRLA_MODE_USART_INT_CLK (SERCOM_USART_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_USART_CTRLA_MODE_Pos) 290 #define SERCOM_USART_CTRLA_MODE_SPI_SLAVE (SERCOM_USART_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_USART_CTRLA_MODE_Pos) 291 #define SERCOM_USART_CTRLA_MODE_SPI_MASTER (SERCOM_USART_CTRLA_MODE_SPI_MASTER_Val << SERCOM_USART_CTRLA_MODE_Pos) 292 #define SERCOM_USART_CTRLA_MODE_I2C_SLAVE (SERCOM_USART_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_USART_CTRLA_MODE_Pos) 293 #define SERCOM_USART_CTRLA_MODE_I2C_MASTER (SERCOM_USART_CTRLA_MODE_I2C_MASTER_Val << SERCOM_USART_CTRLA_MODE_Pos) 294 #define SERCOM_USART_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_USART_CTRLA) Run during Standby */ 295 #define SERCOM_USART_CTRLA_RUNSTDBY (_U_(0x1) << SERCOM_USART_CTRLA_RUNSTDBY_Pos) 296 #define SERCOM_USART_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_USART_CTRLA) Immediate Buffer Overflow Notification */ 297 #define SERCOM_USART_CTRLA_IBON (_U_(0x1) << SERCOM_USART_CTRLA_IBON_Pos) 298 #define SERCOM_USART_CTRLA_SAMPR_Pos 13 /**< \brief (SERCOM_USART_CTRLA) Sample */ 299 #define SERCOM_USART_CTRLA_SAMPR_Msk (_U_(0x7) << SERCOM_USART_CTRLA_SAMPR_Pos) 300 #define SERCOM_USART_CTRLA_SAMPR(value) (SERCOM_USART_CTRLA_SAMPR_Msk & ((value) << SERCOM_USART_CTRLA_SAMPR_Pos)) 301 #define SERCOM_USART_CTRLA_TXPO_Pos 16 /**< \brief (SERCOM_USART_CTRLA) Transmit Data Pinout */ 302 #define SERCOM_USART_CTRLA_TXPO_Msk (_U_(0x3) << SERCOM_USART_CTRLA_TXPO_Pos) 303 #define SERCOM_USART_CTRLA_TXPO(value) (SERCOM_USART_CTRLA_TXPO_Msk & ((value) << SERCOM_USART_CTRLA_TXPO_Pos)) 304 #define SERCOM_USART_CTRLA_RXPO_Pos 20 /**< \brief (SERCOM_USART_CTRLA) Receive Data Pinout */ 305 #define SERCOM_USART_CTRLA_RXPO_Msk (_U_(0x3) << SERCOM_USART_CTRLA_RXPO_Pos) 306 #define SERCOM_USART_CTRLA_RXPO(value) (SERCOM_USART_CTRLA_RXPO_Msk & ((value) << SERCOM_USART_CTRLA_RXPO_Pos)) 307 #define SERCOM_USART_CTRLA_SAMPA_Pos 22 /**< \brief (SERCOM_USART_CTRLA) Sample Adjustment */ 308 #define SERCOM_USART_CTRLA_SAMPA_Msk (_U_(0x3) << SERCOM_USART_CTRLA_SAMPA_Pos) 309 #define SERCOM_USART_CTRLA_SAMPA(value) (SERCOM_USART_CTRLA_SAMPA_Msk & ((value) << SERCOM_USART_CTRLA_SAMPA_Pos)) 310 #define SERCOM_USART_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_USART_CTRLA) Frame Format */ 311 #define SERCOM_USART_CTRLA_FORM_Msk (_U_(0xF) << SERCOM_USART_CTRLA_FORM_Pos) 312 #define SERCOM_USART_CTRLA_FORM(value) (SERCOM_USART_CTRLA_FORM_Msk & ((value) << SERCOM_USART_CTRLA_FORM_Pos)) 313 #define SERCOM_USART_CTRLA_CMODE_Pos 28 /**< \brief (SERCOM_USART_CTRLA) Communication Mode */ 314 #define SERCOM_USART_CTRLA_CMODE (_U_(0x1) << SERCOM_USART_CTRLA_CMODE_Pos) 315 #define SERCOM_USART_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_USART_CTRLA) Clock Polarity */ 316 #define SERCOM_USART_CTRLA_CPOL (_U_(0x1) << SERCOM_USART_CTRLA_CPOL_Pos) 317 #define SERCOM_USART_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_USART_CTRLA) Data Order */ 318 #define SERCOM_USART_CTRLA_DORD (_U_(0x1) << SERCOM_USART_CTRLA_DORD_Pos) 319 #define SERCOM_USART_CTRLA_MASK _U_(0x7FF3E19F) /**< \brief (SERCOM_USART_CTRLA) MASK Register */ 320 321 /* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM I2CM Control B -------- */ 322 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 323 typedef union { 324 struct { 325 uint32_t :8; /*!< bit: 0.. 7 Reserved */ 326 uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */ 327 uint32_t QCEN:1; /*!< bit: 9 Quick Command Enable */ 328 uint32_t :6; /*!< bit: 10..15 Reserved */ 329 uint32_t CMD:2; /*!< bit: 16..17 Command */ 330 uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */ 331 uint32_t :13; /*!< bit: 19..31 Reserved */ 332 } bit; /*!< Structure used for bit access */ 333 uint32_t reg; /*!< Type used for register access */ 334 } SERCOM_I2CM_CTRLB_Type; 335 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 336 337 #define SERCOM_I2CM_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CM_CTRLB offset) I2CM Control B */ 338 #define SERCOM_I2CM_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_CTRLB reset_value) I2CM Control B */ 339 340 #define SERCOM_I2CM_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CM_CTRLB) Smart Mode Enable */ 341 #define SERCOM_I2CM_CTRLB_SMEN (_U_(0x1) << SERCOM_I2CM_CTRLB_SMEN_Pos) 342 #define SERCOM_I2CM_CTRLB_QCEN_Pos 9 /**< \brief (SERCOM_I2CM_CTRLB) Quick Command Enable */ 343 #define SERCOM_I2CM_CTRLB_QCEN (_U_(0x1) << SERCOM_I2CM_CTRLB_QCEN_Pos) 344 #define SERCOM_I2CM_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CM_CTRLB) Command */ 345 #define SERCOM_I2CM_CTRLB_CMD_Msk (_U_(0x3) << SERCOM_I2CM_CTRLB_CMD_Pos) 346 #define SERCOM_I2CM_CTRLB_CMD(value) (SERCOM_I2CM_CTRLB_CMD_Msk & ((value) << SERCOM_I2CM_CTRLB_CMD_Pos)) 347 #define SERCOM_I2CM_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CM_CTRLB) Acknowledge Action */ 348 #define SERCOM_I2CM_CTRLB_ACKACT (_U_(0x1) << SERCOM_I2CM_CTRLB_ACKACT_Pos) 349 #define SERCOM_I2CM_CTRLB_MASK _U_(0x00070300) /**< \brief (SERCOM_I2CM_CTRLB) MASK Register */ 350 351 /* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS I2CS Control B -------- */ 352 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 353 typedef union { 354 struct { 355 uint32_t :8; /*!< bit: 0.. 7 Reserved */ 356 uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */ 357 uint32_t GCMD:1; /*!< bit: 9 PMBus Group Command */ 358 uint32_t AACKEN:1; /*!< bit: 10 Automatic Address Acknowledge */ 359 uint32_t :3; /*!< bit: 11..13 Reserved */ 360 uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */ 361 uint32_t CMD:2; /*!< bit: 16..17 Command */ 362 uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */ 363 uint32_t :13; /*!< bit: 19..31 Reserved */ 364 } bit; /*!< Structure used for bit access */ 365 uint32_t reg; /*!< Type used for register access */ 366 } SERCOM_I2CS_CTRLB_Type; 367 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 368 369 #define SERCOM_I2CS_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CS_CTRLB offset) I2CS Control B */ 370 #define SERCOM_I2CS_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_CTRLB reset_value) I2CS Control B */ 371 372 #define SERCOM_I2CS_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CS_CTRLB) Smart Mode Enable */ 373 #define SERCOM_I2CS_CTRLB_SMEN (_U_(0x1) << SERCOM_I2CS_CTRLB_SMEN_Pos) 374 #define SERCOM_I2CS_CTRLB_GCMD_Pos 9 /**< \brief (SERCOM_I2CS_CTRLB) PMBus Group Command */ 375 #define SERCOM_I2CS_CTRLB_GCMD (_U_(0x1) << SERCOM_I2CS_CTRLB_GCMD_Pos) 376 #define SERCOM_I2CS_CTRLB_AACKEN_Pos 10 /**< \brief (SERCOM_I2CS_CTRLB) Automatic Address Acknowledge */ 377 #define SERCOM_I2CS_CTRLB_AACKEN (_U_(0x1) << SERCOM_I2CS_CTRLB_AACKEN_Pos) 378 #define SERCOM_I2CS_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_I2CS_CTRLB) Address Mode */ 379 #define SERCOM_I2CS_CTRLB_AMODE_Msk (_U_(0x3) << SERCOM_I2CS_CTRLB_AMODE_Pos) 380 #define SERCOM_I2CS_CTRLB_AMODE(value) (SERCOM_I2CS_CTRLB_AMODE_Msk & ((value) << SERCOM_I2CS_CTRLB_AMODE_Pos)) 381 #define SERCOM_I2CS_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CS_CTRLB) Command */ 382 #define SERCOM_I2CS_CTRLB_CMD_Msk (_U_(0x3) << SERCOM_I2CS_CTRLB_CMD_Pos) 383 #define SERCOM_I2CS_CTRLB_CMD(value) (SERCOM_I2CS_CTRLB_CMD_Msk & ((value) << SERCOM_I2CS_CTRLB_CMD_Pos)) 384 #define SERCOM_I2CS_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CS_CTRLB) Acknowledge Action */ 385 #define SERCOM_I2CS_CTRLB_ACKACT (_U_(0x1) << SERCOM_I2CS_CTRLB_ACKACT_Pos) 386 #define SERCOM_I2CS_CTRLB_MASK _U_(0x0007C700) /**< \brief (SERCOM_I2CS_CTRLB) MASK Register */ 387 388 /* -------- SERCOM_SPI_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPI SPI Control B -------- */ 389 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 390 typedef union { 391 struct { 392 uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */ 393 uint32_t :3; /*!< bit: 3.. 5 Reserved */ 394 uint32_t PLOADEN:1; /*!< bit: 6 Data Preload Enable */ 395 uint32_t :2; /*!< bit: 7.. 8 Reserved */ 396 uint32_t SSDE:1; /*!< bit: 9 Slave Select Low Detect Enable */ 397 uint32_t :3; /*!< bit: 10..12 Reserved */ 398 uint32_t MSSEN:1; /*!< bit: 13 Master Slave Select Enable */ 399 uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */ 400 uint32_t :1; /*!< bit: 16 Reserved */ 401 uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */ 402 uint32_t :14; /*!< bit: 18..31 Reserved */ 403 } bit; /*!< Structure used for bit access */ 404 uint32_t reg; /*!< Type used for register access */ 405 } SERCOM_SPI_CTRLB_Type; 406 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 407 408 #define SERCOM_SPI_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_SPI_CTRLB offset) SPI Control B */ 409 #define SERCOM_SPI_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_CTRLB reset_value) SPI Control B */ 410 411 #define SERCOM_SPI_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_SPI_CTRLB) Character Size */ 412 #define SERCOM_SPI_CTRLB_CHSIZE_Msk (_U_(0x7) << SERCOM_SPI_CTRLB_CHSIZE_Pos) 413 #define SERCOM_SPI_CTRLB_CHSIZE(value) (SERCOM_SPI_CTRLB_CHSIZE_Msk & ((value) << SERCOM_SPI_CTRLB_CHSIZE_Pos)) 414 #define SERCOM_SPI_CTRLB_PLOADEN_Pos 6 /**< \brief (SERCOM_SPI_CTRLB) Data Preload Enable */ 415 #define SERCOM_SPI_CTRLB_PLOADEN (_U_(0x1) << SERCOM_SPI_CTRLB_PLOADEN_Pos) 416 #define SERCOM_SPI_CTRLB_SSDE_Pos 9 /**< \brief (SERCOM_SPI_CTRLB) Slave Select Low Detect Enable */ 417 #define SERCOM_SPI_CTRLB_SSDE (_U_(0x1) << SERCOM_SPI_CTRLB_SSDE_Pos) 418 #define SERCOM_SPI_CTRLB_MSSEN_Pos 13 /**< \brief (SERCOM_SPI_CTRLB) Master Slave Select Enable */ 419 #define SERCOM_SPI_CTRLB_MSSEN (_U_(0x1) << SERCOM_SPI_CTRLB_MSSEN_Pos) 420 #define SERCOM_SPI_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_SPI_CTRLB) Address Mode */ 421 #define SERCOM_SPI_CTRLB_AMODE_Msk (_U_(0x3) << SERCOM_SPI_CTRLB_AMODE_Pos) 422 #define SERCOM_SPI_CTRLB_AMODE(value) (SERCOM_SPI_CTRLB_AMODE_Msk & ((value) << SERCOM_SPI_CTRLB_AMODE_Pos)) 423 #define SERCOM_SPI_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_SPI_CTRLB) Receiver Enable */ 424 #define SERCOM_SPI_CTRLB_RXEN (_U_(0x1) << SERCOM_SPI_CTRLB_RXEN_Pos) 425 #define SERCOM_SPI_CTRLB_MASK _U_(0x0002E247) /**< \brief (SERCOM_SPI_CTRLB) MASK Register */ 426 427 /* -------- SERCOM_USART_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART USART Control B -------- */ 428 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 429 typedef union { 430 struct { 431 uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */ 432 uint32_t :3; /*!< bit: 3.. 5 Reserved */ 433 uint32_t SBMODE:1; /*!< bit: 6 Stop Bit Mode */ 434 uint32_t :1; /*!< bit: 7 Reserved */ 435 uint32_t COLDEN:1; /*!< bit: 8 Collision Detection Enable */ 436 uint32_t SFDE:1; /*!< bit: 9 Start of Frame Detection Enable */ 437 uint32_t ENC:1; /*!< bit: 10 Encoding Format */ 438 uint32_t :2; /*!< bit: 11..12 Reserved */ 439 uint32_t PMODE:1; /*!< bit: 13 Parity Mode */ 440 uint32_t :2; /*!< bit: 14..15 Reserved */ 441 uint32_t TXEN:1; /*!< bit: 16 Transmitter Enable */ 442 uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */ 443 uint32_t :14; /*!< bit: 18..31 Reserved */ 444 } bit; /*!< Structure used for bit access */ 445 uint32_t reg; /*!< Type used for register access */ 446 } SERCOM_USART_CTRLB_Type; 447 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 448 449 #define SERCOM_USART_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_USART_CTRLB offset) USART Control B */ 450 #define SERCOM_USART_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_CTRLB reset_value) USART Control B */ 451 452 #define SERCOM_USART_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_USART_CTRLB) Character Size */ 453 #define SERCOM_USART_CTRLB_CHSIZE_Msk (_U_(0x7) << SERCOM_USART_CTRLB_CHSIZE_Pos) 454 #define SERCOM_USART_CTRLB_CHSIZE(value) (SERCOM_USART_CTRLB_CHSIZE_Msk & ((value) << SERCOM_USART_CTRLB_CHSIZE_Pos)) 455 #define SERCOM_USART_CTRLB_SBMODE_Pos 6 /**< \brief (SERCOM_USART_CTRLB) Stop Bit Mode */ 456 #define SERCOM_USART_CTRLB_SBMODE (_U_(0x1) << SERCOM_USART_CTRLB_SBMODE_Pos) 457 #define SERCOM_USART_CTRLB_COLDEN_Pos 8 /**< \brief (SERCOM_USART_CTRLB) Collision Detection Enable */ 458 #define SERCOM_USART_CTRLB_COLDEN (_U_(0x1) << SERCOM_USART_CTRLB_COLDEN_Pos) 459 #define SERCOM_USART_CTRLB_SFDE_Pos 9 /**< \brief (SERCOM_USART_CTRLB) Start of Frame Detection Enable */ 460 #define SERCOM_USART_CTRLB_SFDE (_U_(0x1) << SERCOM_USART_CTRLB_SFDE_Pos) 461 #define SERCOM_USART_CTRLB_ENC_Pos 10 /**< \brief (SERCOM_USART_CTRLB) Encoding Format */ 462 #define SERCOM_USART_CTRLB_ENC (_U_(0x1) << SERCOM_USART_CTRLB_ENC_Pos) 463 #define SERCOM_USART_CTRLB_PMODE_Pos 13 /**< \brief (SERCOM_USART_CTRLB) Parity Mode */ 464 #define SERCOM_USART_CTRLB_PMODE (_U_(0x1) << SERCOM_USART_CTRLB_PMODE_Pos) 465 #define SERCOM_USART_CTRLB_TXEN_Pos 16 /**< \brief (SERCOM_USART_CTRLB) Transmitter Enable */ 466 #define SERCOM_USART_CTRLB_TXEN (_U_(0x1) << SERCOM_USART_CTRLB_TXEN_Pos) 467 #define SERCOM_USART_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_USART_CTRLB) Receiver Enable */ 468 #define SERCOM_USART_CTRLB_RXEN (_U_(0x1) << SERCOM_USART_CTRLB_RXEN_Pos) 469 #define SERCOM_USART_CTRLB_MASK _U_(0x00032747) /**< \brief (SERCOM_USART_CTRLB) MASK Register */ 470 471 /* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0C) (R/W 32) I2CM I2CM Baud Rate -------- */ 472 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 473 typedef union { 474 struct { 475 uint32_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */ 476 uint32_t BAUDLOW:8; /*!< bit: 8..15 Baud Rate Value Low */ 477 uint32_t HSBAUD:8; /*!< bit: 16..23 High Speed Baud Rate Value */ 478 uint32_t HSBAUDLOW:8; /*!< bit: 24..31 High Speed Baud Rate Value Low */ 479 } bit; /*!< Structure used for bit access */ 480 uint32_t reg; /*!< Type used for register access */ 481 } SERCOM_I2CM_BAUD_Type; 482 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 483 484 #define SERCOM_I2CM_BAUD_OFFSET 0x0C /**< \brief (SERCOM_I2CM_BAUD offset) I2CM Baud Rate */ 485 #define SERCOM_I2CM_BAUD_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_BAUD reset_value) I2CM Baud Rate */ 486 487 #define SERCOM_I2CM_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value */ 488 #define SERCOM_I2CM_BAUD_BAUD_Msk (_U_(0xFF) << SERCOM_I2CM_BAUD_BAUD_Pos) 489 #define SERCOM_I2CM_BAUD_BAUD(value) (SERCOM_I2CM_BAUD_BAUD_Msk & ((value) << SERCOM_I2CM_BAUD_BAUD_Pos)) 490 #define SERCOM_I2CM_BAUD_BAUDLOW_Pos 8 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value Low */ 491 #define SERCOM_I2CM_BAUD_BAUDLOW_Msk (_U_(0xFF) << SERCOM_I2CM_BAUD_BAUDLOW_Pos) 492 #define SERCOM_I2CM_BAUD_BAUDLOW(value) (SERCOM_I2CM_BAUD_BAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_BAUDLOW_Pos)) 493 #define SERCOM_I2CM_BAUD_HSBAUD_Pos 16 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value */ 494 #define SERCOM_I2CM_BAUD_HSBAUD_Msk (_U_(0xFF) << SERCOM_I2CM_BAUD_HSBAUD_Pos) 495 #define SERCOM_I2CM_BAUD_HSBAUD(value) (SERCOM_I2CM_BAUD_HSBAUD_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUD_Pos)) 496 #define SERCOM_I2CM_BAUD_HSBAUDLOW_Pos 24 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Low */ 497 #define SERCOM_I2CM_BAUD_HSBAUDLOW_Msk (_U_(0xFF) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos) 498 #define SERCOM_I2CM_BAUD_HSBAUDLOW(value) (SERCOM_I2CM_BAUD_HSBAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos)) 499 #define SERCOM_I2CM_BAUD_MASK _U_(0xFFFFFFFF) /**< \brief (SERCOM_I2CM_BAUD) MASK Register */ 500 501 /* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0C) (R/W 8) SPI SPI Baud Rate -------- */ 502 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 503 typedef union { 504 struct { 505 uint8_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */ 506 } bit; /*!< Structure used for bit access */ 507 uint8_t reg; /*!< Type used for register access */ 508 } SERCOM_SPI_BAUD_Type; 509 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 510 511 #define SERCOM_SPI_BAUD_OFFSET 0x0C /**< \brief (SERCOM_SPI_BAUD offset) SPI Baud Rate */ 512 #define SERCOM_SPI_BAUD_RESETVALUE _U_(0x00) /**< \brief (SERCOM_SPI_BAUD reset_value) SPI Baud Rate */ 513 514 #define SERCOM_SPI_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_SPI_BAUD) Baud Rate Value */ 515 #define SERCOM_SPI_BAUD_BAUD_Msk (_U_(0xFF) << SERCOM_SPI_BAUD_BAUD_Pos) 516 #define SERCOM_SPI_BAUD_BAUD(value) (SERCOM_SPI_BAUD_BAUD_Msk & ((value) << SERCOM_SPI_BAUD_BAUD_Pos)) 517 #define SERCOM_SPI_BAUD_MASK _U_(0xFF) /**< \brief (SERCOM_SPI_BAUD) MASK Register */ 518 519 /* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART USART Baud Rate -------- */ 520 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 521 typedef union { 522 struct { 523 uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */ 524 } bit; /*!< Structure used for bit access */ 525 struct { // FRAC mode 526 uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */ 527 uint16_t FP:3; /*!< bit: 13..15 Fractional Part */ 528 } FRAC; /*!< Structure used for FRAC */ 529 struct { // FRACFP mode 530 uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */ 531 uint16_t FP:3; /*!< bit: 13..15 Fractional Part */ 532 } FRACFP; /*!< Structure used for FRACFP */ 533 struct { // USARTFP mode 534 uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */ 535 } USARTFP; /*!< Structure used for USARTFP */ 536 uint16_t reg; /*!< Type used for register access */ 537 } SERCOM_USART_BAUD_Type; 538 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 539 540 #define SERCOM_USART_BAUD_OFFSET 0x0C /**< \brief (SERCOM_USART_BAUD offset) USART Baud Rate */ 541 #define SERCOM_USART_BAUD_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_USART_BAUD reset_value) USART Baud Rate */ 542 543 #define SERCOM_USART_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD) Baud Rate Value */ 544 #define SERCOM_USART_BAUD_BAUD_Msk (_U_(0xFFFF) << SERCOM_USART_BAUD_BAUD_Pos) 545 #define SERCOM_USART_BAUD_BAUD(value) (SERCOM_USART_BAUD_BAUD_Msk & ((value) << SERCOM_USART_BAUD_BAUD_Pos)) 546 #define SERCOM_USART_BAUD_MASK _U_(0xFFFF) /**< \brief (SERCOM_USART_BAUD) MASK Register */ 547 548 // FRAC mode 549 #define SERCOM_USART_BAUD_FRAC_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRAC) Baud Rate Value */ 550 #define SERCOM_USART_BAUD_FRAC_BAUD_Msk (_U_(0x1FFF) << SERCOM_USART_BAUD_FRAC_BAUD_Pos) 551 #define SERCOM_USART_BAUD_FRAC_BAUD(value) (SERCOM_USART_BAUD_FRAC_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRAC_BAUD_Pos)) 552 #define SERCOM_USART_BAUD_FRAC_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRAC) Fractional Part */ 553 #define SERCOM_USART_BAUD_FRAC_FP_Msk (_U_(0x7) << SERCOM_USART_BAUD_FRAC_FP_Pos) 554 #define SERCOM_USART_BAUD_FRAC_FP(value) (SERCOM_USART_BAUD_FRAC_FP_Msk & ((value) << SERCOM_USART_BAUD_FRAC_FP_Pos)) 555 #define SERCOM_USART_BAUD_FRAC_MASK _U_(0xFFFF) /**< \brief (SERCOM_USART_BAUD_FRAC) MASK Register */ 556 557 // FRACFP mode 558 #define SERCOM_USART_BAUD_FRACFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRACFP) Baud Rate Value */ 559 #define SERCOM_USART_BAUD_FRACFP_BAUD_Msk (_U_(0x1FFF) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos) 560 #define SERCOM_USART_BAUD_FRACFP_BAUD(value) (SERCOM_USART_BAUD_FRACFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos)) 561 #define SERCOM_USART_BAUD_FRACFP_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRACFP) Fractional Part */ 562 #define SERCOM_USART_BAUD_FRACFP_FP_Msk (_U_(0x7) << SERCOM_USART_BAUD_FRACFP_FP_Pos) 563 #define SERCOM_USART_BAUD_FRACFP_FP(value) (SERCOM_USART_BAUD_FRACFP_FP_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_FP_Pos)) 564 #define SERCOM_USART_BAUD_FRACFP_MASK _U_(0xFFFF) /**< \brief (SERCOM_USART_BAUD_FRACFP) MASK Register */ 565 566 // USARTFP mode 567 #define SERCOM_USART_BAUD_USARTFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_USARTFP) Baud Rate Value */ 568 #define SERCOM_USART_BAUD_USARTFP_BAUD_Msk (_U_(0xFFFF) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos) 569 #define SERCOM_USART_BAUD_USARTFP_BAUD(value) (SERCOM_USART_BAUD_USARTFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos)) 570 #define SERCOM_USART_BAUD_USARTFP_MASK _U_(0xFFFF) /**< \brief (SERCOM_USART_BAUD_USARTFP) MASK Register */ 571 572 /* -------- SERCOM_USART_RXPL : (SERCOM Offset: 0x0E) (R/W 8) USART USART Receive Pulse Length -------- */ 573 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 574 typedef union { 575 struct { 576 uint8_t RXPL:8; /*!< bit: 0.. 7 Receive Pulse Length */ 577 } bit; /*!< Structure used for bit access */ 578 uint8_t reg; /*!< Type used for register access */ 579 } SERCOM_USART_RXPL_Type; 580 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 581 582 #define SERCOM_USART_RXPL_OFFSET 0x0E /**< \brief (SERCOM_USART_RXPL offset) USART Receive Pulse Length */ 583 #define SERCOM_USART_RXPL_RESETVALUE _U_(0x00) /**< \brief (SERCOM_USART_RXPL reset_value) USART Receive Pulse Length */ 584 585 #define SERCOM_USART_RXPL_RXPL_Pos 0 /**< \brief (SERCOM_USART_RXPL) Receive Pulse Length */ 586 #define SERCOM_USART_RXPL_RXPL_Msk (_U_(0xFF) << SERCOM_USART_RXPL_RXPL_Pos) 587 #define SERCOM_USART_RXPL_RXPL(value) (SERCOM_USART_RXPL_RXPL_Msk & ((value) << SERCOM_USART_RXPL_RXPL_Pos)) 588 #define SERCOM_USART_RXPL_MASK _U_(0xFF) /**< \brief (SERCOM_USART_RXPL) MASK Register */ 589 590 /* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CM I2CM Interrupt Enable Clear -------- */ 591 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 592 typedef union { 593 struct { 594 uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Disable */ 595 uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Disable */ 596 uint8_t :5; /*!< bit: 2.. 6 Reserved */ 597 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ 598 } bit; /*!< Structure used for bit access */ 599 uint8_t reg; /*!< Type used for register access */ 600 } SERCOM_I2CM_INTENCLR_Type; 601 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 602 603 #define SERCOM_I2CM_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_I2CM_INTENCLR offset) I2CM Interrupt Enable Clear */ 604 #define SERCOM_I2CM_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CM_INTENCLR reset_value) I2CM Interrupt Enable Clear */ 605 606 #define SERCOM_I2CM_INTENCLR_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENCLR) Master On Bus Interrupt Disable */ 607 #define SERCOM_I2CM_INTENCLR_MB (_U_(0x1) << SERCOM_I2CM_INTENCLR_MB_Pos) 608 #define SERCOM_I2CM_INTENCLR_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENCLR) Slave On Bus Interrupt Disable */ 609 #define SERCOM_I2CM_INTENCLR_SB (_U_(0x1) << SERCOM_I2CM_INTENCLR_SB_Pos) 610 #define SERCOM_I2CM_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTENCLR) Combined Error Interrupt Disable */ 611 #define SERCOM_I2CM_INTENCLR_ERROR (_U_(0x1) << SERCOM_I2CM_INTENCLR_ERROR_Pos) 612 #define SERCOM_I2CM_INTENCLR_MASK _U_(0x83) /**< \brief (SERCOM_I2CM_INTENCLR) MASK Register */ 613 614 /* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CS I2CS Interrupt Enable Clear -------- */ 615 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 616 typedef union { 617 struct { 618 uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Disable */ 619 uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Disable */ 620 uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Disable */ 621 uint8_t :4; /*!< bit: 3.. 6 Reserved */ 622 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ 623 } bit; /*!< Structure used for bit access */ 624 uint8_t reg; /*!< Type used for register access */ 625 } SERCOM_I2CS_INTENCLR_Type; 626 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 627 628 #define SERCOM_I2CS_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_I2CS_INTENCLR offset) I2CS Interrupt Enable Clear */ 629 #define SERCOM_I2CS_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CS_INTENCLR reset_value) I2CS Interrupt Enable Clear */ 630 631 #define SERCOM_I2CS_INTENCLR_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENCLR) Stop Received Interrupt Disable */ 632 #define SERCOM_I2CS_INTENCLR_PREC (_U_(0x1) << SERCOM_I2CS_INTENCLR_PREC_Pos) 633 #define SERCOM_I2CS_INTENCLR_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENCLR) Address Match Interrupt Disable */ 634 #define SERCOM_I2CS_INTENCLR_AMATCH (_U_(0x1) << SERCOM_I2CS_INTENCLR_AMATCH_Pos) 635 #define SERCOM_I2CS_INTENCLR_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENCLR) Data Interrupt Disable */ 636 #define SERCOM_I2CS_INTENCLR_DRDY (_U_(0x1) << SERCOM_I2CS_INTENCLR_DRDY_Pos) 637 #define SERCOM_I2CS_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTENCLR) Combined Error Interrupt Disable */ 638 #define SERCOM_I2CS_INTENCLR_ERROR (_U_(0x1) << SERCOM_I2CS_INTENCLR_ERROR_Pos) 639 #define SERCOM_I2CS_INTENCLR_MASK _U_(0x87) /**< \brief (SERCOM_I2CS_INTENCLR) MASK Register */ 640 641 /* -------- SERCOM_SPI_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) SPI SPI Interrupt Enable Clear -------- */ 642 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 643 typedef union { 644 struct { 645 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */ 646 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */ 647 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */ 648 uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Disable */ 649 uint8_t :3; /*!< bit: 4.. 6 Reserved */ 650 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ 651 } bit; /*!< Structure used for bit access */ 652 uint8_t reg; /*!< Type used for register access */ 653 } SERCOM_SPI_INTENCLR_Type; 654 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 655 656 #define SERCOM_SPI_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_SPI_INTENCLR offset) SPI Interrupt Enable Clear */ 657 #define SERCOM_SPI_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (SERCOM_SPI_INTENCLR reset_value) SPI Interrupt Enable Clear */ 658 659 #define SERCOM_SPI_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENCLR) Data Register Empty Interrupt Disable */ 660 #define SERCOM_SPI_INTENCLR_DRE (_U_(0x1) << SERCOM_SPI_INTENCLR_DRE_Pos) 661 #define SERCOM_SPI_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENCLR) Transmit Complete Interrupt Disable */ 662 #define SERCOM_SPI_INTENCLR_TXC (_U_(0x1) << SERCOM_SPI_INTENCLR_TXC_Pos) 663 #define SERCOM_SPI_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENCLR) Receive Complete Interrupt Disable */ 664 #define SERCOM_SPI_INTENCLR_RXC (_U_(0x1) << SERCOM_SPI_INTENCLR_RXC_Pos) 665 #define SERCOM_SPI_INTENCLR_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTENCLR) Slave Select Low Interrupt Disable */ 666 #define SERCOM_SPI_INTENCLR_SSL (_U_(0x1) << SERCOM_SPI_INTENCLR_SSL_Pos) 667 #define SERCOM_SPI_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTENCLR) Combined Error Interrupt Disable */ 668 #define SERCOM_SPI_INTENCLR_ERROR (_U_(0x1) << SERCOM_SPI_INTENCLR_ERROR_Pos) 669 #define SERCOM_SPI_INTENCLR_MASK _U_(0x8F) /**< \brief (SERCOM_SPI_INTENCLR) MASK Register */ 670 671 /* -------- SERCOM_USART_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) USART USART Interrupt Enable Clear -------- */ 672 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 673 typedef union { 674 struct { 675 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */ 676 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */ 677 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */ 678 uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Disable */ 679 uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Disable */ 680 uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Disable */ 681 uint8_t :1; /*!< bit: 6 Reserved */ 682 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ 683 } bit; /*!< Structure used for bit access */ 684 uint8_t reg; /*!< Type used for register access */ 685 } SERCOM_USART_INTENCLR_Type; 686 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 687 688 #define SERCOM_USART_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_USART_INTENCLR offset) USART Interrupt Enable Clear */ 689 #define SERCOM_USART_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (SERCOM_USART_INTENCLR reset_value) USART Interrupt Enable Clear */ 690 691 #define SERCOM_USART_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENCLR) Data Register Empty Interrupt Disable */ 692 #define SERCOM_USART_INTENCLR_DRE (_U_(0x1) << SERCOM_USART_INTENCLR_DRE_Pos) 693 #define SERCOM_USART_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENCLR) Transmit Complete Interrupt Disable */ 694 #define SERCOM_USART_INTENCLR_TXC (_U_(0x1) << SERCOM_USART_INTENCLR_TXC_Pos) 695 #define SERCOM_USART_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENCLR) Receive Complete Interrupt Disable */ 696 #define SERCOM_USART_INTENCLR_RXC (_U_(0x1) << SERCOM_USART_INTENCLR_RXC_Pos) 697 #define SERCOM_USART_INTENCLR_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENCLR) Receive Start Interrupt Disable */ 698 #define SERCOM_USART_INTENCLR_RXS (_U_(0x1) << SERCOM_USART_INTENCLR_RXS_Pos) 699 #define SERCOM_USART_INTENCLR_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTENCLR) Clear To Send Input Change Interrupt Disable */ 700 #define SERCOM_USART_INTENCLR_CTSIC (_U_(0x1) << SERCOM_USART_INTENCLR_CTSIC_Pos) 701 #define SERCOM_USART_INTENCLR_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTENCLR) Break Received Interrupt Disable */ 702 #define SERCOM_USART_INTENCLR_RXBRK (_U_(0x1) << SERCOM_USART_INTENCLR_RXBRK_Pos) 703 #define SERCOM_USART_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTENCLR) Combined Error Interrupt Disable */ 704 #define SERCOM_USART_INTENCLR_ERROR (_U_(0x1) << SERCOM_USART_INTENCLR_ERROR_Pos) 705 #define SERCOM_USART_INTENCLR_MASK _U_(0xBF) /**< \brief (SERCOM_USART_INTENCLR) MASK Register */ 706 707 /* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CM I2CM Interrupt Enable Set -------- */ 708 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 709 typedef union { 710 struct { 711 uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Enable */ 712 uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Enable */ 713 uint8_t :5; /*!< bit: 2.. 6 Reserved */ 714 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ 715 } bit; /*!< Structure used for bit access */ 716 uint8_t reg; /*!< Type used for register access */ 717 } SERCOM_I2CM_INTENSET_Type; 718 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 719 720 #define SERCOM_I2CM_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_I2CM_INTENSET offset) I2CM Interrupt Enable Set */ 721 #define SERCOM_I2CM_INTENSET_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CM_INTENSET reset_value) I2CM Interrupt Enable Set */ 722 723 #define SERCOM_I2CM_INTENSET_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENSET) Master On Bus Interrupt Enable */ 724 #define SERCOM_I2CM_INTENSET_MB (_U_(0x1) << SERCOM_I2CM_INTENSET_MB_Pos) 725 #define SERCOM_I2CM_INTENSET_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENSET) Slave On Bus Interrupt Enable */ 726 #define SERCOM_I2CM_INTENSET_SB (_U_(0x1) << SERCOM_I2CM_INTENSET_SB_Pos) 727 #define SERCOM_I2CM_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTENSET) Combined Error Interrupt Enable */ 728 #define SERCOM_I2CM_INTENSET_ERROR (_U_(0x1) << SERCOM_I2CM_INTENSET_ERROR_Pos) 729 #define SERCOM_I2CM_INTENSET_MASK _U_(0x83) /**< \brief (SERCOM_I2CM_INTENSET) MASK Register */ 730 731 /* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CS I2CS Interrupt Enable Set -------- */ 732 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 733 typedef union { 734 struct { 735 uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Enable */ 736 uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Enable */ 737 uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Enable */ 738 uint8_t :4; /*!< bit: 3.. 6 Reserved */ 739 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ 740 } bit; /*!< Structure used for bit access */ 741 uint8_t reg; /*!< Type used for register access */ 742 } SERCOM_I2CS_INTENSET_Type; 743 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 744 745 #define SERCOM_I2CS_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_I2CS_INTENSET offset) I2CS Interrupt Enable Set */ 746 #define SERCOM_I2CS_INTENSET_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CS_INTENSET reset_value) I2CS Interrupt Enable Set */ 747 748 #define SERCOM_I2CS_INTENSET_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENSET) Stop Received Interrupt Enable */ 749 #define SERCOM_I2CS_INTENSET_PREC (_U_(0x1) << SERCOM_I2CS_INTENSET_PREC_Pos) 750 #define SERCOM_I2CS_INTENSET_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENSET) Address Match Interrupt Enable */ 751 #define SERCOM_I2CS_INTENSET_AMATCH (_U_(0x1) << SERCOM_I2CS_INTENSET_AMATCH_Pos) 752 #define SERCOM_I2CS_INTENSET_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENSET) Data Interrupt Enable */ 753 #define SERCOM_I2CS_INTENSET_DRDY (_U_(0x1) << SERCOM_I2CS_INTENSET_DRDY_Pos) 754 #define SERCOM_I2CS_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTENSET) Combined Error Interrupt Enable */ 755 #define SERCOM_I2CS_INTENSET_ERROR (_U_(0x1) << SERCOM_I2CS_INTENSET_ERROR_Pos) 756 #define SERCOM_I2CS_INTENSET_MASK _U_(0x87) /**< \brief (SERCOM_I2CS_INTENSET) MASK Register */ 757 758 /* -------- SERCOM_SPI_INTENSET : (SERCOM Offset: 0x16) (R/W 8) SPI SPI Interrupt Enable Set -------- */ 759 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 760 typedef union { 761 struct { 762 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */ 763 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */ 764 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */ 765 uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Enable */ 766 uint8_t :3; /*!< bit: 4.. 6 Reserved */ 767 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ 768 } bit; /*!< Structure used for bit access */ 769 uint8_t reg; /*!< Type used for register access */ 770 } SERCOM_SPI_INTENSET_Type; 771 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 772 773 #define SERCOM_SPI_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_SPI_INTENSET offset) SPI Interrupt Enable Set */ 774 #define SERCOM_SPI_INTENSET_RESETVALUE _U_(0x00) /**< \brief (SERCOM_SPI_INTENSET reset_value) SPI Interrupt Enable Set */ 775 776 #define SERCOM_SPI_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENSET) Data Register Empty Interrupt Enable */ 777 #define SERCOM_SPI_INTENSET_DRE (_U_(0x1) << SERCOM_SPI_INTENSET_DRE_Pos) 778 #define SERCOM_SPI_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENSET) Transmit Complete Interrupt Enable */ 779 #define SERCOM_SPI_INTENSET_TXC (_U_(0x1) << SERCOM_SPI_INTENSET_TXC_Pos) 780 #define SERCOM_SPI_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENSET) Receive Complete Interrupt Enable */ 781 #define SERCOM_SPI_INTENSET_RXC (_U_(0x1) << SERCOM_SPI_INTENSET_RXC_Pos) 782 #define SERCOM_SPI_INTENSET_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTENSET) Slave Select Low Interrupt Enable */ 783 #define SERCOM_SPI_INTENSET_SSL (_U_(0x1) << SERCOM_SPI_INTENSET_SSL_Pos) 784 #define SERCOM_SPI_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTENSET) Combined Error Interrupt Enable */ 785 #define SERCOM_SPI_INTENSET_ERROR (_U_(0x1) << SERCOM_SPI_INTENSET_ERROR_Pos) 786 #define SERCOM_SPI_INTENSET_MASK _U_(0x8F) /**< \brief (SERCOM_SPI_INTENSET) MASK Register */ 787 788 /* -------- SERCOM_USART_INTENSET : (SERCOM Offset: 0x16) (R/W 8) USART USART Interrupt Enable Set -------- */ 789 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 790 typedef union { 791 struct { 792 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */ 793 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */ 794 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */ 795 uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Enable */ 796 uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Enable */ 797 uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Enable */ 798 uint8_t :1; /*!< bit: 6 Reserved */ 799 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ 800 } bit; /*!< Structure used for bit access */ 801 uint8_t reg; /*!< Type used for register access */ 802 } SERCOM_USART_INTENSET_Type; 803 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 804 805 #define SERCOM_USART_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_USART_INTENSET offset) USART Interrupt Enable Set */ 806 #define SERCOM_USART_INTENSET_RESETVALUE _U_(0x00) /**< \brief (SERCOM_USART_INTENSET reset_value) USART Interrupt Enable Set */ 807 808 #define SERCOM_USART_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENSET) Data Register Empty Interrupt Enable */ 809 #define SERCOM_USART_INTENSET_DRE (_U_(0x1) << SERCOM_USART_INTENSET_DRE_Pos) 810 #define SERCOM_USART_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENSET) Transmit Complete Interrupt Enable */ 811 #define SERCOM_USART_INTENSET_TXC (_U_(0x1) << SERCOM_USART_INTENSET_TXC_Pos) 812 #define SERCOM_USART_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENSET) Receive Complete Interrupt Enable */ 813 #define SERCOM_USART_INTENSET_RXC (_U_(0x1) << SERCOM_USART_INTENSET_RXC_Pos) 814 #define SERCOM_USART_INTENSET_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENSET) Receive Start Interrupt Enable */ 815 #define SERCOM_USART_INTENSET_RXS (_U_(0x1) << SERCOM_USART_INTENSET_RXS_Pos) 816 #define SERCOM_USART_INTENSET_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTENSET) Clear To Send Input Change Interrupt Enable */ 817 #define SERCOM_USART_INTENSET_CTSIC (_U_(0x1) << SERCOM_USART_INTENSET_CTSIC_Pos) 818 #define SERCOM_USART_INTENSET_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTENSET) Break Received Interrupt Enable */ 819 #define SERCOM_USART_INTENSET_RXBRK (_U_(0x1) << SERCOM_USART_INTENSET_RXBRK_Pos) 820 #define SERCOM_USART_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTENSET) Combined Error Interrupt Enable */ 821 #define SERCOM_USART_INTENSET_ERROR (_U_(0x1) << SERCOM_USART_INTENSET_ERROR_Pos) 822 #define SERCOM_USART_INTENSET_MASK _U_(0xBF) /**< \brief (SERCOM_USART_INTENSET) MASK Register */ 823 824 /* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CM I2CM Interrupt Flag Status and Clear -------- */ 825 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 826 typedef union { // __I to avoid read-modify-write on write-to-clear register 827 struct { 828 __I uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt */ 829 __I uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt */ 830 __I uint8_t :5; /*!< bit: 2.. 6 Reserved */ 831 __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ 832 } bit; /*!< Structure used for bit access */ 833 uint8_t reg; /*!< Type used for register access */ 834 } SERCOM_I2CM_INTFLAG_Type; 835 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 836 837 #define SERCOM_I2CM_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_I2CM_INTFLAG offset) I2CM Interrupt Flag Status and Clear */ 838 #define SERCOM_I2CM_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CM_INTFLAG reset_value) I2CM Interrupt Flag Status and Clear */ 839 840 #define SERCOM_I2CM_INTFLAG_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTFLAG) Master On Bus Interrupt */ 841 #define SERCOM_I2CM_INTFLAG_MB (_U_(0x1) << SERCOM_I2CM_INTFLAG_MB_Pos) 842 #define SERCOM_I2CM_INTFLAG_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTFLAG) Slave On Bus Interrupt */ 843 #define SERCOM_I2CM_INTFLAG_SB (_U_(0x1) << SERCOM_I2CM_INTFLAG_SB_Pos) 844 #define SERCOM_I2CM_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTFLAG) Combined Error Interrupt */ 845 #define SERCOM_I2CM_INTFLAG_ERROR (_U_(0x1) << SERCOM_I2CM_INTFLAG_ERROR_Pos) 846 #define SERCOM_I2CM_INTFLAG_MASK _U_(0x83) /**< \brief (SERCOM_I2CM_INTFLAG) MASK Register */ 847 848 /* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CS I2CS Interrupt Flag Status and Clear -------- */ 849 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 850 typedef union { // __I to avoid read-modify-write on write-to-clear register 851 struct { 852 __I uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt */ 853 __I uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt */ 854 __I uint8_t DRDY:1; /*!< bit: 2 Data Interrupt */ 855 __I uint8_t :4; /*!< bit: 3.. 6 Reserved */ 856 __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ 857 } bit; /*!< Structure used for bit access */ 858 uint8_t reg; /*!< Type used for register access */ 859 } SERCOM_I2CS_INTFLAG_Type; 860 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 861 862 #define SERCOM_I2CS_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_I2CS_INTFLAG offset) I2CS Interrupt Flag Status and Clear */ 863 #define SERCOM_I2CS_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CS_INTFLAG reset_value) I2CS Interrupt Flag Status and Clear */ 864 865 #define SERCOM_I2CS_INTFLAG_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTFLAG) Stop Received Interrupt */ 866 #define SERCOM_I2CS_INTFLAG_PREC (_U_(0x1) << SERCOM_I2CS_INTFLAG_PREC_Pos) 867 #define SERCOM_I2CS_INTFLAG_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTFLAG) Address Match Interrupt */ 868 #define SERCOM_I2CS_INTFLAG_AMATCH (_U_(0x1) << SERCOM_I2CS_INTFLAG_AMATCH_Pos) 869 #define SERCOM_I2CS_INTFLAG_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTFLAG) Data Interrupt */ 870 #define SERCOM_I2CS_INTFLAG_DRDY (_U_(0x1) << SERCOM_I2CS_INTFLAG_DRDY_Pos) 871 #define SERCOM_I2CS_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTFLAG) Combined Error Interrupt */ 872 #define SERCOM_I2CS_INTFLAG_ERROR (_U_(0x1) << SERCOM_I2CS_INTFLAG_ERROR_Pos) 873 #define SERCOM_I2CS_INTFLAG_MASK _U_(0x87) /**< \brief (SERCOM_I2CS_INTFLAG) MASK Register */ 874 875 /* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) SPI SPI Interrupt Flag Status and Clear -------- */ 876 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 877 typedef union { // __I to avoid read-modify-write on write-to-clear register 878 struct { 879 __I uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */ 880 __I uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */ 881 __I uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */ 882 __I uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Flag */ 883 __I uint8_t :3; /*!< bit: 4.. 6 Reserved */ 884 __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ 885 } bit; /*!< Structure used for bit access */ 886 uint8_t reg; /*!< Type used for register access */ 887 } SERCOM_SPI_INTFLAG_Type; 888 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 889 890 #define SERCOM_SPI_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_SPI_INTFLAG offset) SPI Interrupt Flag Status and Clear */ 891 #define SERCOM_SPI_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (SERCOM_SPI_INTFLAG reset_value) SPI Interrupt Flag Status and Clear */ 892 893 #define SERCOM_SPI_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTFLAG) Data Register Empty Interrupt */ 894 #define SERCOM_SPI_INTFLAG_DRE (_U_(0x1) << SERCOM_SPI_INTFLAG_DRE_Pos) 895 #define SERCOM_SPI_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTFLAG) Transmit Complete Interrupt */ 896 #define SERCOM_SPI_INTFLAG_TXC (_U_(0x1) << SERCOM_SPI_INTFLAG_TXC_Pos) 897 #define SERCOM_SPI_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTFLAG) Receive Complete Interrupt */ 898 #define SERCOM_SPI_INTFLAG_RXC (_U_(0x1) << SERCOM_SPI_INTFLAG_RXC_Pos) 899 #define SERCOM_SPI_INTFLAG_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTFLAG) Slave Select Low Interrupt Flag */ 900 #define SERCOM_SPI_INTFLAG_SSL (_U_(0x1) << SERCOM_SPI_INTFLAG_SSL_Pos) 901 #define SERCOM_SPI_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTFLAG) Combined Error Interrupt */ 902 #define SERCOM_SPI_INTFLAG_ERROR (_U_(0x1) << SERCOM_SPI_INTFLAG_ERROR_Pos) 903 #define SERCOM_SPI_INTFLAG_MASK _U_(0x8F) /**< \brief (SERCOM_SPI_INTFLAG) MASK Register */ 904 905 /* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) USART USART Interrupt Flag Status and Clear -------- */ 906 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 907 typedef union { // __I to avoid read-modify-write on write-to-clear register 908 struct { 909 __I uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */ 910 __I uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */ 911 __I uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */ 912 __I uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */ 913 __I uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt */ 914 __I uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt */ 915 __I uint8_t :1; /*!< bit: 6 Reserved */ 916 __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ 917 } bit; /*!< Structure used for bit access */ 918 uint8_t reg; /*!< Type used for register access */ 919 } SERCOM_USART_INTFLAG_Type; 920 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 921 922 #define SERCOM_USART_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_USART_INTFLAG offset) USART Interrupt Flag Status and Clear */ 923 #define SERCOM_USART_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (SERCOM_USART_INTFLAG reset_value) USART Interrupt Flag Status and Clear */ 924 925 #define SERCOM_USART_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_USART_INTFLAG) Data Register Empty Interrupt */ 926 #define SERCOM_USART_INTFLAG_DRE (_U_(0x1) << SERCOM_USART_INTFLAG_DRE_Pos) 927 #define SERCOM_USART_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_USART_INTFLAG) Transmit Complete Interrupt */ 928 #define SERCOM_USART_INTFLAG_TXC (_U_(0x1) << SERCOM_USART_INTFLAG_TXC_Pos) 929 #define SERCOM_USART_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_USART_INTFLAG) Receive Complete Interrupt */ 930 #define SERCOM_USART_INTFLAG_RXC (_U_(0x1) << SERCOM_USART_INTFLAG_RXC_Pos) 931 #define SERCOM_USART_INTFLAG_RXS_Pos 3 /**< \brief (SERCOM_USART_INTFLAG) Receive Start Interrupt */ 932 #define SERCOM_USART_INTFLAG_RXS (_U_(0x1) << SERCOM_USART_INTFLAG_RXS_Pos) 933 #define SERCOM_USART_INTFLAG_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTFLAG) Clear To Send Input Change Interrupt */ 934 #define SERCOM_USART_INTFLAG_CTSIC (_U_(0x1) << SERCOM_USART_INTFLAG_CTSIC_Pos) 935 #define SERCOM_USART_INTFLAG_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTFLAG) Break Received Interrupt */ 936 #define SERCOM_USART_INTFLAG_RXBRK (_U_(0x1) << SERCOM_USART_INTFLAG_RXBRK_Pos) 937 #define SERCOM_USART_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTFLAG) Combined Error Interrupt */ 938 #define SERCOM_USART_INTFLAG_ERROR (_U_(0x1) << SERCOM_USART_INTFLAG_ERROR_Pos) 939 #define SERCOM_USART_INTFLAG_MASK _U_(0xBF) /**< \brief (SERCOM_USART_INTFLAG) MASK Register */ 940 941 /* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CM I2CM Status -------- */ 942 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 943 typedef union { 944 struct { 945 uint16_t BUSERR:1; /*!< bit: 0 Bus Error */ 946 uint16_t ARBLOST:1; /*!< bit: 1 Arbitration Lost */ 947 uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */ 948 uint16_t :1; /*!< bit: 3 Reserved */ 949 uint16_t BUSSTATE:2; /*!< bit: 4.. 5 Bus State */ 950 uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */ 951 uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */ 952 uint16_t MEXTTOUT:1; /*!< bit: 8 Master SCL Low Extend Timeout */ 953 uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */ 954 uint16_t LENERR:1; /*!< bit: 10 Length Error */ 955 uint16_t :5; /*!< bit: 11..15 Reserved */ 956 } bit; /*!< Structure used for bit access */ 957 uint16_t reg; /*!< Type used for register access */ 958 } SERCOM_I2CM_STATUS_Type; 959 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 960 961 #define SERCOM_I2CM_STATUS_OFFSET 0x1A /**< \brief (SERCOM_I2CM_STATUS offset) I2CM Status */ 962 #define SERCOM_I2CM_STATUS_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_I2CM_STATUS reset_value) I2CM Status */ 963 964 #define SERCOM_I2CM_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CM_STATUS) Bus Error */ 965 #define SERCOM_I2CM_STATUS_BUSERR (_U_(0x1) << SERCOM_I2CM_STATUS_BUSERR_Pos) 966 #define SERCOM_I2CM_STATUS_ARBLOST_Pos 1 /**< \brief (SERCOM_I2CM_STATUS) Arbitration Lost */ 967 #define SERCOM_I2CM_STATUS_ARBLOST (_U_(0x1) << SERCOM_I2CM_STATUS_ARBLOST_Pos) 968 #define SERCOM_I2CM_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CM_STATUS) Received Not Acknowledge */ 969 #define SERCOM_I2CM_STATUS_RXNACK (_U_(0x1) << SERCOM_I2CM_STATUS_RXNACK_Pos) 970 #define SERCOM_I2CM_STATUS_BUSSTATE_Pos 4 /**< \brief (SERCOM_I2CM_STATUS) Bus State */ 971 #define SERCOM_I2CM_STATUS_BUSSTATE_Msk (_U_(0x3) << SERCOM_I2CM_STATUS_BUSSTATE_Pos) 972 #define SERCOM_I2CM_STATUS_BUSSTATE(value) (SERCOM_I2CM_STATUS_BUSSTATE_Msk & ((value) << SERCOM_I2CM_STATUS_BUSSTATE_Pos)) 973 #define SERCOM_I2CM_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CM_STATUS) SCL Low Timeout */ 974 #define SERCOM_I2CM_STATUS_LOWTOUT (_U_(0x1) << SERCOM_I2CM_STATUS_LOWTOUT_Pos) 975 #define SERCOM_I2CM_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CM_STATUS) Clock Hold */ 976 #define SERCOM_I2CM_STATUS_CLKHOLD (_U_(0x1) << SERCOM_I2CM_STATUS_CLKHOLD_Pos) 977 #define SERCOM_I2CM_STATUS_MEXTTOUT_Pos 8 /**< \brief (SERCOM_I2CM_STATUS) Master SCL Low Extend Timeout */ 978 #define SERCOM_I2CM_STATUS_MEXTTOUT (_U_(0x1) << SERCOM_I2CM_STATUS_MEXTTOUT_Pos) 979 #define SERCOM_I2CM_STATUS_SEXTTOUT_Pos 9 /**< \brief (SERCOM_I2CM_STATUS) Slave SCL Low Extend Timeout */ 980 #define SERCOM_I2CM_STATUS_SEXTTOUT (_U_(0x1) << SERCOM_I2CM_STATUS_SEXTTOUT_Pos) 981 #define SERCOM_I2CM_STATUS_LENERR_Pos 10 /**< \brief (SERCOM_I2CM_STATUS) Length Error */ 982 #define SERCOM_I2CM_STATUS_LENERR (_U_(0x1) << SERCOM_I2CM_STATUS_LENERR_Pos) 983 #define SERCOM_I2CM_STATUS_MASK _U_(0x07F7) /**< \brief (SERCOM_I2CM_STATUS) MASK Register */ 984 985 /* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CS I2CS Status -------- */ 986 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 987 typedef union { 988 struct { 989 uint16_t BUSERR:1; /*!< bit: 0 Bus Error */ 990 uint16_t COLL:1; /*!< bit: 1 Transmit Collision */ 991 uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */ 992 uint16_t DIR:1; /*!< bit: 3 Read/Write Direction */ 993 uint16_t SR:1; /*!< bit: 4 Repeated Start */ 994 uint16_t :1; /*!< bit: 5 Reserved */ 995 uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */ 996 uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */ 997 uint16_t :1; /*!< bit: 8 Reserved */ 998 uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */ 999 uint16_t HS:1; /*!< bit: 10 High Speed */ 1000 uint16_t :5; /*!< bit: 11..15 Reserved */ 1001 } bit; /*!< Structure used for bit access */ 1002 uint16_t reg; /*!< Type used for register access */ 1003 } SERCOM_I2CS_STATUS_Type; 1004 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1005 1006 #define SERCOM_I2CS_STATUS_OFFSET 0x1A /**< \brief (SERCOM_I2CS_STATUS offset) I2CS Status */ 1007 #define SERCOM_I2CS_STATUS_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_I2CS_STATUS reset_value) I2CS Status */ 1008 1009 #define SERCOM_I2CS_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CS_STATUS) Bus Error */ 1010 #define SERCOM_I2CS_STATUS_BUSERR (_U_(0x1) << SERCOM_I2CS_STATUS_BUSERR_Pos) 1011 #define SERCOM_I2CS_STATUS_COLL_Pos 1 /**< \brief (SERCOM_I2CS_STATUS) Transmit Collision */ 1012 #define SERCOM_I2CS_STATUS_COLL (_U_(0x1) << SERCOM_I2CS_STATUS_COLL_Pos) 1013 #define SERCOM_I2CS_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CS_STATUS) Received Not Acknowledge */ 1014 #define SERCOM_I2CS_STATUS_RXNACK (_U_(0x1) << SERCOM_I2CS_STATUS_RXNACK_Pos) 1015 #define SERCOM_I2CS_STATUS_DIR_Pos 3 /**< \brief (SERCOM_I2CS_STATUS) Read/Write Direction */ 1016 #define SERCOM_I2CS_STATUS_DIR (_U_(0x1) << SERCOM_I2CS_STATUS_DIR_Pos) 1017 #define SERCOM_I2CS_STATUS_SR_Pos 4 /**< \brief (SERCOM_I2CS_STATUS) Repeated Start */ 1018 #define SERCOM_I2CS_STATUS_SR (_U_(0x1) << SERCOM_I2CS_STATUS_SR_Pos) 1019 #define SERCOM_I2CS_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CS_STATUS) SCL Low Timeout */ 1020 #define SERCOM_I2CS_STATUS_LOWTOUT (_U_(0x1) << SERCOM_I2CS_STATUS_LOWTOUT_Pos) 1021 #define SERCOM_I2CS_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CS_STATUS) Clock Hold */ 1022 #define SERCOM_I2CS_STATUS_CLKHOLD (_U_(0x1) << SERCOM_I2CS_STATUS_CLKHOLD_Pos) 1023 #define SERCOM_I2CS_STATUS_SEXTTOUT_Pos 9 /**< \brief (SERCOM_I2CS_STATUS) Slave SCL Low Extend Timeout */ 1024 #define SERCOM_I2CS_STATUS_SEXTTOUT (_U_(0x1) << SERCOM_I2CS_STATUS_SEXTTOUT_Pos) 1025 #define SERCOM_I2CS_STATUS_HS_Pos 10 /**< \brief (SERCOM_I2CS_STATUS) High Speed */ 1026 #define SERCOM_I2CS_STATUS_HS (_U_(0x1) << SERCOM_I2CS_STATUS_HS_Pos) 1027 #define SERCOM_I2CS_STATUS_MASK _U_(0x06DF) /**< \brief (SERCOM_I2CS_STATUS) MASK Register */ 1028 1029 /* -------- SERCOM_SPI_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPI SPI Status -------- */ 1030 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1031 typedef union { 1032 struct { 1033 uint16_t :2; /*!< bit: 0.. 1 Reserved */ 1034 uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */ 1035 uint16_t :13; /*!< bit: 3..15 Reserved */ 1036 } bit; /*!< Structure used for bit access */ 1037 uint16_t reg; /*!< Type used for register access */ 1038 } SERCOM_SPI_STATUS_Type; 1039 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1040 1041 #define SERCOM_SPI_STATUS_OFFSET 0x1A /**< \brief (SERCOM_SPI_STATUS offset) SPI Status */ 1042 #define SERCOM_SPI_STATUS_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_SPI_STATUS reset_value) SPI Status */ 1043 1044 #define SERCOM_SPI_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_SPI_STATUS) Buffer Overflow */ 1045 #define SERCOM_SPI_STATUS_BUFOVF (_U_(0x1) << SERCOM_SPI_STATUS_BUFOVF_Pos) 1046 #define SERCOM_SPI_STATUS_MASK _U_(0x0004) /**< \brief (SERCOM_SPI_STATUS) MASK Register */ 1047 1048 /* -------- SERCOM_USART_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART USART Status -------- */ 1049 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1050 typedef union { 1051 struct { 1052 uint16_t PERR:1; /*!< bit: 0 Parity Error */ 1053 uint16_t FERR:1; /*!< bit: 1 Frame Error */ 1054 uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */ 1055 uint16_t CTS:1; /*!< bit: 3 Clear To Send */ 1056 uint16_t ISF:1; /*!< bit: 4 Inconsistent Sync Field */ 1057 uint16_t COLL:1; /*!< bit: 5 Collision Detected */ 1058 uint16_t :10; /*!< bit: 6..15 Reserved */ 1059 } bit; /*!< Structure used for bit access */ 1060 uint16_t reg; /*!< Type used for register access */ 1061 } SERCOM_USART_STATUS_Type; 1062 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1063 1064 #define SERCOM_USART_STATUS_OFFSET 0x1A /**< \brief (SERCOM_USART_STATUS offset) USART Status */ 1065 #define SERCOM_USART_STATUS_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_USART_STATUS reset_value) USART Status */ 1066 1067 #define SERCOM_USART_STATUS_PERR_Pos 0 /**< \brief (SERCOM_USART_STATUS) Parity Error */ 1068 #define SERCOM_USART_STATUS_PERR (_U_(0x1) << SERCOM_USART_STATUS_PERR_Pos) 1069 #define SERCOM_USART_STATUS_FERR_Pos 1 /**< \brief (SERCOM_USART_STATUS) Frame Error */ 1070 #define SERCOM_USART_STATUS_FERR (_U_(0x1) << SERCOM_USART_STATUS_FERR_Pos) 1071 #define SERCOM_USART_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_USART_STATUS) Buffer Overflow */ 1072 #define SERCOM_USART_STATUS_BUFOVF (_U_(0x1) << SERCOM_USART_STATUS_BUFOVF_Pos) 1073 #define SERCOM_USART_STATUS_CTS_Pos 3 /**< \brief (SERCOM_USART_STATUS) Clear To Send */ 1074 #define SERCOM_USART_STATUS_CTS (_U_(0x1) << SERCOM_USART_STATUS_CTS_Pos) 1075 #define SERCOM_USART_STATUS_ISF_Pos 4 /**< \brief (SERCOM_USART_STATUS) Inconsistent Sync Field */ 1076 #define SERCOM_USART_STATUS_ISF (_U_(0x1) << SERCOM_USART_STATUS_ISF_Pos) 1077 #define SERCOM_USART_STATUS_COLL_Pos 5 /**< \brief (SERCOM_USART_STATUS) Collision Detected */ 1078 #define SERCOM_USART_STATUS_COLL (_U_(0x1) << SERCOM_USART_STATUS_COLL_Pos) 1079 #define SERCOM_USART_STATUS_MASK _U_(0x003F) /**< \brief (SERCOM_USART_STATUS) MASK Register */ 1080 1081 /* -------- SERCOM_I2CM_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CM I2CM Syncbusy -------- */ 1082 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1083 typedef union { 1084 struct { 1085 uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ 1086 uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ 1087 uint32_t SYSOP:1; /*!< bit: 2 System Operation Synchronization Busy */ 1088 uint32_t :29; /*!< bit: 3..31 Reserved */ 1089 } bit; /*!< Structure used for bit access */ 1090 uint32_t reg; /*!< Type used for register access */ 1091 } SERCOM_I2CM_SYNCBUSY_Type; 1092 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1093 1094 #define SERCOM_I2CM_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CM_SYNCBUSY offset) I2CM Syncbusy */ 1095 #define SERCOM_I2CM_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_SYNCBUSY reset_value) I2CM Syncbusy */ 1096 1097 #define SERCOM_I2CM_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_SYNCBUSY) Software Reset Synchronization Busy */ 1098 #define SERCOM_I2CM_SYNCBUSY_SWRST (_U_(0x1) << SERCOM_I2CM_SYNCBUSY_SWRST_Pos) 1099 #define SERCOM_I2CM_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_SYNCBUSY) SERCOM Enable Synchronization Busy */ 1100 #define SERCOM_I2CM_SYNCBUSY_ENABLE (_U_(0x1) << SERCOM_I2CM_SYNCBUSY_ENABLE_Pos) 1101 #define SERCOM_I2CM_SYNCBUSY_SYSOP_Pos 2 /**< \brief (SERCOM_I2CM_SYNCBUSY) System Operation Synchronization Busy */ 1102 #define SERCOM_I2CM_SYNCBUSY_SYSOP (_U_(0x1) << SERCOM_I2CM_SYNCBUSY_SYSOP_Pos) 1103 #define SERCOM_I2CM_SYNCBUSY_MASK _U_(0x00000007) /**< \brief (SERCOM_I2CM_SYNCBUSY) MASK Register */ 1104 1105 /* -------- SERCOM_I2CS_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CS I2CS Syncbusy -------- */ 1106 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1107 typedef union { 1108 struct { 1109 uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ 1110 uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ 1111 uint32_t :30; /*!< bit: 2..31 Reserved */ 1112 } bit; /*!< Structure used for bit access */ 1113 uint32_t reg; /*!< Type used for register access */ 1114 } SERCOM_I2CS_SYNCBUSY_Type; 1115 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1116 1117 #define SERCOM_I2CS_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CS_SYNCBUSY offset) I2CS Syncbusy */ 1118 #define SERCOM_I2CS_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_SYNCBUSY reset_value) I2CS Syncbusy */ 1119 1120 #define SERCOM_I2CS_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_SYNCBUSY) Software Reset Synchronization Busy */ 1121 #define SERCOM_I2CS_SYNCBUSY_SWRST (_U_(0x1) << SERCOM_I2CS_SYNCBUSY_SWRST_Pos) 1122 #define SERCOM_I2CS_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_SYNCBUSY) SERCOM Enable Synchronization Busy */ 1123 #define SERCOM_I2CS_SYNCBUSY_ENABLE (_U_(0x1) << SERCOM_I2CS_SYNCBUSY_ENABLE_Pos) 1124 #define SERCOM_I2CS_SYNCBUSY_MASK _U_(0x00000003) /**< \brief (SERCOM_I2CS_SYNCBUSY) MASK Register */ 1125 1126 /* -------- SERCOM_SPI_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) SPI SPI Syncbusy -------- */ 1127 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1128 typedef union { 1129 struct { 1130 uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ 1131 uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ 1132 uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */ 1133 uint32_t :29; /*!< bit: 3..31 Reserved */ 1134 } bit; /*!< Structure used for bit access */ 1135 uint32_t reg; /*!< Type used for register access */ 1136 } SERCOM_SPI_SYNCBUSY_Type; 1137 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1138 1139 #define SERCOM_SPI_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_SPI_SYNCBUSY offset) SPI Syncbusy */ 1140 #define SERCOM_SPI_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_SYNCBUSY reset_value) SPI Syncbusy */ 1141 1142 #define SERCOM_SPI_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_SPI_SYNCBUSY) Software Reset Synchronization Busy */ 1143 #define SERCOM_SPI_SYNCBUSY_SWRST (_U_(0x1) << SERCOM_SPI_SYNCBUSY_SWRST_Pos) 1144 #define SERCOM_SPI_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_SYNCBUSY) SERCOM Enable Synchronization Busy */ 1145 #define SERCOM_SPI_SYNCBUSY_ENABLE (_U_(0x1) << SERCOM_SPI_SYNCBUSY_ENABLE_Pos) 1146 #define SERCOM_SPI_SYNCBUSY_CTRLB_Pos 2 /**< \brief (SERCOM_SPI_SYNCBUSY) CTRLB Synchronization Busy */ 1147 #define SERCOM_SPI_SYNCBUSY_CTRLB (_U_(0x1) << SERCOM_SPI_SYNCBUSY_CTRLB_Pos) 1148 #define SERCOM_SPI_SYNCBUSY_MASK _U_(0x00000007) /**< \brief (SERCOM_SPI_SYNCBUSY) MASK Register */ 1149 1150 /* -------- SERCOM_USART_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) USART USART Syncbusy -------- */ 1151 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1152 typedef union { 1153 struct { 1154 uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ 1155 uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ 1156 uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */ 1157 uint32_t :29; /*!< bit: 3..31 Reserved */ 1158 } bit; /*!< Structure used for bit access */ 1159 uint32_t reg; /*!< Type used for register access */ 1160 } SERCOM_USART_SYNCBUSY_Type; 1161 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1162 1163 #define SERCOM_USART_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_USART_SYNCBUSY offset) USART Syncbusy */ 1164 #define SERCOM_USART_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_SYNCBUSY reset_value) USART Syncbusy */ 1165 1166 #define SERCOM_USART_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_USART_SYNCBUSY) Software Reset Synchronization Busy */ 1167 #define SERCOM_USART_SYNCBUSY_SWRST (_U_(0x1) << SERCOM_USART_SYNCBUSY_SWRST_Pos) 1168 #define SERCOM_USART_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_USART_SYNCBUSY) SERCOM Enable Synchronization Busy */ 1169 #define SERCOM_USART_SYNCBUSY_ENABLE (_U_(0x1) << SERCOM_USART_SYNCBUSY_ENABLE_Pos) 1170 #define SERCOM_USART_SYNCBUSY_CTRLB_Pos 2 /**< \brief (SERCOM_USART_SYNCBUSY) CTRLB Synchronization Busy */ 1171 #define SERCOM_USART_SYNCBUSY_CTRLB (_U_(0x1) << SERCOM_USART_SYNCBUSY_CTRLB_Pos) 1172 #define SERCOM_USART_SYNCBUSY_MASK _U_(0x00000007) /**< \brief (SERCOM_USART_SYNCBUSY) MASK Register */ 1173 1174 /* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CM I2CM Address -------- */ 1175 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1176 typedef union { 1177 struct { 1178 uint32_t ADDR:11; /*!< bit: 0..10 Address Value */ 1179 uint32_t :2; /*!< bit: 11..12 Reserved */ 1180 uint32_t LENEN:1; /*!< bit: 13 Length Enable */ 1181 uint32_t HS:1; /*!< bit: 14 High Speed Mode */ 1182 uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */ 1183 uint32_t LEN:8; /*!< bit: 16..23 Length */ 1184 uint32_t :8; /*!< bit: 24..31 Reserved */ 1185 } bit; /*!< Structure used for bit access */ 1186 uint32_t reg; /*!< Type used for register access */ 1187 } SERCOM_I2CM_ADDR_Type; 1188 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1189 1190 #define SERCOM_I2CM_ADDR_OFFSET 0x24 /**< \brief (SERCOM_I2CM_ADDR offset) I2CM Address */ 1191 #define SERCOM_I2CM_ADDR_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_ADDR reset_value) I2CM Address */ 1192 1193 #define SERCOM_I2CM_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_I2CM_ADDR) Address Value */ 1194 #define SERCOM_I2CM_ADDR_ADDR_Msk (_U_(0x7FF) << SERCOM_I2CM_ADDR_ADDR_Pos) 1195 #define SERCOM_I2CM_ADDR_ADDR(value) (SERCOM_I2CM_ADDR_ADDR_Msk & ((value) << SERCOM_I2CM_ADDR_ADDR_Pos)) 1196 #define SERCOM_I2CM_ADDR_LENEN_Pos 13 /**< \brief (SERCOM_I2CM_ADDR) Length Enable */ 1197 #define SERCOM_I2CM_ADDR_LENEN (_U_(0x1) << SERCOM_I2CM_ADDR_LENEN_Pos) 1198 #define SERCOM_I2CM_ADDR_HS_Pos 14 /**< \brief (SERCOM_I2CM_ADDR) High Speed Mode */ 1199 #define SERCOM_I2CM_ADDR_HS (_U_(0x1) << SERCOM_I2CM_ADDR_HS_Pos) 1200 #define SERCOM_I2CM_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CM_ADDR) Ten Bit Addressing Enable */ 1201 #define SERCOM_I2CM_ADDR_TENBITEN (_U_(0x1) << SERCOM_I2CM_ADDR_TENBITEN_Pos) 1202 #define SERCOM_I2CM_ADDR_LEN_Pos 16 /**< \brief (SERCOM_I2CM_ADDR) Length */ 1203 #define SERCOM_I2CM_ADDR_LEN_Msk (_U_(0xFF) << SERCOM_I2CM_ADDR_LEN_Pos) 1204 #define SERCOM_I2CM_ADDR_LEN(value) (SERCOM_I2CM_ADDR_LEN_Msk & ((value) << SERCOM_I2CM_ADDR_LEN_Pos)) 1205 #define SERCOM_I2CM_ADDR_MASK _U_(0x00FFE7FF) /**< \brief (SERCOM_I2CM_ADDR) MASK Register */ 1206 1207 /* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CS I2CS Address -------- */ 1208 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1209 typedef union { 1210 struct { 1211 uint32_t GENCEN:1; /*!< bit: 0 General Call Address Enable */ 1212 uint32_t ADDR:10; /*!< bit: 1..10 Address Value */ 1213 uint32_t :4; /*!< bit: 11..14 Reserved */ 1214 uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */ 1215 uint32_t :1; /*!< bit: 16 Reserved */ 1216 uint32_t ADDRMASK:10; /*!< bit: 17..26 Address Mask */ 1217 uint32_t :5; /*!< bit: 27..31 Reserved */ 1218 } bit; /*!< Structure used for bit access */ 1219 uint32_t reg; /*!< Type used for register access */ 1220 } SERCOM_I2CS_ADDR_Type; 1221 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1222 1223 #define SERCOM_I2CS_ADDR_OFFSET 0x24 /**< \brief (SERCOM_I2CS_ADDR offset) I2CS Address */ 1224 #define SERCOM_I2CS_ADDR_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_ADDR reset_value) I2CS Address */ 1225 1226 #define SERCOM_I2CS_ADDR_GENCEN_Pos 0 /**< \brief (SERCOM_I2CS_ADDR) General Call Address Enable */ 1227 #define SERCOM_I2CS_ADDR_GENCEN (_U_(0x1) << SERCOM_I2CS_ADDR_GENCEN_Pos) 1228 #define SERCOM_I2CS_ADDR_ADDR_Pos 1 /**< \brief (SERCOM_I2CS_ADDR) Address Value */ 1229 #define SERCOM_I2CS_ADDR_ADDR_Msk (_U_(0x3FF) << SERCOM_I2CS_ADDR_ADDR_Pos) 1230 #define SERCOM_I2CS_ADDR_ADDR(value) (SERCOM_I2CS_ADDR_ADDR_Msk & ((value) << SERCOM_I2CS_ADDR_ADDR_Pos)) 1231 #define SERCOM_I2CS_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CS_ADDR) Ten Bit Addressing Enable */ 1232 #define SERCOM_I2CS_ADDR_TENBITEN (_U_(0x1) << SERCOM_I2CS_ADDR_TENBITEN_Pos) 1233 #define SERCOM_I2CS_ADDR_ADDRMASK_Pos 17 /**< \brief (SERCOM_I2CS_ADDR) Address Mask */ 1234 #define SERCOM_I2CS_ADDR_ADDRMASK_Msk (_U_(0x3FF) << SERCOM_I2CS_ADDR_ADDRMASK_Pos) 1235 #define SERCOM_I2CS_ADDR_ADDRMASK(value) (SERCOM_I2CS_ADDR_ADDRMASK_Msk & ((value) << SERCOM_I2CS_ADDR_ADDRMASK_Pos)) 1236 #define SERCOM_I2CS_ADDR_MASK _U_(0x07FE87FF) /**< \brief (SERCOM_I2CS_ADDR) MASK Register */ 1237 1238 /* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPI SPI Address -------- */ 1239 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1240 typedef union { 1241 struct { 1242 uint32_t ADDR:8; /*!< bit: 0.. 7 Address Value */ 1243 uint32_t :8; /*!< bit: 8..15 Reserved */ 1244 uint32_t ADDRMASK:8; /*!< bit: 16..23 Address Mask */ 1245 uint32_t :8; /*!< bit: 24..31 Reserved */ 1246 } bit; /*!< Structure used for bit access */ 1247 uint32_t reg; /*!< Type used for register access */ 1248 } SERCOM_SPI_ADDR_Type; 1249 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1250 1251 #define SERCOM_SPI_ADDR_OFFSET 0x24 /**< \brief (SERCOM_SPI_ADDR offset) SPI Address */ 1252 #define SERCOM_SPI_ADDR_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_ADDR reset_value) SPI Address */ 1253 1254 #define SERCOM_SPI_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_SPI_ADDR) Address Value */ 1255 #define SERCOM_SPI_ADDR_ADDR_Msk (_U_(0xFF) << SERCOM_SPI_ADDR_ADDR_Pos) 1256 #define SERCOM_SPI_ADDR_ADDR(value) (SERCOM_SPI_ADDR_ADDR_Msk & ((value) << SERCOM_SPI_ADDR_ADDR_Pos)) 1257 #define SERCOM_SPI_ADDR_ADDRMASK_Pos 16 /**< \brief (SERCOM_SPI_ADDR) Address Mask */ 1258 #define SERCOM_SPI_ADDR_ADDRMASK_Msk (_U_(0xFF) << SERCOM_SPI_ADDR_ADDRMASK_Pos) 1259 #define SERCOM_SPI_ADDR_ADDRMASK(value) (SERCOM_SPI_ADDR_ADDRMASK_Msk & ((value) << SERCOM_SPI_ADDR_ADDRMASK_Pos)) 1260 #define SERCOM_SPI_ADDR_MASK _U_(0x00FF00FF) /**< \brief (SERCOM_SPI_ADDR) MASK Register */ 1261 1262 /* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CM I2CM Data -------- */ 1263 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1264 typedef union { 1265 struct { 1266 uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */ 1267 } bit; /*!< Structure used for bit access */ 1268 uint8_t reg; /*!< Type used for register access */ 1269 } SERCOM_I2CM_DATA_Type; 1270 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1271 1272 #define SERCOM_I2CM_DATA_OFFSET 0x28 /**< \brief (SERCOM_I2CM_DATA offset) I2CM Data */ 1273 #define SERCOM_I2CM_DATA_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CM_DATA reset_value) I2CM Data */ 1274 1275 #define SERCOM_I2CM_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CM_DATA) Data Value */ 1276 #define SERCOM_I2CM_DATA_DATA_Msk (_U_(0xFF) << SERCOM_I2CM_DATA_DATA_Pos) 1277 #define SERCOM_I2CM_DATA_DATA(value) (SERCOM_I2CM_DATA_DATA_Msk & ((value) << SERCOM_I2CM_DATA_DATA_Pos)) 1278 #define SERCOM_I2CM_DATA_MASK _U_(0xFF) /**< \brief (SERCOM_I2CM_DATA) MASK Register */ 1279 1280 /* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CS I2CS Data -------- */ 1281 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1282 typedef union { 1283 struct { 1284 uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */ 1285 } bit; /*!< Structure used for bit access */ 1286 uint8_t reg; /*!< Type used for register access */ 1287 } SERCOM_I2CS_DATA_Type; 1288 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1289 1290 #define SERCOM_I2CS_DATA_OFFSET 0x28 /**< \brief (SERCOM_I2CS_DATA offset) I2CS Data */ 1291 #define SERCOM_I2CS_DATA_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CS_DATA reset_value) I2CS Data */ 1292 1293 #define SERCOM_I2CS_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CS_DATA) Data Value */ 1294 #define SERCOM_I2CS_DATA_DATA_Msk (_U_(0xFF) << SERCOM_I2CS_DATA_DATA_Pos) 1295 #define SERCOM_I2CS_DATA_DATA(value) (SERCOM_I2CS_DATA_DATA_Msk & ((value) << SERCOM_I2CS_DATA_DATA_Pos)) 1296 #define SERCOM_I2CS_DATA_MASK _U_(0xFF) /**< \brief (SERCOM_I2CS_DATA) MASK Register */ 1297 1298 /* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x28) (R/W 32) SPI SPI Data -------- */ 1299 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1300 typedef union { 1301 struct { 1302 uint32_t DATA:9; /*!< bit: 0.. 8 Data Value */ 1303 uint32_t :23; /*!< bit: 9..31 Reserved */ 1304 } bit; /*!< Structure used for bit access */ 1305 uint32_t reg; /*!< Type used for register access */ 1306 } SERCOM_SPI_DATA_Type; 1307 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1308 1309 #define SERCOM_SPI_DATA_OFFSET 0x28 /**< \brief (SERCOM_SPI_DATA offset) SPI Data */ 1310 #define SERCOM_SPI_DATA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_DATA reset_value) SPI Data */ 1311 1312 #define SERCOM_SPI_DATA_DATA_Pos 0 /**< \brief (SERCOM_SPI_DATA) Data Value */ 1313 #define SERCOM_SPI_DATA_DATA_Msk (_U_(0x1FF) << SERCOM_SPI_DATA_DATA_Pos) 1314 #define SERCOM_SPI_DATA_DATA(value) (SERCOM_SPI_DATA_DATA_Msk & ((value) << SERCOM_SPI_DATA_DATA_Pos)) 1315 #define SERCOM_SPI_DATA_MASK _U_(0x000001FF) /**< \brief (SERCOM_SPI_DATA) MASK Register */ 1316 1317 /* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x28) (R/W 16) USART USART Data -------- */ 1318 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1319 typedef union { 1320 struct { 1321 uint16_t DATA:9; /*!< bit: 0.. 8 Data Value */ 1322 uint16_t :7; /*!< bit: 9..15 Reserved */ 1323 } bit; /*!< Structure used for bit access */ 1324 uint16_t reg; /*!< Type used for register access */ 1325 } SERCOM_USART_DATA_Type; 1326 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1327 1328 #define SERCOM_USART_DATA_OFFSET 0x28 /**< \brief (SERCOM_USART_DATA offset) USART Data */ 1329 #define SERCOM_USART_DATA_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_USART_DATA reset_value) USART Data */ 1330 1331 #define SERCOM_USART_DATA_DATA_Pos 0 /**< \brief (SERCOM_USART_DATA) Data Value */ 1332 #define SERCOM_USART_DATA_DATA_Msk (_U_(0x1FF) << SERCOM_USART_DATA_DATA_Pos) 1333 #define SERCOM_USART_DATA_DATA(value) (SERCOM_USART_DATA_DATA_Msk & ((value) << SERCOM_USART_DATA_DATA_Pos)) 1334 #define SERCOM_USART_DATA_MASK _U_(0x01FF) /**< \brief (SERCOM_USART_DATA) MASK Register */ 1335 1336 /* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) I2CM I2CM Debug Control -------- */ 1337 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1338 typedef union { 1339 struct { 1340 uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ 1341 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 1342 } bit; /*!< Structure used for bit access */ 1343 uint8_t reg; /*!< Type used for register access */ 1344 } SERCOM_I2CM_DBGCTRL_Type; 1345 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1346 1347 #define SERCOM_I2CM_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_I2CM_DBGCTRL offset) I2CM Debug Control */ 1348 #define SERCOM_I2CM_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CM_DBGCTRL reset_value) I2CM Debug Control */ 1349 1350 #define SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_I2CM_DBGCTRL) Debug Mode */ 1351 #define SERCOM_I2CM_DBGCTRL_DBGSTOP (_U_(0x1) << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos) 1352 #define SERCOM_I2CM_DBGCTRL_MASK _U_(0x01) /**< \brief (SERCOM_I2CM_DBGCTRL) MASK Register */ 1353 1354 /* -------- SERCOM_SPI_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) SPI SPI Debug Control -------- */ 1355 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1356 typedef union { 1357 struct { 1358 uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ 1359 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 1360 } bit; /*!< Structure used for bit access */ 1361 uint8_t reg; /*!< Type used for register access */ 1362 } SERCOM_SPI_DBGCTRL_Type; 1363 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1364 1365 #define SERCOM_SPI_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_SPI_DBGCTRL offset) SPI Debug Control */ 1366 #define SERCOM_SPI_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (SERCOM_SPI_DBGCTRL reset_value) SPI Debug Control */ 1367 1368 #define SERCOM_SPI_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_SPI_DBGCTRL) Debug Mode */ 1369 #define SERCOM_SPI_DBGCTRL_DBGSTOP (_U_(0x1) << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos) 1370 #define SERCOM_SPI_DBGCTRL_MASK _U_(0x01) /**< \brief (SERCOM_SPI_DBGCTRL) MASK Register */ 1371 1372 /* -------- SERCOM_USART_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) USART USART Debug Control -------- */ 1373 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1374 typedef union { 1375 struct { 1376 uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ 1377 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 1378 } bit; /*!< Structure used for bit access */ 1379 uint8_t reg; /*!< Type used for register access */ 1380 } SERCOM_USART_DBGCTRL_Type; 1381 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1382 1383 #define SERCOM_USART_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_USART_DBGCTRL offset) USART Debug Control */ 1384 #define SERCOM_USART_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (SERCOM_USART_DBGCTRL reset_value) USART Debug Control */ 1385 1386 #define SERCOM_USART_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_USART_DBGCTRL) Debug Mode */ 1387 #define SERCOM_USART_DBGCTRL_DBGSTOP (_U_(0x1) << SERCOM_USART_DBGCTRL_DBGSTOP_Pos) 1388 #define SERCOM_USART_DBGCTRL_MASK _U_(0x01) /**< \brief (SERCOM_USART_DBGCTRL) MASK Register */ 1389 1390 /** \brief SERCOM_I2CM hardware registers */ 1391 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1392 typedef struct { /* I2C Master Mode */ 1393 __IO SERCOM_I2CM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */ 1394 __IO SERCOM_I2CM_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */ 1395 RoReg8 Reserved1[0x4]; 1396 __IO SERCOM_I2CM_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */ 1397 RoReg8 Reserved2[0x4]; 1398 __IO SERCOM_I2CM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CM Interrupt Enable Clear */ 1399 RoReg8 Reserved3[0x1]; 1400 __IO SERCOM_I2CM_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CM Interrupt Enable Set */ 1401 RoReg8 Reserved4[0x1]; 1402 __IO SERCOM_I2CM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CM Interrupt Flag Status and Clear */ 1403 RoReg8 Reserved5[0x1]; 1404 __IO SERCOM_I2CM_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CM Status */ 1405 __I SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CM Syncbusy */ 1406 RoReg8 Reserved6[0x4]; 1407 __IO SERCOM_I2CM_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CM Address */ 1408 __IO SERCOM_I2CM_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CM Data */ 1409 RoReg8 Reserved7[0x7]; 1410 __IO SERCOM_I2CM_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) I2CM Debug Control */ 1411 } SercomI2cm; 1412 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1413 1414 /** \brief SERCOM_I2CS hardware registers */ 1415 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1416 typedef struct { /* I2C Slave Mode */ 1417 __IO SERCOM_I2CS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */ 1418 __IO SERCOM_I2CS_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */ 1419 RoReg8 Reserved1[0xC]; 1420 __IO SERCOM_I2CS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CS Interrupt Enable Clear */ 1421 RoReg8 Reserved2[0x1]; 1422 __IO SERCOM_I2CS_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CS Interrupt Enable Set */ 1423 RoReg8 Reserved3[0x1]; 1424 __IO SERCOM_I2CS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CS Interrupt Flag Status and Clear */ 1425 RoReg8 Reserved4[0x1]; 1426 __IO SERCOM_I2CS_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CS Status */ 1427 __I SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CS Syncbusy */ 1428 RoReg8 Reserved5[0x4]; 1429 __IO SERCOM_I2CS_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CS Address */ 1430 __IO SERCOM_I2CS_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CS Data */ 1431 } SercomI2cs; 1432 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1433 1434 /** \brief SERCOM_SPI hardware registers */ 1435 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1436 typedef struct { /* SPI Mode */ 1437 __IO SERCOM_SPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) SPI Control A */ 1438 __IO SERCOM_SPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) SPI Control B */ 1439 RoReg8 Reserved1[0x4]; 1440 __IO SERCOM_SPI_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 8) SPI Baud Rate */ 1441 RoReg8 Reserved2[0x7]; 1442 __IO SERCOM_SPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) SPI Interrupt Enable Clear */ 1443 RoReg8 Reserved3[0x1]; 1444 __IO SERCOM_SPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) SPI Interrupt Enable Set */ 1445 RoReg8 Reserved4[0x1]; 1446 __IO SERCOM_SPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) SPI Interrupt Flag Status and Clear */ 1447 RoReg8 Reserved5[0x1]; 1448 __IO SERCOM_SPI_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) SPI Status */ 1449 __I SERCOM_SPI_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) SPI Syncbusy */ 1450 RoReg8 Reserved6[0x4]; 1451 __IO SERCOM_SPI_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) SPI Address */ 1452 __IO SERCOM_SPI_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) SPI Data */ 1453 RoReg8 Reserved7[0x4]; 1454 __IO SERCOM_SPI_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) SPI Debug Control */ 1455 } SercomSpi; 1456 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1457 1458 /** \brief SERCOM_USART hardware registers */ 1459 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1460 typedef struct { /* USART Mode */ 1461 __IO SERCOM_USART_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) USART Control A */ 1462 __IO SERCOM_USART_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) USART Control B */ 1463 RoReg8 Reserved1[0x4]; 1464 __IO SERCOM_USART_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */ 1465 __IO SERCOM_USART_RXPL_Type RXPL; /**< \brief Offset: 0x0E (R/W 8) USART Receive Pulse Length */ 1466 RoReg8 Reserved2[0x5]; 1467 __IO SERCOM_USART_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) USART Interrupt Enable Clear */ 1468 RoReg8 Reserved3[0x1]; 1469 __IO SERCOM_USART_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) USART Interrupt Enable Set */ 1470 RoReg8 Reserved4[0x1]; 1471 __IO SERCOM_USART_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) USART Interrupt Flag Status and Clear */ 1472 RoReg8 Reserved5[0x1]; 1473 __IO SERCOM_USART_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) USART Status */ 1474 __I SERCOM_USART_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) USART Syncbusy */ 1475 RoReg8 Reserved6[0x8]; 1476 __IO SERCOM_USART_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 16) USART Data */ 1477 RoReg8 Reserved7[0x6]; 1478 __IO SERCOM_USART_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) USART Debug Control */ 1479 } SercomUsart; 1480 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1481 1482 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1483 typedef union { 1484 SercomI2cm I2CM; /**< \brief Offset: 0x00 I2C Master Mode */ 1485 SercomI2cs I2CS; /**< \brief Offset: 0x00 I2C Slave Mode */ 1486 SercomSpi SPI; /**< \brief Offset: 0x00 SPI Mode */ 1487 SercomUsart USART; /**< \brief Offset: 0x00 USART Mode */ 1488 } Sercom; 1489 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1490 1491 /*@}*/ 1492 1493 #endif /* _SAMR21_SERCOM_COMPONENT_ */ 1494
