1 /** 2 * \file 3 * 4 * \brief Component description for RFCTRL 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAMR21_RFCTRL_COMPONENT_ 30 #define _SAMR21_RFCTRL_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR RFCTRL */ 34 /* ========================================================================== */ 35 /** \addtogroup SAMR21_RFCTRL RF233 control module */ 36 /*@{*/ 37 38 #define RFCTRL_U2233 39 #define REV_RFCTRL 0x100 40 41 /* -------- RFCTRL_FECFG : (RFCTRL Offset: 0x0) (R/W 16) Front-end control bus configuration -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint16_t F0CFG:2; /*!< bit: 0.. 1 Front-end control signal 0 configuration */ 46 uint16_t F1CFG:2; /*!< bit: 2.. 3 Front-end control signal 1 configuration */ 47 uint16_t F2CFG:2; /*!< bit: 4.. 5 Front-end control signal 2 configuration */ 48 uint16_t F3CFG:2; /*!< bit: 6.. 7 Front-end control signal 3 configuration */ 49 uint16_t F4CFG:2; /*!< bit: 8.. 9 Front-end control signal 4 configuration */ 50 uint16_t F5CFG:2; /*!< bit: 10..11 Front-end control signal 5 configuration */ 51 uint16_t :4; /*!< bit: 12..15 Reserved */ 52 } bit; /*!< Structure used for bit access */ 53 uint16_t reg; /*!< Type used for register access */ 54 } RFCTRL_FECFG_Type; 55 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 56 57 #define RFCTRL_FECFG_OFFSET 0x0 /**< \brief (RFCTRL_FECFG offset) Front-end control bus configuration */ 58 #define RFCTRL_FECFG_RESETVALUE _U_(0x0000) /**< \brief (RFCTRL_FECFG reset_value) Front-end control bus configuration */ 59 60 #define RFCTRL_FECFG_F0CFG_Pos 0 /**< \brief (RFCTRL_FECFG) Front-end control signal 0 configuration */ 61 #define RFCTRL_FECFG_F0CFG_Msk (_U_(0x3) << RFCTRL_FECFG_F0CFG_Pos) 62 #define RFCTRL_FECFG_F0CFG(value) (RFCTRL_FECFG_F0CFG_Msk & ((value) << RFCTRL_FECFG_F0CFG_Pos)) 63 #define RFCTRL_FECFG_F1CFG_Pos 2 /**< \brief (RFCTRL_FECFG) Front-end control signal 1 configuration */ 64 #define RFCTRL_FECFG_F1CFG_Msk (_U_(0x3) << RFCTRL_FECFG_F1CFG_Pos) 65 #define RFCTRL_FECFG_F1CFG(value) (RFCTRL_FECFG_F1CFG_Msk & ((value) << RFCTRL_FECFG_F1CFG_Pos)) 66 #define RFCTRL_FECFG_F2CFG_Pos 4 /**< \brief (RFCTRL_FECFG) Front-end control signal 2 configuration */ 67 #define RFCTRL_FECFG_F2CFG_Msk (_U_(0x3) << RFCTRL_FECFG_F2CFG_Pos) 68 #define RFCTRL_FECFG_F2CFG(value) (RFCTRL_FECFG_F2CFG_Msk & ((value) << RFCTRL_FECFG_F2CFG_Pos)) 69 #define RFCTRL_FECFG_F3CFG_Pos 6 /**< \brief (RFCTRL_FECFG) Front-end control signal 3 configuration */ 70 #define RFCTRL_FECFG_F3CFG_Msk (_U_(0x3) << RFCTRL_FECFG_F3CFG_Pos) 71 #define RFCTRL_FECFG_F3CFG(value) (RFCTRL_FECFG_F3CFG_Msk & ((value) << RFCTRL_FECFG_F3CFG_Pos)) 72 #define RFCTRL_FECFG_F4CFG_Pos 8 /**< \brief (RFCTRL_FECFG) Front-end control signal 4 configuration */ 73 #define RFCTRL_FECFG_F4CFG_Msk (_U_(0x3) << RFCTRL_FECFG_F4CFG_Pos) 74 #define RFCTRL_FECFG_F4CFG(value) (RFCTRL_FECFG_F4CFG_Msk & ((value) << RFCTRL_FECFG_F4CFG_Pos)) 75 #define RFCTRL_FECFG_F5CFG_Pos 10 /**< \brief (RFCTRL_FECFG) Front-end control signal 5 configuration */ 76 #define RFCTRL_FECFG_F5CFG_Msk (_U_(0x3) << RFCTRL_FECFG_F5CFG_Pos) 77 #define RFCTRL_FECFG_F5CFG(value) (RFCTRL_FECFG_F5CFG_Msk & ((value) << RFCTRL_FECFG_F5CFG_Pos)) 78 #define RFCTRL_FECFG_MASK _U_(0x0FFF) /**< \brief (RFCTRL_FECFG) MASK Register */ 79 80 /** \brief RFCTRL hardware registers */ 81 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 82 typedef struct { 83 __IO RFCTRL_FECFG_Type FECFG; /**< \brief Offset: 0x0 (R/W 16) Front-end control bus configuration */ 84 } Rfctrl; 85 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 86 87 /*@}*/ 88 89 #endif /* _SAMR21_RFCTRL_COMPONENT_ */ 90
