1 /** 2 * \file 3 * 4 * \brief Component description for EIC 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAMR21_EIC_COMPONENT_ 30 #define _SAMR21_EIC_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR EIC */ 34 /* ========================================================================== */ 35 /** \addtogroup SAMR21_EIC External Interrupt Controller */ 36 /*@{*/ 37 38 #define EIC_U2217 39 #define REV_EIC 0x101 40 41 /* -------- EIC_CTRL : (EIC Offset: 0x00) (R/W 8) Control -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint8_t SWRST:1; /*!< bit: 0 Software Reset */ 46 uint8_t ENABLE:1; /*!< bit: 1 Enable */ 47 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 48 } bit; /*!< Structure used for bit access */ 49 uint8_t reg; /*!< Type used for register access */ 50 } EIC_CTRL_Type; 51 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 52 53 #define EIC_CTRL_OFFSET 0x00 /**< \brief (EIC_CTRL offset) Control */ 54 #define EIC_CTRL_RESETVALUE _U_(0x00) /**< \brief (EIC_CTRL reset_value) Control */ 55 56 #define EIC_CTRL_SWRST_Pos 0 /**< \brief (EIC_CTRL) Software Reset */ 57 #define EIC_CTRL_SWRST (_U_(0x1) << EIC_CTRL_SWRST_Pos) 58 #define EIC_CTRL_ENABLE_Pos 1 /**< \brief (EIC_CTRL) Enable */ 59 #define EIC_CTRL_ENABLE (_U_(0x1) << EIC_CTRL_ENABLE_Pos) 60 #define EIC_CTRL_MASK _U_(0x03) /**< \brief (EIC_CTRL) MASK Register */ 61 62 /* -------- EIC_STATUS : (EIC Offset: 0x01) (R/ 8) Status -------- */ 63 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 64 typedef union { 65 struct { 66 uint8_t :7; /*!< bit: 0.. 6 Reserved */ 67 uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ 68 } bit; /*!< Structure used for bit access */ 69 uint8_t reg; /*!< Type used for register access */ 70 } EIC_STATUS_Type; 71 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 72 73 #define EIC_STATUS_OFFSET 0x01 /**< \brief (EIC_STATUS offset) Status */ 74 #define EIC_STATUS_RESETVALUE _U_(0x00) /**< \brief (EIC_STATUS reset_value) Status */ 75 76 #define EIC_STATUS_SYNCBUSY_Pos 7 /**< \brief (EIC_STATUS) Synchronization Busy */ 77 #define EIC_STATUS_SYNCBUSY (_U_(0x1) << EIC_STATUS_SYNCBUSY_Pos) 78 #define EIC_STATUS_MASK _U_(0x80) /**< \brief (EIC_STATUS) MASK Register */ 79 80 /* -------- EIC_NMICTRL : (EIC Offset: 0x02) (R/W 8) Non-Maskable Interrupt Control -------- */ 81 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 82 typedef union { 83 struct { 84 uint8_t NMISENSE:3; /*!< bit: 0.. 2 Non-Maskable Interrupt Sense */ 85 uint8_t NMIFILTEN:1; /*!< bit: 3 Non-Maskable Interrupt Filter Enable */ 86 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 87 } bit; /*!< Structure used for bit access */ 88 uint8_t reg; /*!< Type used for register access */ 89 } EIC_NMICTRL_Type; 90 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 91 92 #define EIC_NMICTRL_OFFSET 0x02 /**< \brief (EIC_NMICTRL offset) Non-Maskable Interrupt Control */ 93 #define EIC_NMICTRL_RESETVALUE _U_(0x00) /**< \brief (EIC_NMICTRL reset_value) Non-Maskable Interrupt Control */ 94 95 #define EIC_NMICTRL_NMISENSE_Pos 0 /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Sense */ 96 #define EIC_NMICTRL_NMISENSE_Msk (_U_(0x7) << EIC_NMICTRL_NMISENSE_Pos) 97 #define EIC_NMICTRL_NMISENSE(value) (EIC_NMICTRL_NMISENSE_Msk & ((value) << EIC_NMICTRL_NMISENSE_Pos)) 98 #define EIC_NMICTRL_NMISENSE_NONE_Val _U_(0x0) /**< \brief (EIC_NMICTRL) No detection */ 99 #define EIC_NMICTRL_NMISENSE_RISE_Val _U_(0x1) /**< \brief (EIC_NMICTRL) Rising-edge detection */ 100 #define EIC_NMICTRL_NMISENSE_FALL_Val _U_(0x2) /**< \brief (EIC_NMICTRL) Falling-edge detection */ 101 #define EIC_NMICTRL_NMISENSE_BOTH_Val _U_(0x3) /**< \brief (EIC_NMICTRL) Both-edges detection */ 102 #define EIC_NMICTRL_NMISENSE_HIGH_Val _U_(0x4) /**< \brief (EIC_NMICTRL) High-level detection */ 103 #define EIC_NMICTRL_NMISENSE_LOW_Val _U_(0x5) /**< \brief (EIC_NMICTRL) Low-level detection */ 104 #define EIC_NMICTRL_NMISENSE_NONE (EIC_NMICTRL_NMISENSE_NONE_Val << EIC_NMICTRL_NMISENSE_Pos) 105 #define EIC_NMICTRL_NMISENSE_RISE (EIC_NMICTRL_NMISENSE_RISE_Val << EIC_NMICTRL_NMISENSE_Pos) 106 #define EIC_NMICTRL_NMISENSE_FALL (EIC_NMICTRL_NMISENSE_FALL_Val << EIC_NMICTRL_NMISENSE_Pos) 107 #define EIC_NMICTRL_NMISENSE_BOTH (EIC_NMICTRL_NMISENSE_BOTH_Val << EIC_NMICTRL_NMISENSE_Pos) 108 #define EIC_NMICTRL_NMISENSE_HIGH (EIC_NMICTRL_NMISENSE_HIGH_Val << EIC_NMICTRL_NMISENSE_Pos) 109 #define EIC_NMICTRL_NMISENSE_LOW (EIC_NMICTRL_NMISENSE_LOW_Val << EIC_NMICTRL_NMISENSE_Pos) 110 #define EIC_NMICTRL_NMIFILTEN_Pos 3 /**< \brief (EIC_NMICTRL) Non-Maskable Interrupt Filter Enable */ 111 #define EIC_NMICTRL_NMIFILTEN (_U_(0x1) << EIC_NMICTRL_NMIFILTEN_Pos) 112 #define EIC_NMICTRL_MASK _U_(0x0F) /**< \brief (EIC_NMICTRL) MASK Register */ 113 114 /* -------- EIC_NMIFLAG : (EIC Offset: 0x03) (R/W 8) Non-Maskable Interrupt Flag Status and Clear -------- */ 115 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 116 typedef union { 117 struct { 118 uint8_t NMI:1; /*!< bit: 0 Non-Maskable Interrupt */ 119 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 120 } bit; /*!< Structure used for bit access */ 121 uint8_t reg; /*!< Type used for register access */ 122 } EIC_NMIFLAG_Type; 123 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 124 125 #define EIC_NMIFLAG_OFFSET 0x03 /**< \brief (EIC_NMIFLAG offset) Non-Maskable Interrupt Flag Status and Clear */ 126 #define EIC_NMIFLAG_RESETVALUE _U_(0x00) /**< \brief (EIC_NMIFLAG reset_value) Non-Maskable Interrupt Flag Status and Clear */ 127 128 #define EIC_NMIFLAG_NMI_Pos 0 /**< \brief (EIC_NMIFLAG) Non-Maskable Interrupt */ 129 #define EIC_NMIFLAG_NMI (_U_(0x1) << EIC_NMIFLAG_NMI_Pos) 130 #define EIC_NMIFLAG_MASK _U_(0x01) /**< \brief (EIC_NMIFLAG) MASK Register */ 131 132 /* -------- EIC_EVCTRL : (EIC Offset: 0x04) (R/W 32) Event Control -------- */ 133 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 134 typedef union { 135 struct { 136 uint32_t EXTINTEO0:1; /*!< bit: 0 External Interrupt 0 Event Output Enable */ 137 uint32_t EXTINTEO1:1; /*!< bit: 1 External Interrupt 1 Event Output Enable */ 138 uint32_t EXTINTEO2:1; /*!< bit: 2 External Interrupt 2 Event Output Enable */ 139 uint32_t EXTINTEO3:1; /*!< bit: 3 External Interrupt 3 Event Output Enable */ 140 uint32_t EXTINTEO4:1; /*!< bit: 4 External Interrupt 4 Event Output Enable */ 141 uint32_t EXTINTEO5:1; /*!< bit: 5 External Interrupt 5 Event Output Enable */ 142 uint32_t EXTINTEO6:1; /*!< bit: 6 External Interrupt 6 Event Output Enable */ 143 uint32_t EXTINTEO7:1; /*!< bit: 7 External Interrupt 7 Event Output Enable */ 144 uint32_t EXTINTEO8:1; /*!< bit: 8 External Interrupt 8 Event Output Enable */ 145 uint32_t EXTINTEO9:1; /*!< bit: 9 External Interrupt 9 Event Output Enable */ 146 uint32_t EXTINTEO10:1; /*!< bit: 10 External Interrupt 10 Event Output Enable */ 147 uint32_t EXTINTEO11:1; /*!< bit: 11 External Interrupt 11 Event Output Enable */ 148 uint32_t EXTINTEO12:1; /*!< bit: 12 External Interrupt 12 Event Output Enable */ 149 uint32_t EXTINTEO13:1; /*!< bit: 13 External Interrupt 13 Event Output Enable */ 150 uint32_t EXTINTEO14:1; /*!< bit: 14 External Interrupt 14 Event Output Enable */ 151 uint32_t EXTINTEO15:1; /*!< bit: 15 External Interrupt 15 Event Output Enable */ 152 uint32_t :16; /*!< bit: 16..31 Reserved */ 153 } bit; /*!< Structure used for bit access */ 154 struct { 155 uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt x Event Output Enable */ 156 uint32_t :16; /*!< bit: 16..31 Reserved */ 157 } vec; /*!< Structure used for vec access */ 158 uint32_t reg; /*!< Type used for register access */ 159 } EIC_EVCTRL_Type; 160 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 161 162 #define EIC_EVCTRL_OFFSET 0x04 /**< \brief (EIC_EVCTRL offset) Event Control */ 163 #define EIC_EVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (EIC_EVCTRL reset_value) Event Control */ 164 165 #define EIC_EVCTRL_EXTINTEO0_Pos 0 /**< \brief (EIC_EVCTRL) External Interrupt 0 Event Output Enable */ 166 #define EIC_EVCTRL_EXTINTEO0 (1 << EIC_EVCTRL_EXTINTEO0_Pos) 167 #define EIC_EVCTRL_EXTINTEO1_Pos 1 /**< \brief (EIC_EVCTRL) External Interrupt 1 Event Output Enable */ 168 #define EIC_EVCTRL_EXTINTEO1 (1 << EIC_EVCTRL_EXTINTEO1_Pos) 169 #define EIC_EVCTRL_EXTINTEO2_Pos 2 /**< \brief (EIC_EVCTRL) External Interrupt 2 Event Output Enable */ 170 #define EIC_EVCTRL_EXTINTEO2 (1 << EIC_EVCTRL_EXTINTEO2_Pos) 171 #define EIC_EVCTRL_EXTINTEO3_Pos 3 /**< \brief (EIC_EVCTRL) External Interrupt 3 Event Output Enable */ 172 #define EIC_EVCTRL_EXTINTEO3 (1 << EIC_EVCTRL_EXTINTEO3_Pos) 173 #define EIC_EVCTRL_EXTINTEO4_Pos 4 /**< \brief (EIC_EVCTRL) External Interrupt 4 Event Output Enable */ 174 #define EIC_EVCTRL_EXTINTEO4 (1 << EIC_EVCTRL_EXTINTEO4_Pos) 175 #define EIC_EVCTRL_EXTINTEO5_Pos 5 /**< \brief (EIC_EVCTRL) External Interrupt 5 Event Output Enable */ 176 #define EIC_EVCTRL_EXTINTEO5 (1 << EIC_EVCTRL_EXTINTEO5_Pos) 177 #define EIC_EVCTRL_EXTINTEO6_Pos 6 /**< \brief (EIC_EVCTRL) External Interrupt 6 Event Output Enable */ 178 #define EIC_EVCTRL_EXTINTEO6 (1 << EIC_EVCTRL_EXTINTEO6_Pos) 179 #define EIC_EVCTRL_EXTINTEO7_Pos 7 /**< \brief (EIC_EVCTRL) External Interrupt 7 Event Output Enable */ 180 #define EIC_EVCTRL_EXTINTEO7 (1 << EIC_EVCTRL_EXTINTEO7_Pos) 181 #define EIC_EVCTRL_EXTINTEO8_Pos 8 /**< \brief (EIC_EVCTRL) External Interrupt 8 Event Output Enable */ 182 #define EIC_EVCTRL_EXTINTEO8 (1 << EIC_EVCTRL_EXTINTEO8_Pos) 183 #define EIC_EVCTRL_EXTINTEO9_Pos 9 /**< \brief (EIC_EVCTRL) External Interrupt 9 Event Output Enable */ 184 #define EIC_EVCTRL_EXTINTEO9 (1 << EIC_EVCTRL_EXTINTEO9_Pos) 185 #define EIC_EVCTRL_EXTINTEO10_Pos 10 /**< \brief (EIC_EVCTRL) External Interrupt 10 Event Output Enable */ 186 #define EIC_EVCTRL_EXTINTEO10 (1 << EIC_EVCTRL_EXTINTEO10_Pos) 187 #define EIC_EVCTRL_EXTINTEO11_Pos 11 /**< \brief (EIC_EVCTRL) External Interrupt 11 Event Output Enable */ 188 #define EIC_EVCTRL_EXTINTEO11 (1 << EIC_EVCTRL_EXTINTEO11_Pos) 189 #define EIC_EVCTRL_EXTINTEO12_Pos 12 /**< \brief (EIC_EVCTRL) External Interrupt 12 Event Output Enable */ 190 #define EIC_EVCTRL_EXTINTEO12 (1 << EIC_EVCTRL_EXTINTEO12_Pos) 191 #define EIC_EVCTRL_EXTINTEO13_Pos 13 /**< \brief (EIC_EVCTRL) External Interrupt 13 Event Output Enable */ 192 #define EIC_EVCTRL_EXTINTEO13 (1 << EIC_EVCTRL_EXTINTEO13_Pos) 193 #define EIC_EVCTRL_EXTINTEO14_Pos 14 /**< \brief (EIC_EVCTRL) External Interrupt 14 Event Output Enable */ 194 #define EIC_EVCTRL_EXTINTEO14 (1 << EIC_EVCTRL_EXTINTEO14_Pos) 195 #define EIC_EVCTRL_EXTINTEO15_Pos 15 /**< \brief (EIC_EVCTRL) External Interrupt 15 Event Output Enable */ 196 #define EIC_EVCTRL_EXTINTEO15 (1 << EIC_EVCTRL_EXTINTEO15_Pos) 197 #define EIC_EVCTRL_EXTINTEO_Pos 0 /**< \brief (EIC_EVCTRL) External Interrupt x Event Output Enable */ 198 #define EIC_EVCTRL_EXTINTEO_Msk (_U_(0xFFFF) << EIC_EVCTRL_EXTINTEO_Pos) 199 #define EIC_EVCTRL_EXTINTEO(value) (EIC_EVCTRL_EXTINTEO_Msk & ((value) << EIC_EVCTRL_EXTINTEO_Pos)) 200 #define EIC_EVCTRL_MASK _U_(0x0000FFFF) /**< \brief (EIC_EVCTRL) MASK Register */ 201 202 /* -------- EIC_INTENCLR : (EIC Offset: 0x08) (R/W 32) Interrupt Enable Clear -------- */ 203 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 204 typedef union { 205 struct { 206 uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */ 207 uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */ 208 uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */ 209 uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */ 210 uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */ 211 uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */ 212 uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */ 213 uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */ 214 uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */ 215 uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */ 216 uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */ 217 uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */ 218 uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */ 219 uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */ 220 uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */ 221 uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */ 222 uint32_t :16; /*!< bit: 16..31 Reserved */ 223 } bit; /*!< Structure used for bit access */ 224 struct { 225 uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */ 226 uint32_t :16; /*!< bit: 16..31 Reserved */ 227 } vec; /*!< Structure used for vec access */ 228 uint32_t reg; /*!< Type used for register access */ 229 } EIC_INTENCLR_Type; 230 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 231 232 #define EIC_INTENCLR_OFFSET 0x08 /**< \brief (EIC_INTENCLR offset) Interrupt Enable Clear */ 233 #define EIC_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (EIC_INTENCLR reset_value) Interrupt Enable Clear */ 234 235 #define EIC_INTENCLR_EXTINT0_Pos 0 /**< \brief (EIC_INTENCLR) External Interrupt 0 Enable */ 236 #define EIC_INTENCLR_EXTINT0 (1 << EIC_INTENCLR_EXTINT0_Pos) 237 #define EIC_INTENCLR_EXTINT1_Pos 1 /**< \brief (EIC_INTENCLR) External Interrupt 1 Enable */ 238 #define EIC_INTENCLR_EXTINT1 (1 << EIC_INTENCLR_EXTINT1_Pos) 239 #define EIC_INTENCLR_EXTINT2_Pos 2 /**< \brief (EIC_INTENCLR) External Interrupt 2 Enable */ 240 #define EIC_INTENCLR_EXTINT2 (1 << EIC_INTENCLR_EXTINT2_Pos) 241 #define EIC_INTENCLR_EXTINT3_Pos 3 /**< \brief (EIC_INTENCLR) External Interrupt 3 Enable */ 242 #define EIC_INTENCLR_EXTINT3 (1 << EIC_INTENCLR_EXTINT3_Pos) 243 #define EIC_INTENCLR_EXTINT4_Pos 4 /**< \brief (EIC_INTENCLR) External Interrupt 4 Enable */ 244 #define EIC_INTENCLR_EXTINT4 (1 << EIC_INTENCLR_EXTINT4_Pos) 245 #define EIC_INTENCLR_EXTINT5_Pos 5 /**< \brief (EIC_INTENCLR) External Interrupt 5 Enable */ 246 #define EIC_INTENCLR_EXTINT5 (1 << EIC_INTENCLR_EXTINT5_Pos) 247 #define EIC_INTENCLR_EXTINT6_Pos 6 /**< \brief (EIC_INTENCLR) External Interrupt 6 Enable */ 248 #define EIC_INTENCLR_EXTINT6 (1 << EIC_INTENCLR_EXTINT6_Pos) 249 #define EIC_INTENCLR_EXTINT7_Pos 7 /**< \brief (EIC_INTENCLR) External Interrupt 7 Enable */ 250 #define EIC_INTENCLR_EXTINT7 (1 << EIC_INTENCLR_EXTINT7_Pos) 251 #define EIC_INTENCLR_EXTINT8_Pos 8 /**< \brief (EIC_INTENCLR) External Interrupt 8 Enable */ 252 #define EIC_INTENCLR_EXTINT8 (1 << EIC_INTENCLR_EXTINT8_Pos) 253 #define EIC_INTENCLR_EXTINT9_Pos 9 /**< \brief (EIC_INTENCLR) External Interrupt 9 Enable */ 254 #define EIC_INTENCLR_EXTINT9 (1 << EIC_INTENCLR_EXTINT9_Pos) 255 #define EIC_INTENCLR_EXTINT10_Pos 10 /**< \brief (EIC_INTENCLR) External Interrupt 10 Enable */ 256 #define EIC_INTENCLR_EXTINT10 (1 << EIC_INTENCLR_EXTINT10_Pos) 257 #define EIC_INTENCLR_EXTINT11_Pos 11 /**< \brief (EIC_INTENCLR) External Interrupt 11 Enable */ 258 #define EIC_INTENCLR_EXTINT11 (1 << EIC_INTENCLR_EXTINT11_Pos) 259 #define EIC_INTENCLR_EXTINT12_Pos 12 /**< \brief (EIC_INTENCLR) External Interrupt 12 Enable */ 260 #define EIC_INTENCLR_EXTINT12 (1 << EIC_INTENCLR_EXTINT12_Pos) 261 #define EIC_INTENCLR_EXTINT13_Pos 13 /**< \brief (EIC_INTENCLR) External Interrupt 13 Enable */ 262 #define EIC_INTENCLR_EXTINT13 (1 << EIC_INTENCLR_EXTINT13_Pos) 263 #define EIC_INTENCLR_EXTINT14_Pos 14 /**< \brief (EIC_INTENCLR) External Interrupt 14 Enable */ 264 #define EIC_INTENCLR_EXTINT14 (1 << EIC_INTENCLR_EXTINT14_Pos) 265 #define EIC_INTENCLR_EXTINT15_Pos 15 /**< \brief (EIC_INTENCLR) External Interrupt 15 Enable */ 266 #define EIC_INTENCLR_EXTINT15 (1 << EIC_INTENCLR_EXTINT15_Pos) 267 #define EIC_INTENCLR_EXTINT_Pos 0 /**< \brief (EIC_INTENCLR) External Interrupt x Enable */ 268 #define EIC_INTENCLR_EXTINT_Msk (_U_(0xFFFF) << EIC_INTENCLR_EXTINT_Pos) 269 #define EIC_INTENCLR_EXTINT(value) (EIC_INTENCLR_EXTINT_Msk & ((value) << EIC_INTENCLR_EXTINT_Pos)) 270 #define EIC_INTENCLR_MASK _U_(0x0000FFFF) /**< \brief (EIC_INTENCLR) MASK Register */ 271 272 /* -------- EIC_INTENSET : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Set -------- */ 273 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 274 typedef union { 275 struct { 276 uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */ 277 uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */ 278 uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */ 279 uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */ 280 uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */ 281 uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */ 282 uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */ 283 uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */ 284 uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */ 285 uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */ 286 uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */ 287 uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */ 288 uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */ 289 uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */ 290 uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */ 291 uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */ 292 uint32_t :16; /*!< bit: 16..31 Reserved */ 293 } bit; /*!< Structure used for bit access */ 294 struct { 295 uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */ 296 uint32_t :16; /*!< bit: 16..31 Reserved */ 297 } vec; /*!< Structure used for vec access */ 298 uint32_t reg; /*!< Type used for register access */ 299 } EIC_INTENSET_Type; 300 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 301 302 #define EIC_INTENSET_OFFSET 0x0C /**< \brief (EIC_INTENSET offset) Interrupt Enable Set */ 303 #define EIC_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (EIC_INTENSET reset_value) Interrupt Enable Set */ 304 305 #define EIC_INTENSET_EXTINT0_Pos 0 /**< \brief (EIC_INTENSET) External Interrupt 0 Enable */ 306 #define EIC_INTENSET_EXTINT0 (1 << EIC_INTENSET_EXTINT0_Pos) 307 #define EIC_INTENSET_EXTINT1_Pos 1 /**< \brief (EIC_INTENSET) External Interrupt 1 Enable */ 308 #define EIC_INTENSET_EXTINT1 (1 << EIC_INTENSET_EXTINT1_Pos) 309 #define EIC_INTENSET_EXTINT2_Pos 2 /**< \brief (EIC_INTENSET) External Interrupt 2 Enable */ 310 #define EIC_INTENSET_EXTINT2 (1 << EIC_INTENSET_EXTINT2_Pos) 311 #define EIC_INTENSET_EXTINT3_Pos 3 /**< \brief (EIC_INTENSET) External Interrupt 3 Enable */ 312 #define EIC_INTENSET_EXTINT3 (1 << EIC_INTENSET_EXTINT3_Pos) 313 #define EIC_INTENSET_EXTINT4_Pos 4 /**< \brief (EIC_INTENSET) External Interrupt 4 Enable */ 314 #define EIC_INTENSET_EXTINT4 (1 << EIC_INTENSET_EXTINT4_Pos) 315 #define EIC_INTENSET_EXTINT5_Pos 5 /**< \brief (EIC_INTENSET) External Interrupt 5 Enable */ 316 #define EIC_INTENSET_EXTINT5 (1 << EIC_INTENSET_EXTINT5_Pos) 317 #define EIC_INTENSET_EXTINT6_Pos 6 /**< \brief (EIC_INTENSET) External Interrupt 6 Enable */ 318 #define EIC_INTENSET_EXTINT6 (1 << EIC_INTENSET_EXTINT6_Pos) 319 #define EIC_INTENSET_EXTINT7_Pos 7 /**< \brief (EIC_INTENSET) External Interrupt 7 Enable */ 320 #define EIC_INTENSET_EXTINT7 (1 << EIC_INTENSET_EXTINT7_Pos) 321 #define EIC_INTENSET_EXTINT8_Pos 8 /**< \brief (EIC_INTENSET) External Interrupt 8 Enable */ 322 #define EIC_INTENSET_EXTINT8 (1 << EIC_INTENSET_EXTINT8_Pos) 323 #define EIC_INTENSET_EXTINT9_Pos 9 /**< \brief (EIC_INTENSET) External Interrupt 9 Enable */ 324 #define EIC_INTENSET_EXTINT9 (1 << EIC_INTENSET_EXTINT9_Pos) 325 #define EIC_INTENSET_EXTINT10_Pos 10 /**< \brief (EIC_INTENSET) External Interrupt 10 Enable */ 326 #define EIC_INTENSET_EXTINT10 (1 << EIC_INTENSET_EXTINT10_Pos) 327 #define EIC_INTENSET_EXTINT11_Pos 11 /**< \brief (EIC_INTENSET) External Interrupt 11 Enable */ 328 #define EIC_INTENSET_EXTINT11 (1 << EIC_INTENSET_EXTINT11_Pos) 329 #define EIC_INTENSET_EXTINT12_Pos 12 /**< \brief (EIC_INTENSET) External Interrupt 12 Enable */ 330 #define EIC_INTENSET_EXTINT12 (1 << EIC_INTENSET_EXTINT12_Pos) 331 #define EIC_INTENSET_EXTINT13_Pos 13 /**< \brief (EIC_INTENSET) External Interrupt 13 Enable */ 332 #define EIC_INTENSET_EXTINT13 (1 << EIC_INTENSET_EXTINT13_Pos) 333 #define EIC_INTENSET_EXTINT14_Pos 14 /**< \brief (EIC_INTENSET) External Interrupt 14 Enable */ 334 #define EIC_INTENSET_EXTINT14 (1 << EIC_INTENSET_EXTINT14_Pos) 335 #define EIC_INTENSET_EXTINT15_Pos 15 /**< \brief (EIC_INTENSET) External Interrupt 15 Enable */ 336 #define EIC_INTENSET_EXTINT15 (1 << EIC_INTENSET_EXTINT15_Pos) 337 #define EIC_INTENSET_EXTINT_Pos 0 /**< \brief (EIC_INTENSET) External Interrupt x Enable */ 338 #define EIC_INTENSET_EXTINT_Msk (_U_(0xFFFF) << EIC_INTENSET_EXTINT_Pos) 339 #define EIC_INTENSET_EXTINT(value) (EIC_INTENSET_EXTINT_Msk & ((value) << EIC_INTENSET_EXTINT_Pos)) 340 #define EIC_INTENSET_MASK _U_(0x0000FFFF) /**< \brief (EIC_INTENSET) MASK Register */ 341 342 /* -------- EIC_INTFLAG : (EIC Offset: 0x10) (R/W 32) Interrupt Flag Status and Clear -------- */ 343 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 344 typedef union { // __I to avoid read-modify-write on write-to-clear register 345 struct { 346 __I uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 */ 347 __I uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 */ 348 __I uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 */ 349 __I uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 */ 350 __I uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 */ 351 __I uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 */ 352 __I uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 */ 353 __I uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 */ 354 __I uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 */ 355 __I uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 */ 356 __I uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 */ 357 __I uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 */ 358 __I uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 */ 359 __I uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 */ 360 __I uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 */ 361 __I uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 */ 362 __I uint32_t Reserved1:16; /*!< bit: 16..31 Reserved */ 363 } bit; /*!< Structure used for bit access */ 364 struct { 365 __I uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x */ 366 __I uint32_t Reserved1:16; /*!< bit: 16..31 Reserved */ 367 } vec; /*!< Structure used for vec access */ 368 uint32_t reg; /*!< Type used for register access */ 369 } EIC_INTFLAG_Type; 370 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 371 372 #define EIC_INTFLAG_OFFSET 0x10 /**< \brief (EIC_INTFLAG offset) Interrupt Flag Status and Clear */ 373 #define EIC_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (EIC_INTFLAG reset_value) Interrupt Flag Status and Clear */ 374 375 #define EIC_INTFLAG_EXTINT0_Pos 0 /**< \brief (EIC_INTFLAG) External Interrupt 0 */ 376 #define EIC_INTFLAG_EXTINT0 (1 << EIC_INTFLAG_EXTINT0_Pos) 377 #define EIC_INTFLAG_EXTINT1_Pos 1 /**< \brief (EIC_INTFLAG) External Interrupt 1 */ 378 #define EIC_INTFLAG_EXTINT1 (1 << EIC_INTFLAG_EXTINT1_Pos) 379 #define EIC_INTFLAG_EXTINT2_Pos 2 /**< \brief (EIC_INTFLAG) External Interrupt 2 */ 380 #define EIC_INTFLAG_EXTINT2 (1 << EIC_INTFLAG_EXTINT2_Pos) 381 #define EIC_INTFLAG_EXTINT3_Pos 3 /**< \brief (EIC_INTFLAG) External Interrupt 3 */ 382 #define EIC_INTFLAG_EXTINT3 (1 << EIC_INTFLAG_EXTINT3_Pos) 383 #define EIC_INTFLAG_EXTINT4_Pos 4 /**< \brief (EIC_INTFLAG) External Interrupt 4 */ 384 #define EIC_INTFLAG_EXTINT4 (1 << EIC_INTFLAG_EXTINT4_Pos) 385 #define EIC_INTFLAG_EXTINT5_Pos 5 /**< \brief (EIC_INTFLAG) External Interrupt 5 */ 386 #define EIC_INTFLAG_EXTINT5 (1 << EIC_INTFLAG_EXTINT5_Pos) 387 #define EIC_INTFLAG_EXTINT6_Pos 6 /**< \brief (EIC_INTFLAG) External Interrupt 6 */ 388 #define EIC_INTFLAG_EXTINT6 (1 << EIC_INTFLAG_EXTINT6_Pos) 389 #define EIC_INTFLAG_EXTINT7_Pos 7 /**< \brief (EIC_INTFLAG) External Interrupt 7 */ 390 #define EIC_INTFLAG_EXTINT7 (1 << EIC_INTFLAG_EXTINT7_Pos) 391 #define EIC_INTFLAG_EXTINT8_Pos 8 /**< \brief (EIC_INTFLAG) External Interrupt 8 */ 392 #define EIC_INTFLAG_EXTINT8 (1 << EIC_INTFLAG_EXTINT8_Pos) 393 #define EIC_INTFLAG_EXTINT9_Pos 9 /**< \brief (EIC_INTFLAG) External Interrupt 9 */ 394 #define EIC_INTFLAG_EXTINT9 (1 << EIC_INTFLAG_EXTINT9_Pos) 395 #define EIC_INTFLAG_EXTINT10_Pos 10 /**< \brief (EIC_INTFLAG) External Interrupt 10 */ 396 #define EIC_INTFLAG_EXTINT10 (1 << EIC_INTFLAG_EXTINT10_Pos) 397 #define EIC_INTFLAG_EXTINT11_Pos 11 /**< \brief (EIC_INTFLAG) External Interrupt 11 */ 398 #define EIC_INTFLAG_EXTINT11 (1 << EIC_INTFLAG_EXTINT11_Pos) 399 #define EIC_INTFLAG_EXTINT12_Pos 12 /**< \brief (EIC_INTFLAG) External Interrupt 12 */ 400 #define EIC_INTFLAG_EXTINT12 (1 << EIC_INTFLAG_EXTINT12_Pos) 401 #define EIC_INTFLAG_EXTINT13_Pos 13 /**< \brief (EIC_INTFLAG) External Interrupt 13 */ 402 #define EIC_INTFLAG_EXTINT13 (1 << EIC_INTFLAG_EXTINT13_Pos) 403 #define EIC_INTFLAG_EXTINT14_Pos 14 /**< \brief (EIC_INTFLAG) External Interrupt 14 */ 404 #define EIC_INTFLAG_EXTINT14 (1 << EIC_INTFLAG_EXTINT14_Pos) 405 #define EIC_INTFLAG_EXTINT15_Pos 15 /**< \brief (EIC_INTFLAG) External Interrupt 15 */ 406 #define EIC_INTFLAG_EXTINT15 (1 << EIC_INTFLAG_EXTINT15_Pos) 407 #define EIC_INTFLAG_EXTINT_Pos 0 /**< \brief (EIC_INTFLAG) External Interrupt x */ 408 #define EIC_INTFLAG_EXTINT_Msk (_U_(0xFFFF) << EIC_INTFLAG_EXTINT_Pos) 409 #define EIC_INTFLAG_EXTINT(value) (EIC_INTFLAG_EXTINT_Msk & ((value) << EIC_INTFLAG_EXTINT_Pos)) 410 #define EIC_INTFLAG_MASK _U_(0x0000FFFF) /**< \brief (EIC_INTFLAG) MASK Register */ 411 412 /* -------- EIC_WAKEUP : (EIC Offset: 0x14) (R/W 32) Wake-Up Enable -------- */ 413 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 414 typedef union { 415 struct { 416 uint32_t WAKEUPEN0:1; /*!< bit: 0 External Interrupt 0 Wake-up Enable */ 417 uint32_t WAKEUPEN1:1; /*!< bit: 1 External Interrupt 1 Wake-up Enable */ 418 uint32_t WAKEUPEN2:1; /*!< bit: 2 External Interrupt 2 Wake-up Enable */ 419 uint32_t WAKEUPEN3:1; /*!< bit: 3 External Interrupt 3 Wake-up Enable */ 420 uint32_t WAKEUPEN4:1; /*!< bit: 4 External Interrupt 4 Wake-up Enable */ 421 uint32_t WAKEUPEN5:1; /*!< bit: 5 External Interrupt 5 Wake-up Enable */ 422 uint32_t WAKEUPEN6:1; /*!< bit: 6 External Interrupt 6 Wake-up Enable */ 423 uint32_t WAKEUPEN7:1; /*!< bit: 7 External Interrupt 7 Wake-up Enable */ 424 uint32_t WAKEUPEN8:1; /*!< bit: 8 External Interrupt 8 Wake-up Enable */ 425 uint32_t WAKEUPEN9:1; /*!< bit: 9 External Interrupt 9 Wake-up Enable */ 426 uint32_t WAKEUPEN10:1; /*!< bit: 10 External Interrupt 10 Wake-up Enable */ 427 uint32_t WAKEUPEN11:1; /*!< bit: 11 External Interrupt 11 Wake-up Enable */ 428 uint32_t WAKEUPEN12:1; /*!< bit: 12 External Interrupt 12 Wake-up Enable */ 429 uint32_t WAKEUPEN13:1; /*!< bit: 13 External Interrupt 13 Wake-up Enable */ 430 uint32_t WAKEUPEN14:1; /*!< bit: 14 External Interrupt 14 Wake-up Enable */ 431 uint32_t WAKEUPEN15:1; /*!< bit: 15 External Interrupt 15 Wake-up Enable */ 432 uint32_t :16; /*!< bit: 16..31 Reserved */ 433 } bit; /*!< Structure used for bit access */ 434 struct { 435 uint32_t WAKEUPEN:16; /*!< bit: 0..15 External Interrupt x Wake-up Enable */ 436 uint32_t :16; /*!< bit: 16..31 Reserved */ 437 } vec; /*!< Structure used for vec access */ 438 uint32_t reg; /*!< Type used for register access */ 439 } EIC_WAKEUP_Type; 440 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 441 442 #define EIC_WAKEUP_OFFSET 0x14 /**< \brief (EIC_WAKEUP offset) Wake-Up Enable */ 443 #define EIC_WAKEUP_RESETVALUE _U_(0x00000000) /**< \brief (EIC_WAKEUP reset_value) Wake-Up Enable */ 444 445 #define EIC_WAKEUP_WAKEUPEN0_Pos 0 /**< \brief (EIC_WAKEUP) External Interrupt 0 Wake-up Enable */ 446 #define EIC_WAKEUP_WAKEUPEN0 (1 << EIC_WAKEUP_WAKEUPEN0_Pos) 447 #define EIC_WAKEUP_WAKEUPEN1_Pos 1 /**< \brief (EIC_WAKEUP) External Interrupt 1 Wake-up Enable */ 448 #define EIC_WAKEUP_WAKEUPEN1 (1 << EIC_WAKEUP_WAKEUPEN1_Pos) 449 #define EIC_WAKEUP_WAKEUPEN2_Pos 2 /**< \brief (EIC_WAKEUP) External Interrupt 2 Wake-up Enable */ 450 #define EIC_WAKEUP_WAKEUPEN2 (1 << EIC_WAKEUP_WAKEUPEN2_Pos) 451 #define EIC_WAKEUP_WAKEUPEN3_Pos 3 /**< \brief (EIC_WAKEUP) External Interrupt 3 Wake-up Enable */ 452 #define EIC_WAKEUP_WAKEUPEN3 (1 << EIC_WAKEUP_WAKEUPEN3_Pos) 453 #define EIC_WAKEUP_WAKEUPEN4_Pos 4 /**< \brief (EIC_WAKEUP) External Interrupt 4 Wake-up Enable */ 454 #define EIC_WAKEUP_WAKEUPEN4 (1 << EIC_WAKEUP_WAKEUPEN4_Pos) 455 #define EIC_WAKEUP_WAKEUPEN5_Pos 5 /**< \brief (EIC_WAKEUP) External Interrupt 5 Wake-up Enable */ 456 #define EIC_WAKEUP_WAKEUPEN5 (1 << EIC_WAKEUP_WAKEUPEN5_Pos) 457 #define EIC_WAKEUP_WAKEUPEN6_Pos 6 /**< \brief (EIC_WAKEUP) External Interrupt 6 Wake-up Enable */ 458 #define EIC_WAKEUP_WAKEUPEN6 (1 << EIC_WAKEUP_WAKEUPEN6_Pos) 459 #define EIC_WAKEUP_WAKEUPEN7_Pos 7 /**< \brief (EIC_WAKEUP) External Interrupt 7 Wake-up Enable */ 460 #define EIC_WAKEUP_WAKEUPEN7 (1 << EIC_WAKEUP_WAKEUPEN7_Pos) 461 #define EIC_WAKEUP_WAKEUPEN8_Pos 8 /**< \brief (EIC_WAKEUP) External Interrupt 8 Wake-up Enable */ 462 #define EIC_WAKEUP_WAKEUPEN8 (1 << EIC_WAKEUP_WAKEUPEN8_Pos) 463 #define EIC_WAKEUP_WAKEUPEN9_Pos 9 /**< \brief (EIC_WAKEUP) External Interrupt 9 Wake-up Enable */ 464 #define EIC_WAKEUP_WAKEUPEN9 (1 << EIC_WAKEUP_WAKEUPEN9_Pos) 465 #define EIC_WAKEUP_WAKEUPEN10_Pos 10 /**< \brief (EIC_WAKEUP) External Interrupt 10 Wake-up Enable */ 466 #define EIC_WAKEUP_WAKEUPEN10 (1 << EIC_WAKEUP_WAKEUPEN10_Pos) 467 #define EIC_WAKEUP_WAKEUPEN11_Pos 11 /**< \brief (EIC_WAKEUP) External Interrupt 11 Wake-up Enable */ 468 #define EIC_WAKEUP_WAKEUPEN11 (1 << EIC_WAKEUP_WAKEUPEN11_Pos) 469 #define EIC_WAKEUP_WAKEUPEN12_Pos 12 /**< \brief (EIC_WAKEUP) External Interrupt 12 Wake-up Enable */ 470 #define EIC_WAKEUP_WAKEUPEN12 (1 << EIC_WAKEUP_WAKEUPEN12_Pos) 471 #define EIC_WAKEUP_WAKEUPEN13_Pos 13 /**< \brief (EIC_WAKEUP) External Interrupt 13 Wake-up Enable */ 472 #define EIC_WAKEUP_WAKEUPEN13 (1 << EIC_WAKEUP_WAKEUPEN13_Pos) 473 #define EIC_WAKEUP_WAKEUPEN14_Pos 14 /**< \brief (EIC_WAKEUP) External Interrupt 14 Wake-up Enable */ 474 #define EIC_WAKEUP_WAKEUPEN14 (1 << EIC_WAKEUP_WAKEUPEN14_Pos) 475 #define EIC_WAKEUP_WAKEUPEN15_Pos 15 /**< \brief (EIC_WAKEUP) External Interrupt 15 Wake-up Enable */ 476 #define EIC_WAKEUP_WAKEUPEN15 (1 << EIC_WAKEUP_WAKEUPEN15_Pos) 477 #define EIC_WAKEUP_WAKEUPEN_Pos 0 /**< \brief (EIC_WAKEUP) External Interrupt x Wake-up Enable */ 478 #define EIC_WAKEUP_WAKEUPEN_Msk (_U_(0xFFFF) << EIC_WAKEUP_WAKEUPEN_Pos) 479 #define EIC_WAKEUP_WAKEUPEN(value) (EIC_WAKEUP_WAKEUPEN_Msk & ((value) << EIC_WAKEUP_WAKEUPEN_Pos)) 480 #define EIC_WAKEUP_MASK _U_(0x0000FFFF) /**< \brief (EIC_WAKEUP) MASK Register */ 481 482 /* -------- EIC_CONFIG : (EIC Offset: 0x18) (R/W 32) Configuration n -------- */ 483 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 484 typedef union { 485 struct { 486 uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense 0 Configuration */ 487 uint32_t FILTEN0:1; /*!< bit: 3 Filter 0 Enable */ 488 uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense 1 Configuration */ 489 uint32_t FILTEN1:1; /*!< bit: 7 Filter 1 Enable */ 490 uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense 2 Configuration */ 491 uint32_t FILTEN2:1; /*!< bit: 11 Filter 2 Enable */ 492 uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense 3 Configuration */ 493 uint32_t FILTEN3:1; /*!< bit: 15 Filter 3 Enable */ 494 uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense 4 Configuration */ 495 uint32_t FILTEN4:1; /*!< bit: 19 Filter 4 Enable */ 496 uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense 5 Configuration */ 497 uint32_t FILTEN5:1; /*!< bit: 23 Filter 5 Enable */ 498 uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense 6 Configuration */ 499 uint32_t FILTEN6:1; /*!< bit: 27 Filter 6 Enable */ 500 uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense 7 Configuration */ 501 uint32_t FILTEN7:1; /*!< bit: 31 Filter 7 Enable */ 502 } bit; /*!< Structure used for bit access */ 503 uint32_t reg; /*!< Type used for register access */ 504 } EIC_CONFIG_Type; 505 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 506 507 #define EIC_CONFIG_OFFSET 0x18 /**< \brief (EIC_CONFIG offset) Configuration n */ 508 #define EIC_CONFIG_RESETVALUE _U_(0x00000000) /**< \brief (EIC_CONFIG reset_value) Configuration n */ 509 510 #define EIC_CONFIG_SENSE0_Pos 0 /**< \brief (EIC_CONFIG) Input Sense 0 Configuration */ 511 #define EIC_CONFIG_SENSE0_Msk (_U_(0x7) << EIC_CONFIG_SENSE0_Pos) 512 #define EIC_CONFIG_SENSE0(value) (EIC_CONFIG_SENSE0_Msk & ((value) << EIC_CONFIG_SENSE0_Pos)) 513 #define EIC_CONFIG_SENSE0_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */ 514 #define EIC_CONFIG_SENSE0_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising-edge detection */ 515 #define EIC_CONFIG_SENSE0_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling-edge detection */ 516 #define EIC_CONFIG_SENSE0_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both-edges detection */ 517 #define EIC_CONFIG_SENSE0_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High-level detection */ 518 #define EIC_CONFIG_SENSE0_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low-level detection */ 519 #define EIC_CONFIG_SENSE0_NONE (EIC_CONFIG_SENSE0_NONE_Val << EIC_CONFIG_SENSE0_Pos) 520 #define EIC_CONFIG_SENSE0_RISE (EIC_CONFIG_SENSE0_RISE_Val << EIC_CONFIG_SENSE0_Pos) 521 #define EIC_CONFIG_SENSE0_FALL (EIC_CONFIG_SENSE0_FALL_Val << EIC_CONFIG_SENSE0_Pos) 522 #define EIC_CONFIG_SENSE0_BOTH (EIC_CONFIG_SENSE0_BOTH_Val << EIC_CONFIG_SENSE0_Pos) 523 #define EIC_CONFIG_SENSE0_HIGH (EIC_CONFIG_SENSE0_HIGH_Val << EIC_CONFIG_SENSE0_Pos) 524 #define EIC_CONFIG_SENSE0_LOW (EIC_CONFIG_SENSE0_LOW_Val << EIC_CONFIG_SENSE0_Pos) 525 #define EIC_CONFIG_FILTEN0_Pos 3 /**< \brief (EIC_CONFIG) Filter 0 Enable */ 526 #define EIC_CONFIG_FILTEN0 (_U_(0x1) << EIC_CONFIG_FILTEN0_Pos) 527 #define EIC_CONFIG_SENSE1_Pos 4 /**< \brief (EIC_CONFIG) Input Sense 1 Configuration */ 528 #define EIC_CONFIG_SENSE1_Msk (_U_(0x7) << EIC_CONFIG_SENSE1_Pos) 529 #define EIC_CONFIG_SENSE1(value) (EIC_CONFIG_SENSE1_Msk & ((value) << EIC_CONFIG_SENSE1_Pos)) 530 #define EIC_CONFIG_SENSE1_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */ 531 #define EIC_CONFIG_SENSE1_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */ 532 #define EIC_CONFIG_SENSE1_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */ 533 #define EIC_CONFIG_SENSE1_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */ 534 #define EIC_CONFIG_SENSE1_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */ 535 #define EIC_CONFIG_SENSE1_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */ 536 #define EIC_CONFIG_SENSE1_NONE (EIC_CONFIG_SENSE1_NONE_Val << EIC_CONFIG_SENSE1_Pos) 537 #define EIC_CONFIG_SENSE1_RISE (EIC_CONFIG_SENSE1_RISE_Val << EIC_CONFIG_SENSE1_Pos) 538 #define EIC_CONFIG_SENSE1_FALL (EIC_CONFIG_SENSE1_FALL_Val << EIC_CONFIG_SENSE1_Pos) 539 #define EIC_CONFIG_SENSE1_BOTH (EIC_CONFIG_SENSE1_BOTH_Val << EIC_CONFIG_SENSE1_Pos) 540 #define EIC_CONFIG_SENSE1_HIGH (EIC_CONFIG_SENSE1_HIGH_Val << EIC_CONFIG_SENSE1_Pos) 541 #define EIC_CONFIG_SENSE1_LOW (EIC_CONFIG_SENSE1_LOW_Val << EIC_CONFIG_SENSE1_Pos) 542 #define EIC_CONFIG_FILTEN1_Pos 7 /**< \brief (EIC_CONFIG) Filter 1 Enable */ 543 #define EIC_CONFIG_FILTEN1 (_U_(0x1) << EIC_CONFIG_FILTEN1_Pos) 544 #define EIC_CONFIG_SENSE2_Pos 8 /**< \brief (EIC_CONFIG) Input Sense 2 Configuration */ 545 #define EIC_CONFIG_SENSE2_Msk (_U_(0x7) << EIC_CONFIG_SENSE2_Pos) 546 #define EIC_CONFIG_SENSE2(value) (EIC_CONFIG_SENSE2_Msk & ((value) << EIC_CONFIG_SENSE2_Pos)) 547 #define EIC_CONFIG_SENSE2_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */ 548 #define EIC_CONFIG_SENSE2_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */ 549 #define EIC_CONFIG_SENSE2_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */ 550 #define EIC_CONFIG_SENSE2_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */ 551 #define EIC_CONFIG_SENSE2_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */ 552 #define EIC_CONFIG_SENSE2_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */ 553 #define EIC_CONFIG_SENSE2_NONE (EIC_CONFIG_SENSE2_NONE_Val << EIC_CONFIG_SENSE2_Pos) 554 #define EIC_CONFIG_SENSE2_RISE (EIC_CONFIG_SENSE2_RISE_Val << EIC_CONFIG_SENSE2_Pos) 555 #define EIC_CONFIG_SENSE2_FALL (EIC_CONFIG_SENSE2_FALL_Val << EIC_CONFIG_SENSE2_Pos) 556 #define EIC_CONFIG_SENSE2_BOTH (EIC_CONFIG_SENSE2_BOTH_Val << EIC_CONFIG_SENSE2_Pos) 557 #define EIC_CONFIG_SENSE2_HIGH (EIC_CONFIG_SENSE2_HIGH_Val << EIC_CONFIG_SENSE2_Pos) 558 #define EIC_CONFIG_SENSE2_LOW (EIC_CONFIG_SENSE2_LOW_Val << EIC_CONFIG_SENSE2_Pos) 559 #define EIC_CONFIG_FILTEN2_Pos 11 /**< \brief (EIC_CONFIG) Filter 2 Enable */ 560 #define EIC_CONFIG_FILTEN2 (_U_(0x1) << EIC_CONFIG_FILTEN2_Pos) 561 #define EIC_CONFIG_SENSE3_Pos 12 /**< \brief (EIC_CONFIG) Input Sense 3 Configuration */ 562 #define EIC_CONFIG_SENSE3_Msk (_U_(0x7) << EIC_CONFIG_SENSE3_Pos) 563 #define EIC_CONFIG_SENSE3(value) (EIC_CONFIG_SENSE3_Msk & ((value) << EIC_CONFIG_SENSE3_Pos)) 564 #define EIC_CONFIG_SENSE3_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */ 565 #define EIC_CONFIG_SENSE3_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */ 566 #define EIC_CONFIG_SENSE3_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */ 567 #define EIC_CONFIG_SENSE3_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */ 568 #define EIC_CONFIG_SENSE3_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */ 569 #define EIC_CONFIG_SENSE3_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */ 570 #define EIC_CONFIG_SENSE3_NONE (EIC_CONFIG_SENSE3_NONE_Val << EIC_CONFIG_SENSE3_Pos) 571 #define EIC_CONFIG_SENSE3_RISE (EIC_CONFIG_SENSE3_RISE_Val << EIC_CONFIG_SENSE3_Pos) 572 #define EIC_CONFIG_SENSE3_FALL (EIC_CONFIG_SENSE3_FALL_Val << EIC_CONFIG_SENSE3_Pos) 573 #define EIC_CONFIG_SENSE3_BOTH (EIC_CONFIG_SENSE3_BOTH_Val << EIC_CONFIG_SENSE3_Pos) 574 #define EIC_CONFIG_SENSE3_HIGH (EIC_CONFIG_SENSE3_HIGH_Val << EIC_CONFIG_SENSE3_Pos) 575 #define EIC_CONFIG_SENSE3_LOW (EIC_CONFIG_SENSE3_LOW_Val << EIC_CONFIG_SENSE3_Pos) 576 #define EIC_CONFIG_FILTEN3_Pos 15 /**< \brief (EIC_CONFIG) Filter 3 Enable */ 577 #define EIC_CONFIG_FILTEN3 (_U_(0x1) << EIC_CONFIG_FILTEN3_Pos) 578 #define EIC_CONFIG_SENSE4_Pos 16 /**< \brief (EIC_CONFIG) Input Sense 4 Configuration */ 579 #define EIC_CONFIG_SENSE4_Msk (_U_(0x7) << EIC_CONFIG_SENSE4_Pos) 580 #define EIC_CONFIG_SENSE4(value) (EIC_CONFIG_SENSE4_Msk & ((value) << EIC_CONFIG_SENSE4_Pos)) 581 #define EIC_CONFIG_SENSE4_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */ 582 #define EIC_CONFIG_SENSE4_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */ 583 #define EIC_CONFIG_SENSE4_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */ 584 #define EIC_CONFIG_SENSE4_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */ 585 #define EIC_CONFIG_SENSE4_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */ 586 #define EIC_CONFIG_SENSE4_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */ 587 #define EIC_CONFIG_SENSE4_NONE (EIC_CONFIG_SENSE4_NONE_Val << EIC_CONFIG_SENSE4_Pos) 588 #define EIC_CONFIG_SENSE4_RISE (EIC_CONFIG_SENSE4_RISE_Val << EIC_CONFIG_SENSE4_Pos) 589 #define EIC_CONFIG_SENSE4_FALL (EIC_CONFIG_SENSE4_FALL_Val << EIC_CONFIG_SENSE4_Pos) 590 #define EIC_CONFIG_SENSE4_BOTH (EIC_CONFIG_SENSE4_BOTH_Val << EIC_CONFIG_SENSE4_Pos) 591 #define EIC_CONFIG_SENSE4_HIGH (EIC_CONFIG_SENSE4_HIGH_Val << EIC_CONFIG_SENSE4_Pos) 592 #define EIC_CONFIG_SENSE4_LOW (EIC_CONFIG_SENSE4_LOW_Val << EIC_CONFIG_SENSE4_Pos) 593 #define EIC_CONFIG_FILTEN4_Pos 19 /**< \brief (EIC_CONFIG) Filter 4 Enable */ 594 #define EIC_CONFIG_FILTEN4 (_U_(0x1) << EIC_CONFIG_FILTEN4_Pos) 595 #define EIC_CONFIG_SENSE5_Pos 20 /**< \brief (EIC_CONFIG) Input Sense 5 Configuration */ 596 #define EIC_CONFIG_SENSE5_Msk (_U_(0x7) << EIC_CONFIG_SENSE5_Pos) 597 #define EIC_CONFIG_SENSE5(value) (EIC_CONFIG_SENSE5_Msk & ((value) << EIC_CONFIG_SENSE5_Pos)) 598 #define EIC_CONFIG_SENSE5_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */ 599 #define EIC_CONFIG_SENSE5_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */ 600 #define EIC_CONFIG_SENSE5_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */ 601 #define EIC_CONFIG_SENSE5_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */ 602 #define EIC_CONFIG_SENSE5_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */ 603 #define EIC_CONFIG_SENSE5_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */ 604 #define EIC_CONFIG_SENSE5_NONE (EIC_CONFIG_SENSE5_NONE_Val << EIC_CONFIG_SENSE5_Pos) 605 #define EIC_CONFIG_SENSE5_RISE (EIC_CONFIG_SENSE5_RISE_Val << EIC_CONFIG_SENSE5_Pos) 606 #define EIC_CONFIG_SENSE5_FALL (EIC_CONFIG_SENSE5_FALL_Val << EIC_CONFIG_SENSE5_Pos) 607 #define EIC_CONFIG_SENSE5_BOTH (EIC_CONFIG_SENSE5_BOTH_Val << EIC_CONFIG_SENSE5_Pos) 608 #define EIC_CONFIG_SENSE5_HIGH (EIC_CONFIG_SENSE5_HIGH_Val << EIC_CONFIG_SENSE5_Pos) 609 #define EIC_CONFIG_SENSE5_LOW (EIC_CONFIG_SENSE5_LOW_Val << EIC_CONFIG_SENSE5_Pos) 610 #define EIC_CONFIG_FILTEN5_Pos 23 /**< \brief (EIC_CONFIG) Filter 5 Enable */ 611 #define EIC_CONFIG_FILTEN5 (_U_(0x1) << EIC_CONFIG_FILTEN5_Pos) 612 #define EIC_CONFIG_SENSE6_Pos 24 /**< \brief (EIC_CONFIG) Input Sense 6 Configuration */ 613 #define EIC_CONFIG_SENSE6_Msk (_U_(0x7) << EIC_CONFIG_SENSE6_Pos) 614 #define EIC_CONFIG_SENSE6(value) (EIC_CONFIG_SENSE6_Msk & ((value) << EIC_CONFIG_SENSE6_Pos)) 615 #define EIC_CONFIG_SENSE6_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */ 616 #define EIC_CONFIG_SENSE6_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */ 617 #define EIC_CONFIG_SENSE6_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */ 618 #define EIC_CONFIG_SENSE6_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */ 619 #define EIC_CONFIG_SENSE6_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */ 620 #define EIC_CONFIG_SENSE6_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */ 621 #define EIC_CONFIG_SENSE6_NONE (EIC_CONFIG_SENSE6_NONE_Val << EIC_CONFIG_SENSE6_Pos) 622 #define EIC_CONFIG_SENSE6_RISE (EIC_CONFIG_SENSE6_RISE_Val << EIC_CONFIG_SENSE6_Pos) 623 #define EIC_CONFIG_SENSE6_FALL (EIC_CONFIG_SENSE6_FALL_Val << EIC_CONFIG_SENSE6_Pos) 624 #define EIC_CONFIG_SENSE6_BOTH (EIC_CONFIG_SENSE6_BOTH_Val << EIC_CONFIG_SENSE6_Pos) 625 #define EIC_CONFIG_SENSE6_HIGH (EIC_CONFIG_SENSE6_HIGH_Val << EIC_CONFIG_SENSE6_Pos) 626 #define EIC_CONFIG_SENSE6_LOW (EIC_CONFIG_SENSE6_LOW_Val << EIC_CONFIG_SENSE6_Pos) 627 #define EIC_CONFIG_FILTEN6_Pos 27 /**< \brief (EIC_CONFIG) Filter 6 Enable */ 628 #define EIC_CONFIG_FILTEN6 (_U_(0x1) << EIC_CONFIG_FILTEN6_Pos) 629 #define EIC_CONFIG_SENSE7_Pos 28 /**< \brief (EIC_CONFIG) Input Sense 7 Configuration */ 630 #define EIC_CONFIG_SENSE7_Msk (_U_(0x7) << EIC_CONFIG_SENSE7_Pos) 631 #define EIC_CONFIG_SENSE7(value) (EIC_CONFIG_SENSE7_Msk & ((value) << EIC_CONFIG_SENSE7_Pos)) 632 #define EIC_CONFIG_SENSE7_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */ 633 #define EIC_CONFIG_SENSE7_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */ 634 #define EIC_CONFIG_SENSE7_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */ 635 #define EIC_CONFIG_SENSE7_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */ 636 #define EIC_CONFIG_SENSE7_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */ 637 #define EIC_CONFIG_SENSE7_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */ 638 #define EIC_CONFIG_SENSE7_NONE (EIC_CONFIG_SENSE7_NONE_Val << EIC_CONFIG_SENSE7_Pos) 639 #define EIC_CONFIG_SENSE7_RISE (EIC_CONFIG_SENSE7_RISE_Val << EIC_CONFIG_SENSE7_Pos) 640 #define EIC_CONFIG_SENSE7_FALL (EIC_CONFIG_SENSE7_FALL_Val << EIC_CONFIG_SENSE7_Pos) 641 #define EIC_CONFIG_SENSE7_BOTH (EIC_CONFIG_SENSE7_BOTH_Val << EIC_CONFIG_SENSE7_Pos) 642 #define EIC_CONFIG_SENSE7_HIGH (EIC_CONFIG_SENSE7_HIGH_Val << EIC_CONFIG_SENSE7_Pos) 643 #define EIC_CONFIG_SENSE7_LOW (EIC_CONFIG_SENSE7_LOW_Val << EIC_CONFIG_SENSE7_Pos) 644 #define EIC_CONFIG_FILTEN7_Pos 31 /**< \brief (EIC_CONFIG) Filter 7 Enable */ 645 #define EIC_CONFIG_FILTEN7 (_U_(0x1) << EIC_CONFIG_FILTEN7_Pos) 646 #define EIC_CONFIG_MASK _U_(0xFFFFFFFF) /**< \brief (EIC_CONFIG) MASK Register */ 647 648 /** \brief EIC hardware registers */ 649 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 650 typedef struct { 651 __IO EIC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */ 652 __I EIC_STATUS_Type STATUS; /**< \brief Offset: 0x01 (R/ 8) Status */ 653 __IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x02 (R/W 8) Non-Maskable Interrupt Control */ 654 __IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x03 (R/W 8) Non-Maskable Interrupt Flag Status and Clear */ 655 __IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) Event Control */ 656 __IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Clear */ 657 __IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Set */ 658 __IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x10 (R/W 32) Interrupt Flag Status and Clear */ 659 __IO EIC_WAKEUP_Type WAKEUP; /**< \brief Offset: 0x14 (R/W 32) Wake-Up Enable */ 660 __IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x18 (R/W 32) Configuration n */ 661 } Eic; 662 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 663 664 /*@}*/ 665 666 #endif /* _SAMR21_EIC_COMPONENT_ */ 667
