1 /** 2 * \file 3 * 4 * \brief Component description for DAC 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAMR21_DAC_COMPONENT_ 30 #define _SAMR21_DAC_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR DAC */ 34 /* ========================================================================== */ 35 /** \addtogroup SAMR21_DAC Digital Analog Converter */ 36 /*@{*/ 37 38 #define DAC_U2214 39 #define REV_DAC 0x110 40 41 /* -------- DAC_CTRLA : (DAC Offset: 0x0) (R/W 8) Control A -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint8_t SWRST:1; /*!< bit: 0 Software Reset */ 46 uint8_t ENABLE:1; /*!< bit: 1 Enable */ 47 uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ 48 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 49 } bit; /*!< Structure used for bit access */ 50 uint8_t reg; /*!< Type used for register access */ 51 } DAC_CTRLA_Type; 52 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 53 54 #define DAC_CTRLA_OFFSET 0x0 /**< \brief (DAC_CTRLA offset) Control A */ 55 #define DAC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (DAC_CTRLA reset_value) Control A */ 56 57 #define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */ 58 #define DAC_CTRLA_SWRST (_U_(0x1) << DAC_CTRLA_SWRST_Pos) 59 #define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable */ 60 #define DAC_CTRLA_ENABLE (_U_(0x1) << DAC_CTRLA_ENABLE_Pos) 61 #define DAC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (DAC_CTRLA) Run in Standby */ 62 #define DAC_CTRLA_RUNSTDBY (_U_(0x1) << DAC_CTRLA_RUNSTDBY_Pos) 63 #define DAC_CTRLA_MASK _U_(0x07) /**< \brief (DAC_CTRLA) MASK Register */ 64 65 /* -------- DAC_CTRLB : (DAC Offset: 0x1) (R/W 8) Control B -------- */ 66 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 67 typedef union { 68 struct { 69 uint8_t EOEN:1; /*!< bit: 0 External Output Enable */ 70 uint8_t IOEN:1; /*!< bit: 1 Internal Output Enable */ 71 uint8_t LEFTADJ:1; /*!< bit: 2 Left Adjusted Data */ 72 uint8_t VPD:1; /*!< bit: 3 Voltage Pump Disable */ 73 uint8_t BDWP:1; /*!< bit: 4 Bypass DATABUF Write Protection */ 74 uint8_t :1; /*!< bit: 5 Reserved */ 75 uint8_t REFSEL:2; /*!< bit: 6.. 7 Reference Selection */ 76 } bit; /*!< Structure used for bit access */ 77 uint8_t reg; /*!< Type used for register access */ 78 } DAC_CTRLB_Type; 79 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 80 81 #define DAC_CTRLB_OFFSET 0x1 /**< \brief (DAC_CTRLB offset) Control B */ 82 #define DAC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (DAC_CTRLB reset_value) Control B */ 83 84 #define DAC_CTRLB_EOEN_Pos 0 /**< \brief (DAC_CTRLB) External Output Enable */ 85 #define DAC_CTRLB_EOEN (_U_(0x1) << DAC_CTRLB_EOEN_Pos) 86 #define DAC_CTRLB_IOEN_Pos 1 /**< \brief (DAC_CTRLB) Internal Output Enable */ 87 #define DAC_CTRLB_IOEN (_U_(0x1) << DAC_CTRLB_IOEN_Pos) 88 #define DAC_CTRLB_LEFTADJ_Pos 2 /**< \brief (DAC_CTRLB) Left Adjusted Data */ 89 #define DAC_CTRLB_LEFTADJ (_U_(0x1) << DAC_CTRLB_LEFTADJ_Pos) 90 #define DAC_CTRLB_VPD_Pos 3 /**< \brief (DAC_CTRLB) Voltage Pump Disable */ 91 #define DAC_CTRLB_VPD (_U_(0x1) << DAC_CTRLB_VPD_Pos) 92 #define DAC_CTRLB_BDWP_Pos 4 /**< \brief (DAC_CTRLB) Bypass DATABUF Write Protection */ 93 #define DAC_CTRLB_BDWP (_U_(0x1) << DAC_CTRLB_BDWP_Pos) 94 #define DAC_CTRLB_REFSEL_Pos 6 /**< \brief (DAC_CTRLB) Reference Selection */ 95 #define DAC_CTRLB_REFSEL_Msk (_U_(0x3) << DAC_CTRLB_REFSEL_Pos) 96 #define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos)) 97 #define DAC_CTRLB_REFSEL_INT1V_Val _U_(0x0) /**< \brief (DAC_CTRLB) Internal 1.0V reference */ 98 #define DAC_CTRLB_REFSEL_AVCC_Val _U_(0x1) /**< \brief (DAC_CTRLB) AVCC */ 99 #define DAC_CTRLB_REFSEL_VREFP_Val _U_(0x2) /**< \brief (DAC_CTRLB) External reference */ 100 #define DAC_CTRLB_REFSEL_INT1V (DAC_CTRLB_REFSEL_INT1V_Val << DAC_CTRLB_REFSEL_Pos) 101 #define DAC_CTRLB_REFSEL_AVCC (DAC_CTRLB_REFSEL_AVCC_Val << DAC_CTRLB_REFSEL_Pos) 102 #define DAC_CTRLB_REFSEL_VREFP (DAC_CTRLB_REFSEL_VREFP_Val << DAC_CTRLB_REFSEL_Pos) 103 #define DAC_CTRLB_MASK _U_(0xDF) /**< \brief (DAC_CTRLB) MASK Register */ 104 105 /* -------- DAC_EVCTRL : (DAC Offset: 0x2) (R/W 8) Event Control -------- */ 106 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 107 typedef union { 108 struct { 109 uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event Input */ 110 uint8_t EMPTYEO:1; /*!< bit: 1 Data Buffer Empty Event Output */ 111 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 112 } bit; /*!< Structure used for bit access */ 113 uint8_t reg; /*!< Type used for register access */ 114 } DAC_EVCTRL_Type; 115 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 116 117 #define DAC_EVCTRL_OFFSET 0x2 /**< \brief (DAC_EVCTRL offset) Event Control */ 118 #define DAC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_EVCTRL reset_value) Event Control */ 119 120 #define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input */ 121 #define DAC_EVCTRL_STARTEI (_U_(0x1) << DAC_EVCTRL_STARTEI_Pos) 122 #define DAC_EVCTRL_EMPTYEO_Pos 1 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output */ 123 #define DAC_EVCTRL_EMPTYEO (_U_(0x1) << DAC_EVCTRL_EMPTYEO_Pos) 124 #define DAC_EVCTRL_MASK _U_(0x03) /**< \brief (DAC_EVCTRL) MASK Register */ 125 126 /* -------- DAC_INTENCLR : (DAC Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */ 127 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 128 typedef union { 129 struct { 130 uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */ 131 uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */ 132 uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */ 133 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 134 } bit; /*!< Structure used for bit access */ 135 uint8_t reg; /*!< Type used for register access */ 136 } DAC_INTENCLR_Type; 137 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 138 139 #define DAC_INTENCLR_OFFSET 0x4 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */ 140 #define DAC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */ 141 142 #define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable */ 143 #define DAC_INTENCLR_UNDERRUN (_U_(0x1) << DAC_INTENCLR_UNDERRUN_Pos) 144 #define DAC_INTENCLR_EMPTY_Pos 1 /**< \brief (DAC_INTENCLR) Data Buffer Empty Interrupt Enable */ 145 #define DAC_INTENCLR_EMPTY (_U_(0x1) << DAC_INTENCLR_EMPTY_Pos) 146 #define DAC_INTENCLR_SYNCRDY_Pos 2 /**< \brief (DAC_INTENCLR) Synchronization Ready Interrupt Enable */ 147 #define DAC_INTENCLR_SYNCRDY (_U_(0x1) << DAC_INTENCLR_SYNCRDY_Pos) 148 #define DAC_INTENCLR_MASK _U_(0x07) /**< \brief (DAC_INTENCLR) MASK Register */ 149 150 /* -------- DAC_INTENSET : (DAC Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */ 151 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 152 typedef union { 153 struct { 154 uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */ 155 uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */ 156 uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */ 157 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 158 } bit; /*!< Structure used for bit access */ 159 uint8_t reg; /*!< Type used for register access */ 160 } DAC_INTENSET_Type; 161 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 162 163 #define DAC_INTENSET_OFFSET 0x5 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */ 164 #define DAC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */ 165 166 #define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable */ 167 #define DAC_INTENSET_UNDERRUN (_U_(0x1) << DAC_INTENSET_UNDERRUN_Pos) 168 #define DAC_INTENSET_EMPTY_Pos 1 /**< \brief (DAC_INTENSET) Data Buffer Empty Interrupt Enable */ 169 #define DAC_INTENSET_EMPTY (_U_(0x1) << DAC_INTENSET_EMPTY_Pos) 170 #define DAC_INTENSET_SYNCRDY_Pos 2 /**< \brief (DAC_INTENSET) Synchronization Ready Interrupt Enable */ 171 #define DAC_INTENSET_SYNCRDY (_U_(0x1) << DAC_INTENSET_SYNCRDY_Pos) 172 #define DAC_INTENSET_MASK _U_(0x07) /**< \brief (DAC_INTENSET) MASK Register */ 173 174 /* -------- DAC_INTFLAG : (DAC Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */ 175 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 176 typedef union { // __I to avoid read-modify-write on write-to-clear register 177 struct { 178 __I uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */ 179 __I uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */ 180 __I uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready */ 181 __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ 182 } bit; /*!< Structure used for bit access */ 183 uint8_t reg; /*!< Type used for register access */ 184 } DAC_INTFLAG_Type; 185 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 186 187 #define DAC_INTFLAG_OFFSET 0x6 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */ 188 #define DAC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */ 189 190 #define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Underrun */ 191 #define DAC_INTFLAG_UNDERRUN (_U_(0x1) << DAC_INTFLAG_UNDERRUN_Pos) 192 #define DAC_INTFLAG_EMPTY_Pos 1 /**< \brief (DAC_INTFLAG) Data Buffer Empty */ 193 #define DAC_INTFLAG_EMPTY (_U_(0x1) << DAC_INTFLAG_EMPTY_Pos) 194 #define DAC_INTFLAG_SYNCRDY_Pos 2 /**< \brief (DAC_INTFLAG) Synchronization Ready */ 195 #define DAC_INTFLAG_SYNCRDY (_U_(0x1) << DAC_INTFLAG_SYNCRDY_Pos) 196 #define DAC_INTFLAG_MASK _U_(0x07) /**< \brief (DAC_INTFLAG) MASK Register */ 197 198 /* -------- DAC_STATUS : (DAC Offset: 0x7) (R/ 8) Status -------- */ 199 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 200 typedef union { 201 struct { 202 uint8_t :7; /*!< bit: 0.. 6 Reserved */ 203 uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */ 204 } bit; /*!< Structure used for bit access */ 205 uint8_t reg; /*!< Type used for register access */ 206 } DAC_STATUS_Type; 207 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 208 209 #define DAC_STATUS_OFFSET 0x7 /**< \brief (DAC_STATUS offset) Status */ 210 #define DAC_STATUS_RESETVALUE _U_(0x00) /**< \brief (DAC_STATUS reset_value) Status */ 211 212 #define DAC_STATUS_SYNCBUSY_Pos 7 /**< \brief (DAC_STATUS) Synchronization Busy Status */ 213 #define DAC_STATUS_SYNCBUSY (_U_(0x1) << DAC_STATUS_SYNCBUSY_Pos) 214 #define DAC_STATUS_MASK _U_(0x80) /**< \brief (DAC_STATUS) MASK Register */ 215 216 /* -------- DAC_DATA : (DAC Offset: 0x8) (R/W 16) Data -------- */ 217 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 218 typedef union { 219 struct { 220 uint16_t DATA:16; /*!< bit: 0..15 Data value to be converted */ 221 } bit; /*!< Structure used for bit access */ 222 uint16_t reg; /*!< Type used for register access */ 223 } DAC_DATA_Type; 224 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 225 226 #define DAC_DATA_OFFSET 0x8 /**< \brief (DAC_DATA offset) Data */ 227 #define DAC_DATA_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATA reset_value) Data */ 228 229 #define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) Data value to be converted */ 230 #define DAC_DATA_DATA_Msk (_U_(0xFFFF) << DAC_DATA_DATA_Pos) 231 #define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos)) 232 #define DAC_DATA_MASK _U_(0xFFFF) /**< \brief (DAC_DATA) MASK Register */ 233 234 /* -------- DAC_DATABUF : (DAC Offset: 0xC) (R/W 16) Data Buffer -------- */ 235 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 236 typedef union { 237 struct { 238 uint16_t DATABUF:16; /*!< bit: 0..15 Data Buffer */ 239 } bit; /*!< Structure used for bit access */ 240 uint16_t reg; /*!< Type used for register access */ 241 } DAC_DATABUF_Type; 242 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 243 244 #define DAC_DATABUF_OFFSET 0xC /**< \brief (DAC_DATABUF offset) Data Buffer */ 245 #define DAC_DATABUF_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATABUF reset_value) Data Buffer */ 246 247 #define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) Data Buffer */ 248 #define DAC_DATABUF_DATABUF_Msk (_U_(0xFFFF) << DAC_DATABUF_DATABUF_Pos) 249 #define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos)) 250 #define DAC_DATABUF_MASK _U_(0xFFFF) /**< \brief (DAC_DATABUF) MASK Register */ 251 252 /** \brief DAC hardware registers */ 253 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 254 typedef struct { 255 __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control A */ 256 __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x1 (R/W 8) Control B */ 257 __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2 (R/W 8) Event Control */ 258 RoReg8 Reserved1[0x1]; 259 __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */ 260 __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */ 261 __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */ 262 __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */ 263 __IO DAC_DATA_Type DATA; /**< \brief Offset: 0x8 (R/W 16) Data */ 264 RoReg8 Reserved2[0x2]; 265 __IO DAC_DATABUF_Type DATABUF; /**< \brief Offset: 0xC (R/W 16) Data Buffer */ 266 } Dac; 267 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 268 269 /*@}*/ 270 271 #endif /* _SAMR21_DAC_COMPONENT_ */ 272
