1 /** 2 * \file 3 * 4 * \brief Instance description for NVMCTRL 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAML21_NVMCTRL_INSTANCE_ 31 #define _SAML21_NVMCTRL_INSTANCE_ 32 33 /* ========== Register definition for NVMCTRL peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_NVMCTRL_CTRLA (0x41004000) /**< \brief (NVMCTRL) Control A */ 36 #define REG_NVMCTRL_CTRLB (0x41004004) /**< \brief (NVMCTRL) Control B */ 37 #define REG_NVMCTRL_PARAM (0x41004008) /**< \brief (NVMCTRL) NVM Parameter */ 38 #define REG_NVMCTRL_INTENCLR (0x4100400C) /**< \brief (NVMCTRL) Interrupt Enable Clear */ 39 #define REG_NVMCTRL_INTENSET (0x41004010) /**< \brief (NVMCTRL) Interrupt Enable Set */ 40 #define REG_NVMCTRL_INTFLAG (0x41004014) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */ 41 #define REG_NVMCTRL_STATUS (0x41004018) /**< \brief (NVMCTRL) Status */ 42 #define REG_NVMCTRL_ADDR (0x4100401C) /**< \brief (NVMCTRL) Address */ 43 #define REG_NVMCTRL_LOCK (0x41004020) /**< \brief (NVMCTRL) Lock Section */ 44 #else 45 #define REG_NVMCTRL_CTRLA (*(RwReg16*)0x41004000UL) /**< \brief (NVMCTRL) Control A */ 46 #define REG_NVMCTRL_CTRLB (*(RwReg *)0x41004004UL) /**< \brief (NVMCTRL) Control B */ 47 #define REG_NVMCTRL_PARAM (*(RwReg *)0x41004008UL) /**< \brief (NVMCTRL) NVM Parameter */ 48 #define REG_NVMCTRL_INTENCLR (*(RwReg8 *)0x4100400CUL) /**< \brief (NVMCTRL) Interrupt Enable Clear */ 49 #define REG_NVMCTRL_INTENSET (*(RwReg8 *)0x41004010UL) /**< \brief (NVMCTRL) Interrupt Enable Set */ 50 #define REG_NVMCTRL_INTFLAG (*(RwReg8 *)0x41004014UL) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */ 51 #define REG_NVMCTRL_STATUS (*(RwReg16*)0x41004018UL) /**< \brief (NVMCTRL) Status */ 52 #define REG_NVMCTRL_ADDR (*(RwReg *)0x4100401CUL) /**< \brief (NVMCTRL) Address */ 53 #define REG_NVMCTRL_LOCK (*(RwReg16*)0x41004020UL) /**< \brief (NVMCTRL) Lock Section */ 54 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 55 56 /* ========== Instance parameters for NVMCTRL peripheral ========== */ 57 #define NVMCTRL_AUX0_ADDRESS 0x00804000 58 #define NVMCTRL_AUX1_ADDRESS 0x00806000 59 #define NVMCTRL_AUX2_ADDRESS 0x00808000 60 #define NVMCTRL_AUX3_ADDRESS 0x0080A000 61 #define NVMCTRL_CLK_AHB_ID 8 // Index of AHB Clock in PM.AHBMASK register 62 #define NVMCTRL_CLK_AHB_ID_PICACHU 15 // Index of PICACHU AHB Clock 63 #define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0XC0000007FFFFFFFF 64 #define NVMCTRL_FLASH_SIZE 262144 65 #define NVMCTRL_GCLK_ID 35 // Index of Generic Clock for test 66 #define NVMCTRL_LOCKBIT_ADDRESS 0x00802000 67 #define NVMCTRL_PAGE_HW 32 68 #define NVMCTRL_PAGE_SIZE 64 69 #define NVMCTRL_PAGE_W 16 70 #define NVMCTRL_PMSB 3 71 #define NVMCTRL_PSZ_BITS 6 72 #define NVMCTRL_ROW_PAGES 4 73 #define NVMCTRL_ROW_SIZE 256 74 #define NVMCTRL_USER_PAGE_ADDRESS 0x00800000 75 #define NVMCTRL_USER_PAGE_OFFSET 0x00800000 76 #define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0XC01FFFFFFFFFFFFF 77 #define NVMCTRL_RWWEE_PAGES 128 78 #define NVMCTRL_RWW_EEPROM_ADDR 0x00400000 // Start address of the RWW EEPROM area 79 80 #endif /* _SAML21_NVMCTRL_INSTANCE_ */ 81
