1 /** 2 * \file 3 * 4 * \brief Instance description for TC0 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAME54_TC0_INSTANCE_ 31 #define _SAME54_TC0_INSTANCE_ 32 33 /* ========== Register definition for TC0 peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_TC0_CTRLA (0x40003800) /**< \brief (TC0) Control A */ 36 #define REG_TC0_CTRLBCLR (0x40003804) /**< \brief (TC0) Control B Clear */ 37 #define REG_TC0_CTRLBSET (0x40003805) /**< \brief (TC0) Control B Set */ 38 #define REG_TC0_EVCTRL (0x40003806) /**< \brief (TC0) Event Control */ 39 #define REG_TC0_INTENCLR (0x40003808) /**< \brief (TC0) Interrupt Enable Clear */ 40 #define REG_TC0_INTENSET (0x40003809) /**< \brief (TC0) Interrupt Enable Set */ 41 #define REG_TC0_INTFLAG (0x4000380A) /**< \brief (TC0) Interrupt Flag Status and Clear */ 42 #define REG_TC0_STATUS (0x4000380B) /**< \brief (TC0) Status */ 43 #define REG_TC0_WAVE (0x4000380C) /**< \brief (TC0) Waveform Generation Control */ 44 #define REG_TC0_DRVCTRL (0x4000380D) /**< \brief (TC0) Control C */ 45 #define REG_TC0_DBGCTRL (0x4000380F) /**< \brief (TC0) Debug Control */ 46 #define REG_TC0_SYNCBUSY (0x40003810) /**< \brief (TC0) Synchronization Status */ 47 #define REG_TC0_COUNT16_COUNT (0x40003814) /**< \brief (TC0) COUNT16 Count */ 48 #define REG_TC0_COUNT16_CC0 (0x4000381C) /**< \brief (TC0) COUNT16 Compare and Capture 0 */ 49 #define REG_TC0_COUNT16_CC1 (0x4000381E) /**< \brief (TC0) COUNT16 Compare and Capture 1 */ 50 #define REG_TC0_COUNT16_CCBUF0 (0x40003830) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 0 */ 51 #define REG_TC0_COUNT16_CCBUF1 (0x40003832) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 1 */ 52 #define REG_TC0_COUNT32_COUNT (0x40003814) /**< \brief (TC0) COUNT32 Count */ 53 #define REG_TC0_COUNT32_CC0 (0x4000381C) /**< \brief (TC0) COUNT32 Compare and Capture 0 */ 54 #define REG_TC0_COUNT32_CC1 (0x40003820) /**< \brief (TC0) COUNT32 Compare and Capture 1 */ 55 #define REG_TC0_COUNT32_CCBUF0 (0x40003830) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 0 */ 56 #define REG_TC0_COUNT32_CCBUF1 (0x40003834) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 1 */ 57 #define REG_TC0_COUNT8_COUNT (0x40003814) /**< \brief (TC0) COUNT8 Count */ 58 #define REG_TC0_COUNT8_PER (0x4000381B) /**< \brief (TC0) COUNT8 Period */ 59 #define REG_TC0_COUNT8_CC0 (0x4000381C) /**< \brief (TC0) COUNT8 Compare and Capture 0 */ 60 #define REG_TC0_COUNT8_CC1 (0x4000381D) /**< \brief (TC0) COUNT8 Compare and Capture 1 */ 61 #define REG_TC0_COUNT8_PERBUF (0x4000382F) /**< \brief (TC0) COUNT8 Period Buffer */ 62 #define REG_TC0_COUNT8_CCBUF0 (0x40003830) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 0 */ 63 #define REG_TC0_COUNT8_CCBUF1 (0x40003831) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 1 */ 64 #else 65 #define REG_TC0_CTRLA (*(RwReg *)0x40003800UL) /**< \brief (TC0) Control A */ 66 #define REG_TC0_CTRLBCLR (*(RwReg8 *)0x40003804UL) /**< \brief (TC0) Control B Clear */ 67 #define REG_TC0_CTRLBSET (*(RwReg8 *)0x40003805UL) /**< \brief (TC0) Control B Set */ 68 #define REG_TC0_EVCTRL (*(RwReg16*)0x40003806UL) /**< \brief (TC0) Event Control */ 69 #define REG_TC0_INTENCLR (*(RwReg8 *)0x40003808UL) /**< \brief (TC0) Interrupt Enable Clear */ 70 #define REG_TC0_INTENSET (*(RwReg8 *)0x40003809UL) /**< \brief (TC0) Interrupt Enable Set */ 71 #define REG_TC0_INTFLAG (*(RwReg8 *)0x4000380AUL) /**< \brief (TC0) Interrupt Flag Status and Clear */ 72 #define REG_TC0_STATUS (*(RwReg8 *)0x4000380BUL) /**< \brief (TC0) Status */ 73 #define REG_TC0_WAVE (*(RwReg8 *)0x4000380CUL) /**< \brief (TC0) Waveform Generation Control */ 74 #define REG_TC0_DRVCTRL (*(RwReg8 *)0x4000380DUL) /**< \brief (TC0) Control C */ 75 #define REG_TC0_DBGCTRL (*(RwReg8 *)0x4000380FUL) /**< \brief (TC0) Debug Control */ 76 #define REG_TC0_SYNCBUSY (*(RoReg *)0x40003810UL) /**< \brief (TC0) Synchronization Status */ 77 #define REG_TC0_COUNT16_COUNT (*(RwReg16*)0x40003814UL) /**< \brief (TC0) COUNT16 Count */ 78 #define REG_TC0_COUNT16_CC0 (*(RwReg16*)0x4000381CUL) /**< \brief (TC0) COUNT16 Compare and Capture 0 */ 79 #define REG_TC0_COUNT16_CC1 (*(RwReg16*)0x4000381EUL) /**< \brief (TC0) COUNT16 Compare and Capture 1 */ 80 #define REG_TC0_COUNT16_CCBUF0 (*(RwReg16*)0x40003830UL) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 0 */ 81 #define REG_TC0_COUNT16_CCBUF1 (*(RwReg16*)0x40003832UL) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 1 */ 82 #define REG_TC0_COUNT32_COUNT (*(RwReg *)0x40003814UL) /**< \brief (TC0) COUNT32 Count */ 83 #define REG_TC0_COUNT32_CC0 (*(RwReg *)0x4000381CUL) /**< \brief (TC0) COUNT32 Compare and Capture 0 */ 84 #define REG_TC0_COUNT32_CC1 (*(RwReg *)0x40003820UL) /**< \brief (TC0) COUNT32 Compare and Capture 1 */ 85 #define REG_TC0_COUNT32_CCBUF0 (*(RwReg *)0x40003830UL) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 0 */ 86 #define REG_TC0_COUNT32_CCBUF1 (*(RwReg *)0x40003834UL) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 1 */ 87 #define REG_TC0_COUNT8_COUNT (*(RwReg8 *)0x40003814UL) /**< \brief (TC0) COUNT8 Count */ 88 #define REG_TC0_COUNT8_PER (*(RwReg8 *)0x4000381BUL) /**< \brief (TC0) COUNT8 Period */ 89 #define REG_TC0_COUNT8_CC0 (*(RwReg8 *)0x4000381CUL) /**< \brief (TC0) COUNT8 Compare and Capture 0 */ 90 #define REG_TC0_COUNT8_CC1 (*(RwReg8 *)0x4000381DUL) /**< \brief (TC0) COUNT8 Compare and Capture 1 */ 91 #define REG_TC0_COUNT8_PERBUF (*(RwReg8 *)0x4000382FUL) /**< \brief (TC0) COUNT8 Period Buffer */ 92 #define REG_TC0_COUNT8_CCBUF0 (*(RwReg8 *)0x40003830UL) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 0 */ 93 #define REG_TC0_COUNT8_CCBUF1 (*(RwReg8 *)0x40003831UL) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 1 */ 94 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 95 96 /* ========== Instance parameters for TC0 peripheral ========== */ 97 #define TC0_CC_NUM 2 98 #define TC0_DMAC_ID_MC_0 45 99 #define TC0_DMAC_ID_MC_1 46 100 #define TC0_DMAC_ID_MC_LSB 45 101 #define TC0_DMAC_ID_MC_MSB 46 102 #define TC0_DMAC_ID_MC_SIZE 2 103 #define TC0_DMAC_ID_OVF 44 // Indexes of DMA Overflow trigger 104 #define TC0_EXT 0 // Coding of implemented extended features (keep 0 value) 105 #define TC0_GCLK_ID 9 // Index of Generic Clock 106 #define TC0_MASTER_SLAVE_MODE 1 // TC type 0 : NA, 1 : Master, 2 : Slave 107 #define TC0_OW_NUM 2 // Number of Output Waveforms 108 109 #endif /* _SAME54_TC0_INSTANCE_ */ 110
