1 /** 2 * \file 3 * 4 * \brief Instance description for PICOP 5 * 6 * Copyright (c) 2015 Atmel Corporation. All rights reserved. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions are met: 14 * 15 * 1. Redistributions of source code must retain the above copyright notice, 16 * this list of conditions and the following disclaimer. 17 * 18 * 2. Redistributions in binary form must reproduce the above copyright notice, 19 * this list of conditions and the following disclaimer in the documentation 20 * and/or other materials provided with the distribution. 21 * 22 * 3. The name of Atmel may not be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * 4. This software may only be redistributed and used in connection with an 26 * Atmel microcontroller product. 27 * 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 * 40 * \asf_license_stop 41 * 42 */ 43 44 #ifndef _SAME54_PICOP_INSTANCE_ 45 #define _SAME54_PICOP_INSTANCE_ 46 47 /* ========== Register definition for PICOP peripheral ========== */ 48 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 49 #define REG_PICOP_ID0 (0x4100E000U) /**< \brief (PICOP) ID 0 */ 50 #define REG_PICOP_ID1 (0x4100E004U) /**< \brief (PICOP) ID 1 */ 51 #define REG_PICOP_ID2 (0x4100E008U) /**< \brief (PICOP) ID 2 */ 52 #define REG_PICOP_ID3 (0x4100E00CU) /**< \brief (PICOP) ID 3 */ 53 #define REG_PICOP_ID4 (0x4100E010U) /**< \brief (PICOP) ID 4 */ 54 #define REG_PICOP_ID5 (0x4100E014U) /**< \brief (PICOP) ID 5 */ 55 #define REG_PICOP_ID6 (0x4100E018U) /**< \brief (PICOP) ID 6 */ 56 #define REG_PICOP_ID7 (0x4100E01CU) /**< \brief (PICOP) ID 7 */ 57 #define REG_PICOP_CONFIG (0x4100E020U) /**< \brief (PICOP) Configuration */ 58 #define REG_PICOP_CTRL (0x4100E024U) /**< \brief (PICOP) Control */ 59 #define REG_PICOP_CMD (0x4100E028U) /**< \brief (PICOP) Command */ 60 #define REG_PICOP_PC (0x4100E02CU) /**< \brief (PICOP) Program Counter */ 61 #define REG_PICOP_HF (0x4100E030U) /**< \brief (PICOP) Host Flags */ 62 #define REG_PICOP_HFCTRL (0x4100E034U) /**< \brief (PICOP) Host Flag Control */ 63 #define REG_PICOP_HFSETCLR0 (0x4100E038U) /**< \brief (PICOP) Host Flags Set/Clr */ 64 #define REG_PICOP_HFSETCLR1 (0x4100E03CU) /**< \brief (PICOP) Host Flags Set/Clr */ 65 #define REG_PICOP_OCDCONFIG (0x4100E050U) /**< \brief (PICOP) OCD Configuration */ 66 #define REG_PICOP_OCDCONTROL (0x4100E054U) /**< \brief (PICOP) OCD Control */ 67 #define REG_PICOP_OCDSTATUS (0x4100E058U) /**< \brief (PICOP) OCD Status and Command */ 68 #define REG_PICOP_OCDPC (0x4100E05CU) /**< \brief (PICOP) ODC Program Counter */ 69 #define REG_PICOP_OCDFEAT (0x4100E060U) /**< \brief (PICOP) OCD Features */ 70 #define REG_PICOP_OCDCCNT (0x4100E068U) /**< \brief (PICOP) OCD Cycle Counter */ 71 #define REG_PICOP_OCDBPGEN0 (0x4100E070U) /**< \brief (PICOP) OCD Breakpoint Generator 0 */ 72 #define REG_PICOP_OCDBPGEN1 (0x4100E074U) /**< \brief (PICOP) OCD Breakpoint Generator 1 */ 73 #define REG_PICOP_OCDBPGEN2 (0x4100E078U) /**< \brief (PICOP) OCD Breakpoint Generator 2 */ 74 #define REG_PICOP_OCDBPGEN3 (0x4100E07CU) /**< \brief (PICOP) OCD Breakpoint Generator 3 */ 75 #define REG_PICOP_R3R0 (0x4100E080U) /**< \brief (PICOP) R3 to 0 */ 76 #define REG_PICOP_R7R4 (0x4100E084U) /**< \brief (PICOP) R7 to 4 */ 77 #define REG_PICOP_R11R8 (0x4100E088U) /**< \brief (PICOP) R11 to 8 */ 78 #define REG_PICOP_R15R12 (0x4100E08CU) /**< \brief (PICOP) R15 to 12 */ 79 #define REG_PICOP_R19R16 (0x4100E090U) /**< \brief (PICOP) R19 to 16 */ 80 #define REG_PICOP_R23R20 (0x4100E094U) /**< \brief (PICOP) R23 to 20 */ 81 #define REG_PICOP_R27R24 (0x4100E098U) /**< \brief (PICOP) R27 to 24: XH, XL, R25, R24 */ 82 #define REG_PICOP_R31R28 (0x4100E09CU) /**< \brief (PICOP) R31 to 28: ZH, ZL, YH, YL */ 83 #define REG_PICOP_S1S0 (0x4100E0A0U) /**< \brief (PICOP) System Regs 1 to 0: SR */ 84 #define REG_PICOP_S3S2 (0x4100E0A4U) /**< \brief (PICOP) System Regs 3 to 2: CTRL */ 85 #define REG_PICOP_S5S4 (0x4100E0A8U) /**< \brief (PICOP) System Regs 5 to 4: SREG, CCR */ 86 #define REG_PICOP_S11S10 (0x4100E0B4U) /**< \brief (PICOP) System Regs 11 to 10: Immediate */ 87 #define REG_PICOP_LINK (0x4100E0B8U) /**< \brief (PICOP) Link */ 88 #define REG_PICOP_SP (0x4100E0BCU) /**< \brief (PICOP) Stack Pointer */ 89 #define REG_PICOP_MMUFLASH (0x4100E100U) /**< \brief (PICOP) MMU mapping for flash */ 90 #define REG_PICOP_MMU0 (0x4100E118U) /**< \brief (PICOP) MMU mapping user 0 */ 91 #define REG_PICOP_MMU1 (0x4100E11CU) /**< \brief (PICOP) MMU mapping user 1 */ 92 #define REG_PICOP_MMUCTRL (0x4100E120U) /**< \brief (PICOP) MMU Control */ 93 #define REG_PICOP_ICACHE (0x4100E180U) /**< \brief (PICOP) Instruction Cache Control */ 94 #define REG_PICOP_ICACHELRU (0x4100E184U) /**< \brief (PICOP) Instruction Cache LRU */ 95 #define REG_PICOP_QOSCTRL (0x4100E200U) /**< \brief (PICOP) QOS Control */ 96 #else 97 #define REG_PICOP_ID0 (*(RwReg *)0x4100E000U) /**< \brief (PICOP) ID 0 */ 98 #define REG_PICOP_ID1 (*(RwReg *)0x4100E004U) /**< \brief (PICOP) ID 1 */ 99 #define REG_PICOP_ID2 (*(RwReg *)0x4100E008U) /**< \brief (PICOP) ID 2 */ 100 #define REG_PICOP_ID3 (*(RwReg *)0x4100E00CU) /**< \brief (PICOP) ID 3 */ 101 #define REG_PICOP_ID4 (*(RwReg *)0x4100E010U) /**< \brief (PICOP) ID 4 */ 102 #define REG_PICOP_ID5 (*(RwReg *)0x4100E014U) /**< \brief (PICOP) ID 5 */ 103 #define REG_PICOP_ID6 (*(RwReg *)0x4100E018U) /**< \brief (PICOP) ID 6 */ 104 #define REG_PICOP_ID7 (*(RwReg *)0x4100E01CU) /**< \brief (PICOP) ID 7 */ 105 #define REG_PICOP_CONFIG (*(RwReg *)0x4100E020U) /**< \brief (PICOP) Configuration */ 106 #define REG_PICOP_CTRL (*(RwReg *)0x4100E024U) /**< \brief (PICOP) Control */ 107 #define REG_PICOP_CMD (*(RwReg *)0x4100E028U) /**< \brief (PICOP) Command */ 108 #define REG_PICOP_PC (*(RwReg *)0x4100E02CU) /**< \brief (PICOP) Program Counter */ 109 #define REG_PICOP_HF (*(RwReg *)0x4100E030U) /**< \brief (PICOP) Host Flags */ 110 #define REG_PICOP_HFCTRL (*(RwReg *)0x4100E034U) /**< \brief (PICOP) Host Flag Control */ 111 #define REG_PICOP_HFSETCLR0 (*(RwReg *)0x4100E038U) /**< \brief (PICOP) Host Flags Set/Clr */ 112 #define REG_PICOP_HFSETCLR1 (*(RwReg *)0x4100E03CU) /**< \brief (PICOP) Host Flags Set/Clr */ 113 #define REG_PICOP_OCDCONFIG (*(RwReg *)0x4100E050U) /**< \brief (PICOP) OCD Configuration */ 114 #define REG_PICOP_OCDCONTROL (*(RwReg *)0x4100E054U) /**< \brief (PICOP) OCD Control */ 115 #define REG_PICOP_OCDSTATUS (*(RwReg *)0x4100E058U) /**< \brief (PICOP) OCD Status and Command */ 116 #define REG_PICOP_OCDPC (*(RwReg *)0x4100E05CU) /**< \brief (PICOP) ODC Program Counter */ 117 #define REG_PICOP_OCDFEAT (*(RwReg *)0x4100E060U) /**< \brief (PICOP) OCD Features */ 118 #define REG_PICOP_OCDCCNT (*(RwReg *)0x4100E068U) /**< \brief (PICOP) OCD Cycle Counter */ 119 #define REG_PICOP_OCDBPGEN0 (*(RwReg *)0x4100E070U) /**< \brief (PICOP) OCD Breakpoint Generator 0 */ 120 #define REG_PICOP_OCDBPGEN1 (*(RwReg *)0x4100E074U) /**< \brief (PICOP) OCD Breakpoint Generator 1 */ 121 #define REG_PICOP_OCDBPGEN2 (*(RwReg *)0x4100E078U) /**< \brief (PICOP) OCD Breakpoint Generator 2 */ 122 #define REG_PICOP_OCDBPGEN3 (*(RwReg *)0x4100E07CU) /**< \brief (PICOP) OCD Breakpoint Generator 3 */ 123 #define REG_PICOP_R3R0 (*(RwReg *)0x4100E080U) /**< \brief (PICOP) R3 to 0 */ 124 #define REG_PICOP_R7R4 (*(RwReg *)0x4100E084U) /**< \brief (PICOP) R7 to 4 */ 125 #define REG_PICOP_R11R8 (*(RwReg *)0x4100E088U) /**< \brief (PICOP) R11 to 8 */ 126 #define REG_PICOP_R15R12 (*(RwReg *)0x4100E08CU) /**< \brief (PICOP) R15 to 12 */ 127 #define REG_PICOP_R19R16 (*(RwReg *)0x4100E090U) /**< \brief (PICOP) R19 to 16 */ 128 #define REG_PICOP_R23R20 (*(RwReg *)0x4100E094U) /**< \brief (PICOP) R23 to 20 */ 129 #define REG_PICOP_R27R24 (*(RwReg *)0x4100E098U) /**< \brief (PICOP) R27 to 24: XH, XL, R25, R24 */ 130 #define REG_PICOP_R31R28 (*(RwReg *)0x4100E09CU) /**< \brief (PICOP) R31 to 28: ZH, ZL, YH, YL */ 131 #define REG_PICOP_S1S0 (*(RwReg *)0x4100E0A0U) /**< \brief (PICOP) System Regs 1 to 0: SR */ 132 #define REG_PICOP_S3S2 (*(RwReg *)0x4100E0A4U) /**< \brief (PICOP) System Regs 3 to 2: CTRL */ 133 #define REG_PICOP_S5S4 (*(RwReg *)0x4100E0A8U) /**< \brief (PICOP) System Regs 5 to 4: SREG, CCR */ 134 #define REG_PICOP_S11S10 (*(RwReg *)0x4100E0B4U) /**< \brief (PICOP) System Regs 11 to 10: Immediate */ 135 #define REG_PICOP_LINK (*(RwReg *)0x4100E0B8U) /**< \brief (PICOP) Link */ 136 #define REG_PICOP_SP (*(RwReg *)0x4100E0BCU) /**< \brief (PICOP) Stack Pointer */ 137 #define REG_PICOP_MMUFLASH (*(RwReg *)0x4100E100U) /**< \brief (PICOP) MMU mapping for flash */ 138 #define REG_PICOP_MMU0 (*(RwReg *)0x4100E118U) /**< \brief (PICOP) MMU mapping user 0 */ 139 #define REG_PICOP_MMU1 (*(RwReg *)0x4100E11CU) /**< \brief (PICOP) MMU mapping user 1 */ 140 #define REG_PICOP_MMUCTRL (*(RwReg *)0x4100E120U) /**< \brief (PICOP) MMU Control */ 141 #define REG_PICOP_ICACHE (*(RwReg *)0x4100E180U) /**< \brief (PICOP) Instruction Cache Control */ 142 #define REG_PICOP_ICACHELRU (*(RwReg *)0x4100E184U) /**< \brief (PICOP) Instruction Cache LRU */ 143 #define REG_PICOP_QOSCTRL (*(RwReg *)0x4100E200U) /**< \brief (PICOP) QOS Control */ 144 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 145 146 147 #endif /* _SAME54_PICOP_INSTANCE_ */ 148
