1 /** 2 * \file 3 * 4 * \brief Component description for RAMECC 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAME54_RAMECC_COMPONENT_ 31 #define _SAME54_RAMECC_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR RAMECC */ 35 /* ========================================================================== */ 36 /** \addtogroup SAME54_RAMECC RAM ECC */ 37 /*@{*/ 38 39 #define RAMECC_U2268 40 #define REV_RAMECC 0x100 41 42 /* -------- RAMECC_INTENCLR : (RAMECC Offset: 0x0) (R/W 8) Interrupt Enable Clear -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint8_t SINGLEE:1; /*!< bit: 0 Single Bit ECC Error Interrupt Enable Clear */ 47 uint8_t DUALE:1; /*!< bit: 1 Dual Bit ECC Error Interrupt Enable Clear */ 48 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 49 } bit; /*!< Structure used for bit access */ 50 uint8_t reg; /*!< Type used for register access */ 51 } RAMECC_INTENCLR_Type; 52 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 53 54 #define RAMECC_INTENCLR_OFFSET 0x0 /**< \brief (RAMECC_INTENCLR offset) Interrupt Enable Clear */ 55 #define RAMECC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (RAMECC_INTENCLR reset_value) Interrupt Enable Clear */ 56 57 #define RAMECC_INTENCLR_SINGLEE_Pos 0 /**< \brief (RAMECC_INTENCLR) Single Bit ECC Error Interrupt Enable Clear */ 58 #define RAMECC_INTENCLR_SINGLEE (_U_(0x1) << RAMECC_INTENCLR_SINGLEE_Pos) 59 #define RAMECC_INTENCLR_DUALE_Pos 1 /**< \brief (RAMECC_INTENCLR) Dual Bit ECC Error Interrupt Enable Clear */ 60 #define RAMECC_INTENCLR_DUALE (_U_(0x1) << RAMECC_INTENCLR_DUALE_Pos) 61 #define RAMECC_INTENCLR_MASK _U_(0x03) /**< \brief (RAMECC_INTENCLR) MASK Register */ 62 63 /* -------- RAMECC_INTENSET : (RAMECC Offset: 0x1) (R/W 8) Interrupt Enable Set -------- */ 64 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 65 typedef union { 66 struct { 67 uint8_t SINGLEE:1; /*!< bit: 0 Single Bit ECC Error Interrupt Enable Set */ 68 uint8_t DUALE:1; /*!< bit: 1 Dual Bit ECC Error Interrupt Enable Set */ 69 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 70 } bit; /*!< Structure used for bit access */ 71 uint8_t reg; /*!< Type used for register access */ 72 } RAMECC_INTENSET_Type; 73 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 74 75 #define RAMECC_INTENSET_OFFSET 0x1 /**< \brief (RAMECC_INTENSET offset) Interrupt Enable Set */ 76 #define RAMECC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (RAMECC_INTENSET reset_value) Interrupt Enable Set */ 77 78 #define RAMECC_INTENSET_SINGLEE_Pos 0 /**< \brief (RAMECC_INTENSET) Single Bit ECC Error Interrupt Enable Set */ 79 #define RAMECC_INTENSET_SINGLEE (_U_(0x1) << RAMECC_INTENSET_SINGLEE_Pos) 80 #define RAMECC_INTENSET_DUALE_Pos 1 /**< \brief (RAMECC_INTENSET) Dual Bit ECC Error Interrupt Enable Set */ 81 #define RAMECC_INTENSET_DUALE (_U_(0x1) << RAMECC_INTENSET_DUALE_Pos) 82 #define RAMECC_INTENSET_MASK _U_(0x03) /**< \brief (RAMECC_INTENSET) MASK Register */ 83 84 /* -------- RAMECC_INTFLAG : (RAMECC Offset: 0x2) (R/W 8) Interrupt Flag -------- */ 85 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 86 typedef union { // __I to avoid read-modify-write on write-to-clear register 87 struct { 88 __I uint8_t SINGLEE:1; /*!< bit: 0 Single Bit ECC Error Interrupt */ 89 __I uint8_t DUALE:1; /*!< bit: 1 Dual Bit ECC Error Interrupt */ 90 __I uint8_t Reserved1:6; /*!< bit: 2.. 7 Reserved */ 91 } bit; /*!< Structure used for bit access */ 92 uint8_t reg; /*!< Type used for register access */ 93 } RAMECC_INTFLAG_Type; 94 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 95 96 #define RAMECC_INTFLAG_OFFSET 0x2 /**< \brief (RAMECC_INTFLAG offset) Interrupt Flag */ 97 #define RAMECC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (RAMECC_INTFLAG reset_value) Interrupt Flag */ 98 99 #define RAMECC_INTFLAG_SINGLEE_Pos 0 /**< \brief (RAMECC_INTFLAG) Single Bit ECC Error Interrupt */ 100 #define RAMECC_INTFLAG_SINGLEE (_U_(0x1) << RAMECC_INTFLAG_SINGLEE_Pos) 101 #define RAMECC_INTFLAG_DUALE_Pos 1 /**< \brief (RAMECC_INTFLAG) Dual Bit ECC Error Interrupt */ 102 #define RAMECC_INTFLAG_DUALE (_U_(0x1) << RAMECC_INTFLAG_DUALE_Pos) 103 #define RAMECC_INTFLAG_MASK _U_(0x03) /**< \brief (RAMECC_INTFLAG) MASK Register */ 104 105 /* -------- RAMECC_STATUS : (RAMECC Offset: 0x3) (R/ 8) Status -------- */ 106 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 107 typedef union { 108 struct { 109 uint8_t ECCDIS:1; /*!< bit: 0 ECC Disable */ 110 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 111 } bit; /*!< Structure used for bit access */ 112 uint8_t reg; /*!< Type used for register access */ 113 } RAMECC_STATUS_Type; 114 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 115 116 #define RAMECC_STATUS_OFFSET 0x3 /**< \brief (RAMECC_STATUS offset) Status */ 117 #define RAMECC_STATUS_RESETVALUE _U_(0x00) /**< \brief (RAMECC_STATUS reset_value) Status */ 118 119 #define RAMECC_STATUS_ECCDIS_Pos 0 /**< \brief (RAMECC_STATUS) ECC Disable */ 120 #define RAMECC_STATUS_ECCDIS (_U_(0x1) << RAMECC_STATUS_ECCDIS_Pos) 121 #define RAMECC_STATUS_MASK _U_(0x01) /**< \brief (RAMECC_STATUS) MASK Register */ 122 123 /* -------- RAMECC_ERRADDR : (RAMECC Offset: 0x4) (R/ 32) Error Address -------- */ 124 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 125 typedef union { 126 struct { 127 uint32_t ERRADDR:17; /*!< bit: 0..16 Error Address */ 128 uint32_t :15; /*!< bit: 17..31 Reserved */ 129 } bit; /*!< Structure used for bit access */ 130 uint32_t reg; /*!< Type used for register access */ 131 } RAMECC_ERRADDR_Type; 132 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 133 134 #define RAMECC_ERRADDR_OFFSET 0x4 /**< \brief (RAMECC_ERRADDR offset) Error Address */ 135 #define RAMECC_ERRADDR_RESETVALUE _U_(0x00000000) /**< \brief (RAMECC_ERRADDR reset_value) Error Address */ 136 137 #define RAMECC_ERRADDR_ERRADDR_Pos 0 /**< \brief (RAMECC_ERRADDR) Error Address */ 138 #define RAMECC_ERRADDR_ERRADDR_Msk (_U_(0x1FFFF) << RAMECC_ERRADDR_ERRADDR_Pos) 139 #define RAMECC_ERRADDR_ERRADDR(value) (RAMECC_ERRADDR_ERRADDR_Msk & ((value) << RAMECC_ERRADDR_ERRADDR_Pos)) 140 #define RAMECC_ERRADDR_MASK _U_(0x0001FFFF) /**< \brief (RAMECC_ERRADDR) MASK Register */ 141 142 /* -------- RAMECC_DBGCTRL : (RAMECC Offset: 0xF) (R/W 8) Debug Control -------- */ 143 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 144 typedef union { 145 struct { 146 uint8_t ECCDIS:1; /*!< bit: 0 ECC Disable */ 147 uint8_t ECCELOG:1; /*!< bit: 1 ECC Error Log */ 148 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 149 } bit; /*!< Structure used for bit access */ 150 uint8_t reg; /*!< Type used for register access */ 151 } RAMECC_DBGCTRL_Type; 152 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 153 154 #define RAMECC_DBGCTRL_OFFSET 0xF /**< \brief (RAMECC_DBGCTRL offset) Debug Control */ 155 #define RAMECC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (RAMECC_DBGCTRL reset_value) Debug Control */ 156 157 #define RAMECC_DBGCTRL_ECCDIS_Pos 0 /**< \brief (RAMECC_DBGCTRL) ECC Disable */ 158 #define RAMECC_DBGCTRL_ECCDIS (_U_(0x1) << RAMECC_DBGCTRL_ECCDIS_Pos) 159 #define RAMECC_DBGCTRL_ECCELOG_Pos 1 /**< \brief (RAMECC_DBGCTRL) ECC Error Log */ 160 #define RAMECC_DBGCTRL_ECCELOG (_U_(0x1) << RAMECC_DBGCTRL_ECCELOG_Pos) 161 #define RAMECC_DBGCTRL_MASK _U_(0x03) /**< \brief (RAMECC_DBGCTRL) MASK Register */ 162 163 /** \brief RAMECC hardware registers */ 164 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 165 typedef struct { 166 __IO RAMECC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0 (R/W 8) Interrupt Enable Clear */ 167 __IO RAMECC_INTENSET_Type INTENSET; /**< \brief Offset: 0x1 (R/W 8) Interrupt Enable Set */ 168 __IO RAMECC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2 (R/W 8) Interrupt Flag */ 169 __I RAMECC_STATUS_Type STATUS; /**< \brief Offset: 0x3 (R/ 8) Status */ 170 __I RAMECC_ERRADDR_Type ERRADDR; /**< \brief Offset: 0x4 (R/ 32) Error Address */ 171 RoReg8 Reserved1[0x7]; 172 __IO RAMECC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0xF (R/W 8) Debug Control */ 173 } Ramecc; 174 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 175 176 /*@}*/ 177 178 #endif /* _SAME54_RAMECC_COMPONENT_ */ 179
