1 /** 2 * \file 3 * 4 * \brief Component description for PCC 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAME54_PCC_COMPONENT_ 31 #define _SAME54_PCC_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR PCC */ 35 /* ========================================================================== */ 36 /** \addtogroup SAME54_PCC Parallel Capture Controller */ 37 /*@{*/ 38 39 #define PCC_U2017 40 #define REV_PCC 0x110 41 42 /* -------- PCC_MR : (PCC Offset: 0x00) (R/W 32) Mode Register -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint32_t PCEN:1; /*!< bit: 0 Parallel Capture Enable */ 47 uint32_t :3; /*!< bit: 1.. 3 Reserved */ 48 uint32_t DSIZE:2; /*!< bit: 4.. 5 Data size */ 49 uint32_t :2; /*!< bit: 6.. 7 Reserved */ 50 uint32_t SCALE:1; /*!< bit: 8 Scale data */ 51 uint32_t ALWYS:1; /*!< bit: 9 Always Sampling */ 52 uint32_t HALFS:1; /*!< bit: 10 Half Sampling */ 53 uint32_t FRSTS:1; /*!< bit: 11 First sample */ 54 uint32_t :4; /*!< bit: 12..15 Reserved */ 55 uint32_t ISIZE:3; /*!< bit: 16..18 Input Data Size */ 56 uint32_t :11; /*!< bit: 19..29 Reserved */ 57 uint32_t CID:2; /*!< bit: 30..31 Clear If Disabled */ 58 } bit; /*!< Structure used for bit access */ 59 uint32_t reg; /*!< Type used for register access */ 60 } PCC_MR_Type; 61 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 62 63 #define PCC_MR_OFFSET 0x00 /**< \brief (PCC_MR offset) Mode Register */ 64 #define PCC_MR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_MR reset_value) Mode Register */ 65 66 #define PCC_MR_PCEN_Pos 0 /**< \brief (PCC_MR) Parallel Capture Enable */ 67 #define PCC_MR_PCEN (_U_(0x1) << PCC_MR_PCEN_Pos) 68 #define PCC_MR_DSIZE_Pos 4 /**< \brief (PCC_MR) Data size */ 69 #define PCC_MR_DSIZE_Msk (_U_(0x3) << PCC_MR_DSIZE_Pos) 70 #define PCC_MR_DSIZE(value) (PCC_MR_DSIZE_Msk & ((value) << PCC_MR_DSIZE_Pos)) 71 #define PCC_MR_SCALE_Pos 8 /**< \brief (PCC_MR) Scale data */ 72 #define PCC_MR_SCALE (_U_(0x1) << PCC_MR_SCALE_Pos) 73 #define PCC_MR_ALWYS_Pos 9 /**< \brief (PCC_MR) Always Sampling */ 74 #define PCC_MR_ALWYS (_U_(0x1) << PCC_MR_ALWYS_Pos) 75 #define PCC_MR_HALFS_Pos 10 /**< \brief (PCC_MR) Half Sampling */ 76 #define PCC_MR_HALFS (_U_(0x1) << PCC_MR_HALFS_Pos) 77 #define PCC_MR_FRSTS_Pos 11 /**< \brief (PCC_MR) First sample */ 78 #define PCC_MR_FRSTS (_U_(0x1) << PCC_MR_FRSTS_Pos) 79 #define PCC_MR_ISIZE_Pos 16 /**< \brief (PCC_MR) Input Data Size */ 80 #define PCC_MR_ISIZE_Msk (_U_(0x7) << PCC_MR_ISIZE_Pos) 81 #define PCC_MR_ISIZE(value) (PCC_MR_ISIZE_Msk & ((value) << PCC_MR_ISIZE_Pos)) 82 #define PCC_MR_CID_Pos 30 /**< \brief (PCC_MR) Clear If Disabled */ 83 #define PCC_MR_CID_Msk (_U_(0x3) << PCC_MR_CID_Pos) 84 #define PCC_MR_CID(value) (PCC_MR_CID_Msk & ((value) << PCC_MR_CID_Pos)) 85 #define PCC_MR_MASK _U_(0xC0070F31) /**< \brief (PCC_MR) MASK Register */ 86 87 /* -------- PCC_IER : (PCC Offset: 0x04) ( /W 32) Interrupt Enable Register -------- */ 88 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 89 typedef union { 90 struct { 91 uint32_t DRDY:1; /*!< bit: 0 Data Ready Interrupt Enable */ 92 uint32_t OVRE:1; /*!< bit: 1 Overrun Error Interrupt Enable */ 93 uint32_t :30; /*!< bit: 2..31 Reserved */ 94 } bit; /*!< Structure used for bit access */ 95 uint32_t reg; /*!< Type used for register access */ 96 } PCC_IER_Type; 97 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 98 99 #define PCC_IER_OFFSET 0x04 /**< \brief (PCC_IER offset) Interrupt Enable Register */ 100 #define PCC_IER_RESETVALUE _U_(0x00000000) /**< \brief (PCC_IER reset_value) Interrupt Enable Register */ 101 102 #define PCC_IER_DRDY_Pos 0 /**< \brief (PCC_IER) Data Ready Interrupt Enable */ 103 #define PCC_IER_DRDY (_U_(0x1) << PCC_IER_DRDY_Pos) 104 #define PCC_IER_OVRE_Pos 1 /**< \brief (PCC_IER) Overrun Error Interrupt Enable */ 105 #define PCC_IER_OVRE (_U_(0x1) << PCC_IER_OVRE_Pos) 106 #define PCC_IER_MASK _U_(0x00000003) /**< \brief (PCC_IER) MASK Register */ 107 108 /* -------- PCC_IDR : (PCC Offset: 0x08) ( /W 32) Interrupt Disable Register -------- */ 109 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 110 typedef union { 111 struct { 112 uint32_t DRDY:1; /*!< bit: 0 Data Ready Interrupt Disable */ 113 uint32_t OVRE:1; /*!< bit: 1 Overrun Error Interrupt Disable */ 114 uint32_t :30; /*!< bit: 2..31 Reserved */ 115 } bit; /*!< Structure used for bit access */ 116 uint32_t reg; /*!< Type used for register access */ 117 } PCC_IDR_Type; 118 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 119 120 #define PCC_IDR_OFFSET 0x08 /**< \brief (PCC_IDR offset) Interrupt Disable Register */ 121 #define PCC_IDR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_IDR reset_value) Interrupt Disable Register */ 122 123 #define PCC_IDR_DRDY_Pos 0 /**< \brief (PCC_IDR) Data Ready Interrupt Disable */ 124 #define PCC_IDR_DRDY (_U_(0x1) << PCC_IDR_DRDY_Pos) 125 #define PCC_IDR_OVRE_Pos 1 /**< \brief (PCC_IDR) Overrun Error Interrupt Disable */ 126 #define PCC_IDR_OVRE (_U_(0x1) << PCC_IDR_OVRE_Pos) 127 #define PCC_IDR_MASK _U_(0x00000003) /**< \brief (PCC_IDR) MASK Register */ 128 129 /* -------- PCC_IMR : (PCC Offset: 0x0C) (R/ 32) Interrupt Mask Register -------- */ 130 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 131 typedef union { 132 struct { 133 uint32_t DRDY:1; /*!< bit: 0 Data Ready Interrupt Mask */ 134 uint32_t OVRE:1; /*!< bit: 1 Overrun Error Interrupt Mask */ 135 uint32_t :30; /*!< bit: 2..31 Reserved */ 136 } bit; /*!< Structure used for bit access */ 137 uint32_t reg; /*!< Type used for register access */ 138 } PCC_IMR_Type; 139 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 140 141 #define PCC_IMR_OFFSET 0x0C /**< \brief (PCC_IMR offset) Interrupt Mask Register */ 142 #define PCC_IMR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_IMR reset_value) Interrupt Mask Register */ 143 144 #define PCC_IMR_DRDY_Pos 0 /**< \brief (PCC_IMR) Data Ready Interrupt Mask */ 145 #define PCC_IMR_DRDY (_U_(0x1) << PCC_IMR_DRDY_Pos) 146 #define PCC_IMR_OVRE_Pos 1 /**< \brief (PCC_IMR) Overrun Error Interrupt Mask */ 147 #define PCC_IMR_OVRE (_U_(0x1) << PCC_IMR_OVRE_Pos) 148 #define PCC_IMR_MASK _U_(0x00000003) /**< \brief (PCC_IMR) MASK Register */ 149 150 /* -------- PCC_ISR : (PCC Offset: 0x10) (R/ 32) Interrupt Status Register -------- */ 151 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 152 typedef union { 153 struct { 154 uint32_t DRDY:1; /*!< bit: 0 Data Ready Interrupt Status */ 155 uint32_t OVRE:1; /*!< bit: 1 Overrun Error Interrupt Status */ 156 uint32_t :30; /*!< bit: 2..31 Reserved */ 157 } bit; /*!< Structure used for bit access */ 158 uint32_t reg; /*!< Type used for register access */ 159 } PCC_ISR_Type; 160 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 161 162 #define PCC_ISR_OFFSET 0x10 /**< \brief (PCC_ISR offset) Interrupt Status Register */ 163 #define PCC_ISR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_ISR reset_value) Interrupt Status Register */ 164 165 #define PCC_ISR_DRDY_Pos 0 /**< \brief (PCC_ISR) Data Ready Interrupt Status */ 166 #define PCC_ISR_DRDY (_U_(0x1) << PCC_ISR_DRDY_Pos) 167 #define PCC_ISR_OVRE_Pos 1 /**< \brief (PCC_ISR) Overrun Error Interrupt Status */ 168 #define PCC_ISR_OVRE (_U_(0x1) << PCC_ISR_OVRE_Pos) 169 #define PCC_ISR_MASK _U_(0x00000003) /**< \brief (PCC_ISR) MASK Register */ 170 171 /* -------- PCC_RHR : (PCC Offset: 0x14) (R/ 32) Reception Holding Register -------- */ 172 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 173 typedef union { 174 struct { 175 uint32_t RDATA:32; /*!< bit: 0..31 Reception Data */ 176 } bit; /*!< Structure used for bit access */ 177 uint32_t reg; /*!< Type used for register access */ 178 } PCC_RHR_Type; 179 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 180 181 #define PCC_RHR_OFFSET 0x14 /**< \brief (PCC_RHR offset) Reception Holding Register */ 182 #define PCC_RHR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_RHR reset_value) Reception Holding Register */ 183 184 #define PCC_RHR_RDATA_Pos 0 /**< \brief (PCC_RHR) Reception Data */ 185 #define PCC_RHR_RDATA_Msk (_U_(0xFFFFFFFF) << PCC_RHR_RDATA_Pos) 186 #define PCC_RHR_RDATA(value) (PCC_RHR_RDATA_Msk & ((value) << PCC_RHR_RDATA_Pos)) 187 #define PCC_RHR_MASK _U_(0xFFFFFFFF) /**< \brief (PCC_RHR) MASK Register */ 188 189 /* -------- PCC_WPMR : (PCC Offset: 0xE0) (R/W 32) Write Protection Mode Register -------- */ 190 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 191 typedef union { 192 struct { 193 uint32_t WPEN:1; /*!< bit: 0 Write Protection Enable */ 194 uint32_t :7; /*!< bit: 1.. 7 Reserved */ 195 uint32_t WPKEY:24; /*!< bit: 8..31 Write Protection Key */ 196 } bit; /*!< Structure used for bit access */ 197 uint32_t reg; /*!< Type used for register access */ 198 } PCC_WPMR_Type; 199 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 200 201 #define PCC_WPMR_OFFSET 0xE0 /**< \brief (PCC_WPMR offset) Write Protection Mode Register */ 202 #define PCC_WPMR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_WPMR reset_value) Write Protection Mode Register */ 203 204 #define PCC_WPMR_WPEN_Pos 0 /**< \brief (PCC_WPMR) Write Protection Enable */ 205 #define PCC_WPMR_WPEN (_U_(0x1) << PCC_WPMR_WPEN_Pos) 206 #define PCC_WPMR_WPKEY_Pos 8 /**< \brief (PCC_WPMR) Write Protection Key */ 207 #define PCC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << PCC_WPMR_WPKEY_Pos) 208 #define PCC_WPMR_WPKEY(value) (PCC_WPMR_WPKEY_Msk & ((value) << PCC_WPMR_WPKEY_Pos)) 209 #define PCC_WPMR_MASK _U_(0xFFFFFF01) /**< \brief (PCC_WPMR) MASK Register */ 210 211 /* -------- PCC_WPSR : (PCC Offset: 0xE4) (R/ 32) Write Protection Status Register -------- */ 212 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 213 typedef union { 214 struct { 215 uint32_t WPVS:1; /*!< bit: 0 Write Protection Violation Source */ 216 uint32_t :7; /*!< bit: 1.. 7 Reserved */ 217 uint32_t WPVSRC:16; /*!< bit: 8..23 Write Protection Violation Status */ 218 uint32_t :8; /*!< bit: 24..31 Reserved */ 219 } bit; /*!< Structure used for bit access */ 220 uint32_t reg; /*!< Type used for register access */ 221 } PCC_WPSR_Type; 222 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 223 224 #define PCC_WPSR_OFFSET 0xE4 /**< \brief (PCC_WPSR offset) Write Protection Status Register */ 225 #define PCC_WPSR_RESETVALUE _U_(0x00000000) /**< \brief (PCC_WPSR reset_value) Write Protection Status Register */ 226 227 #define PCC_WPSR_WPVS_Pos 0 /**< \brief (PCC_WPSR) Write Protection Violation Source */ 228 #define PCC_WPSR_WPVS (_U_(0x1) << PCC_WPSR_WPVS_Pos) 229 #define PCC_WPSR_WPVSRC_Pos 8 /**< \brief (PCC_WPSR) Write Protection Violation Status */ 230 #define PCC_WPSR_WPVSRC_Msk (_U_(0xFFFF) << PCC_WPSR_WPVSRC_Pos) 231 #define PCC_WPSR_WPVSRC(value) (PCC_WPSR_WPVSRC_Msk & ((value) << PCC_WPSR_WPVSRC_Pos)) 232 #define PCC_WPSR_MASK _U_(0x00FFFF01) /**< \brief (PCC_WPSR) MASK Register */ 233 234 /** \brief PCC hardware registers */ 235 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 236 typedef struct { 237 __IO PCC_MR_Type MR; /**< \brief Offset: 0x00 (R/W 32) Mode Register */ 238 __O PCC_IER_Type IER; /**< \brief Offset: 0x04 ( /W 32) Interrupt Enable Register */ 239 __O PCC_IDR_Type IDR; /**< \brief Offset: 0x08 ( /W 32) Interrupt Disable Register */ 240 __I PCC_IMR_Type IMR; /**< \brief Offset: 0x0C (R/ 32) Interrupt Mask Register */ 241 __I PCC_ISR_Type ISR; /**< \brief Offset: 0x10 (R/ 32) Interrupt Status Register */ 242 __I PCC_RHR_Type RHR; /**< \brief Offset: 0x14 (R/ 32) Reception Holding Register */ 243 RoReg8 Reserved1[0xC8]; 244 __IO PCC_WPMR_Type WPMR; /**< \brief Offset: 0xE0 (R/W 32) Write Protection Mode Register */ 245 __I PCC_WPSR_Type WPSR; /**< \brief Offset: 0xE4 (R/ 32) Write Protection Status Register */ 246 } Pcc; 247 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 248 249 /*@}*/ 250 251 #endif /* _SAME54_PCC_COMPONENT_ */ 252
