1 /** 2 * \file 3 * 4 * \brief Component description for MCLK 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAME53_MCLK_COMPONENT_ 31 #define _SAME53_MCLK_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR MCLK */ 35 /* ========================================================================== */ 36 /** \addtogroup SAME53_MCLK Main Clock */ 37 /*@{*/ 38 39 #define MCLK_U2408 40 #define REV_MCLK 0x100 41 42 /* -------- MCLK_INTENCLR : (MCLK Offset: 0x01) (R/W 8) Interrupt Enable Clear -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */ 47 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 48 } bit; /*!< Structure used for bit access */ 49 uint8_t reg; /*!< Type used for register access */ 50 } MCLK_INTENCLR_Type; 51 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 52 53 #define MCLK_INTENCLR_OFFSET 0x01 /**< \brief (MCLK_INTENCLR offset) Interrupt Enable Clear */ 54 #define MCLK_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (MCLK_INTENCLR reset_value) Interrupt Enable Clear */ 55 56 #define MCLK_INTENCLR_CKRDY_Pos 0 /**< \brief (MCLK_INTENCLR) Clock Ready Interrupt Enable */ 57 #define MCLK_INTENCLR_CKRDY (_U_(0x1) << MCLK_INTENCLR_CKRDY_Pos) 58 #define MCLK_INTENCLR_MASK _U_(0x01) /**< \brief (MCLK_INTENCLR) MASK Register */ 59 60 /* -------- MCLK_INTENSET : (MCLK Offset: 0x02) (R/W 8) Interrupt Enable Set -------- */ 61 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 62 typedef union { 63 struct { 64 uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */ 65 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 66 } bit; /*!< Structure used for bit access */ 67 uint8_t reg; /*!< Type used for register access */ 68 } MCLK_INTENSET_Type; 69 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 70 71 #define MCLK_INTENSET_OFFSET 0x02 /**< \brief (MCLK_INTENSET offset) Interrupt Enable Set */ 72 #define MCLK_INTENSET_RESETVALUE _U_(0x00) /**< \brief (MCLK_INTENSET reset_value) Interrupt Enable Set */ 73 74 #define MCLK_INTENSET_CKRDY_Pos 0 /**< \brief (MCLK_INTENSET) Clock Ready Interrupt Enable */ 75 #define MCLK_INTENSET_CKRDY (_U_(0x1) << MCLK_INTENSET_CKRDY_Pos) 76 #define MCLK_INTENSET_MASK _U_(0x01) /**< \brief (MCLK_INTENSET) MASK Register */ 77 78 /* -------- MCLK_INTFLAG : (MCLK Offset: 0x03) (R/W 8) Interrupt Flag Status and Clear -------- */ 79 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 80 typedef union { // __I to avoid read-modify-write on write-to-clear register 81 struct { 82 __I uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */ 83 __I uint8_t Reserved1:7; /*!< bit: 1.. 7 Reserved */ 84 } bit; /*!< Structure used for bit access */ 85 uint8_t reg; /*!< Type used for register access */ 86 } MCLK_INTFLAG_Type; 87 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 88 89 #define MCLK_INTFLAG_OFFSET 0x03 /**< \brief (MCLK_INTFLAG offset) Interrupt Flag Status and Clear */ 90 #define MCLK_INTFLAG_RESETVALUE _U_(0x01) /**< \brief (MCLK_INTFLAG reset_value) Interrupt Flag Status and Clear */ 91 92 #define MCLK_INTFLAG_CKRDY_Pos 0 /**< \brief (MCLK_INTFLAG) Clock Ready */ 93 #define MCLK_INTFLAG_CKRDY (_U_(0x1) << MCLK_INTFLAG_CKRDY_Pos) 94 #define MCLK_INTFLAG_MASK _U_(0x01) /**< \brief (MCLK_INTFLAG) MASK Register */ 95 96 /* -------- MCLK_HSDIV : (MCLK Offset: 0x04) (R/ 8) HS Clock Division -------- */ 97 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 98 typedef union { 99 struct { 100 uint8_t DIV:8; /*!< bit: 0.. 7 CPU Clock Division Factor */ 101 } bit; /*!< Structure used for bit access */ 102 uint8_t reg; /*!< Type used for register access */ 103 } MCLK_HSDIV_Type; 104 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 105 106 #define MCLK_HSDIV_OFFSET 0x04 /**< \brief (MCLK_HSDIV offset) HS Clock Division */ 107 #define MCLK_HSDIV_RESETVALUE _U_(0x01) /**< \brief (MCLK_HSDIV reset_value) HS Clock Division */ 108 109 #define MCLK_HSDIV_DIV_Pos 0 /**< \brief (MCLK_HSDIV) CPU Clock Division Factor */ 110 #define MCLK_HSDIV_DIV_Msk (_U_(0xFF) << MCLK_HSDIV_DIV_Pos) 111 #define MCLK_HSDIV_DIV(value) (MCLK_HSDIV_DIV_Msk & ((value) << MCLK_HSDIV_DIV_Pos)) 112 #define MCLK_HSDIV_DIV_DIV1_Val _U_(0x1) /**< \brief (MCLK_HSDIV) Divide by 1 */ 113 #define MCLK_HSDIV_DIV_DIV1 (MCLK_HSDIV_DIV_DIV1_Val << MCLK_HSDIV_DIV_Pos) 114 #define MCLK_HSDIV_MASK _U_(0xFF) /**< \brief (MCLK_HSDIV) MASK Register */ 115 116 /* -------- MCLK_CPUDIV : (MCLK Offset: 0x05) (R/W 8) CPU Clock Division -------- */ 117 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 118 typedef union { 119 struct { 120 uint8_t DIV:8; /*!< bit: 0.. 7 Low-Power Clock Division Factor */ 121 } bit; /*!< Structure used for bit access */ 122 uint8_t reg; /*!< Type used for register access */ 123 } MCLK_CPUDIV_Type; 124 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 125 126 #define MCLK_CPUDIV_OFFSET 0x05 /**< \brief (MCLK_CPUDIV offset) CPU Clock Division */ 127 #define MCLK_CPUDIV_RESETVALUE _U_(0x01) /**< \brief (MCLK_CPUDIV reset_value) CPU Clock Division */ 128 129 #define MCLK_CPUDIV_DIV_Pos 0 /**< \brief (MCLK_CPUDIV) Low-Power Clock Division Factor */ 130 #define MCLK_CPUDIV_DIV_Msk (_U_(0xFF) << MCLK_CPUDIV_DIV_Pos) 131 #define MCLK_CPUDIV_DIV(value) (MCLK_CPUDIV_DIV_Msk & ((value) << MCLK_CPUDIV_DIV_Pos)) 132 #define MCLK_CPUDIV_DIV_DIV1_Val _U_(0x1) /**< \brief (MCLK_CPUDIV) Divide by 1 */ 133 #define MCLK_CPUDIV_DIV_DIV2_Val _U_(0x2) /**< \brief (MCLK_CPUDIV) Divide by 2 */ 134 #define MCLK_CPUDIV_DIV_DIV4_Val _U_(0x4) /**< \brief (MCLK_CPUDIV) Divide by 4 */ 135 #define MCLK_CPUDIV_DIV_DIV8_Val _U_(0x8) /**< \brief (MCLK_CPUDIV) Divide by 8 */ 136 #define MCLK_CPUDIV_DIV_DIV16_Val _U_(0x10) /**< \brief (MCLK_CPUDIV) Divide by 16 */ 137 #define MCLK_CPUDIV_DIV_DIV32_Val _U_(0x20) /**< \brief (MCLK_CPUDIV) Divide by 32 */ 138 #define MCLK_CPUDIV_DIV_DIV64_Val _U_(0x40) /**< \brief (MCLK_CPUDIV) Divide by 64 */ 139 #define MCLK_CPUDIV_DIV_DIV128_Val _U_(0x80) /**< \brief (MCLK_CPUDIV) Divide by 128 */ 140 #define MCLK_CPUDIV_DIV_DIV1 (MCLK_CPUDIV_DIV_DIV1_Val << MCLK_CPUDIV_DIV_Pos) 141 #define MCLK_CPUDIV_DIV_DIV2 (MCLK_CPUDIV_DIV_DIV2_Val << MCLK_CPUDIV_DIV_Pos) 142 #define MCLK_CPUDIV_DIV_DIV4 (MCLK_CPUDIV_DIV_DIV4_Val << MCLK_CPUDIV_DIV_Pos) 143 #define MCLK_CPUDIV_DIV_DIV8 (MCLK_CPUDIV_DIV_DIV8_Val << MCLK_CPUDIV_DIV_Pos) 144 #define MCLK_CPUDIV_DIV_DIV16 (MCLK_CPUDIV_DIV_DIV16_Val << MCLK_CPUDIV_DIV_Pos) 145 #define MCLK_CPUDIV_DIV_DIV32 (MCLK_CPUDIV_DIV_DIV32_Val << MCLK_CPUDIV_DIV_Pos) 146 #define MCLK_CPUDIV_DIV_DIV64 (MCLK_CPUDIV_DIV_DIV64_Val << MCLK_CPUDIV_DIV_Pos) 147 #define MCLK_CPUDIV_DIV_DIV128 (MCLK_CPUDIV_DIV_DIV128_Val << MCLK_CPUDIV_DIV_Pos) 148 #define MCLK_CPUDIV_MASK _U_(0xFF) /**< \brief (MCLK_CPUDIV) MASK Register */ 149 150 /* -------- MCLK_AHBMASK : (MCLK Offset: 0x10) (R/W 32) AHB Mask -------- */ 151 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 152 typedef union { 153 struct { 154 uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */ 155 uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */ 156 uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */ 157 uint32_t HPB3_:1; /*!< bit: 3 HPB3 AHB Clock Mask */ 158 uint32_t DSU_:1; /*!< bit: 4 DSU AHB Clock Mask */ 159 uint32_t HMATRIX_:1; /*!< bit: 5 HMATRIX AHB Clock Mask */ 160 uint32_t NVMCTRL_:1; /*!< bit: 6 NVMCTRL AHB Clock Mask */ 161 uint32_t HSRAM_:1; /*!< bit: 7 HSRAM AHB Clock Mask */ 162 uint32_t CMCC_:1; /*!< bit: 8 CMCC AHB Clock Mask */ 163 uint32_t DMAC_:1; /*!< bit: 9 DMAC AHB Clock Mask */ 164 uint32_t USB_:1; /*!< bit: 10 USB AHB Clock Mask */ 165 uint32_t BKUPRAM_:1; /*!< bit: 11 BKUPRAM AHB Clock Mask */ 166 uint32_t PAC_:1; /*!< bit: 12 PAC AHB Clock Mask */ 167 uint32_t QSPI_:1; /*!< bit: 13 QSPI AHB Clock Mask */ 168 uint32_t GMAC_:1; /*!< bit: 14 GMAC AHB Clock Mask */ 169 uint32_t SDHC0_:1; /*!< bit: 15 SDHC0 AHB Clock Mask */ 170 uint32_t SDHC1_:1; /*!< bit: 16 SDHC1 AHB Clock Mask */ 171 uint32_t :2; /*!< bit: 17..18 Reserved */ 172 uint32_t ICM_:1; /*!< bit: 19 ICM AHB Clock Mask */ 173 uint32_t PUKCC_:1; /*!< bit: 20 PUKCC AHB Clock Mask */ 174 uint32_t QSPI_2X_:1; /*!< bit: 21 QSPI_2X AHB Clock Mask */ 175 uint32_t NVMCTRL_SMEEPROM_:1; /*!< bit: 22 NVMCTRL_SMEEPROM AHB Clock Mask */ 176 uint32_t NVMCTRL_CACHE_:1; /*!< bit: 23 NVMCTRL_CACHE AHB Clock Mask */ 177 uint32_t :8; /*!< bit: 24..31 Reserved */ 178 } bit; /*!< Structure used for bit access */ 179 uint32_t reg; /*!< Type used for register access */ 180 } MCLK_AHBMASK_Type; 181 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 182 183 #define MCLK_AHBMASK_OFFSET 0x10 /**< \brief (MCLK_AHBMASK offset) AHB Mask */ 184 #define MCLK_AHBMASK_RESETVALUE _U_(0x00FFFFFF) /**< \brief (MCLK_AHBMASK reset_value) AHB Mask */ 185 186 #define MCLK_AHBMASK_HPB0_Pos 0 /**< \brief (MCLK_AHBMASK) HPB0 AHB Clock Mask */ 187 #define MCLK_AHBMASK_HPB0 (_U_(0x1) << MCLK_AHBMASK_HPB0_Pos) 188 #define MCLK_AHBMASK_HPB1_Pos 1 /**< \brief (MCLK_AHBMASK) HPB1 AHB Clock Mask */ 189 #define MCLK_AHBMASK_HPB1 (_U_(0x1) << MCLK_AHBMASK_HPB1_Pos) 190 #define MCLK_AHBMASK_HPB2_Pos 2 /**< \brief (MCLK_AHBMASK) HPB2 AHB Clock Mask */ 191 #define MCLK_AHBMASK_HPB2 (_U_(0x1) << MCLK_AHBMASK_HPB2_Pos) 192 #define MCLK_AHBMASK_HPB3_Pos 3 /**< \brief (MCLK_AHBMASK) HPB3 AHB Clock Mask */ 193 #define MCLK_AHBMASK_HPB3 (_U_(0x1) << MCLK_AHBMASK_HPB3_Pos) 194 #define MCLK_AHBMASK_DSU_Pos 4 /**< \brief (MCLK_AHBMASK) DSU AHB Clock Mask */ 195 #define MCLK_AHBMASK_DSU (_U_(0x1) << MCLK_AHBMASK_DSU_Pos) 196 #define MCLK_AHBMASK_HMATRIX_Pos 5 /**< \brief (MCLK_AHBMASK) HMATRIX AHB Clock Mask */ 197 #define MCLK_AHBMASK_HMATRIX (_U_(0x1) << MCLK_AHBMASK_HMATRIX_Pos) 198 #define MCLK_AHBMASK_NVMCTRL_Pos 6 /**< \brief (MCLK_AHBMASK) NVMCTRL AHB Clock Mask */ 199 #define MCLK_AHBMASK_NVMCTRL (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_Pos) 200 #define MCLK_AHBMASK_HSRAM_Pos 7 /**< \brief (MCLK_AHBMASK) HSRAM AHB Clock Mask */ 201 #define MCLK_AHBMASK_HSRAM (_U_(0x1) << MCLK_AHBMASK_HSRAM_Pos) 202 #define MCLK_AHBMASK_CMCC_Pos 8 /**< \brief (MCLK_AHBMASK) CMCC AHB Clock Mask */ 203 #define MCLK_AHBMASK_CMCC (_U_(0x1) << MCLK_AHBMASK_CMCC_Pos) 204 #define MCLK_AHBMASK_DMAC_Pos 9 /**< \brief (MCLK_AHBMASK) DMAC AHB Clock Mask */ 205 #define MCLK_AHBMASK_DMAC (_U_(0x1) << MCLK_AHBMASK_DMAC_Pos) 206 #define MCLK_AHBMASK_USB_Pos 10 /**< \brief (MCLK_AHBMASK) USB AHB Clock Mask */ 207 #define MCLK_AHBMASK_USB (_U_(0x1) << MCLK_AHBMASK_USB_Pos) 208 #define MCLK_AHBMASK_BKUPRAM_Pos 11 /**< \brief (MCLK_AHBMASK) BKUPRAM AHB Clock Mask */ 209 #define MCLK_AHBMASK_BKUPRAM (_U_(0x1) << MCLK_AHBMASK_BKUPRAM_Pos) 210 #define MCLK_AHBMASK_PAC_Pos 12 /**< \brief (MCLK_AHBMASK) PAC AHB Clock Mask */ 211 #define MCLK_AHBMASK_PAC (_U_(0x1) << MCLK_AHBMASK_PAC_Pos) 212 #define MCLK_AHBMASK_QSPI_Pos 13 /**< \brief (MCLK_AHBMASK) QSPI AHB Clock Mask */ 213 #define MCLK_AHBMASK_QSPI (_U_(0x1) << MCLK_AHBMASK_QSPI_Pos) 214 #define MCLK_AHBMASK_GMAC_Pos 14 /**< \brief (MCLK_AHBMASK) GMAC AHB Clock Mask */ 215 #define MCLK_AHBMASK_GMAC (_U_(0x1) << MCLK_AHBMASK_GMAC_Pos) 216 #define MCLK_AHBMASK_SDHC0_Pos 15 /**< \brief (MCLK_AHBMASK) SDHC0 AHB Clock Mask */ 217 #define MCLK_AHBMASK_SDHC0 (_U_(0x1) << MCLK_AHBMASK_SDHC0_Pos) 218 #define MCLK_AHBMASK_SDHC1_Pos 16 /**< \brief (MCLK_AHBMASK) SDHC1 AHB Clock Mask */ 219 #define MCLK_AHBMASK_SDHC1 (_U_(0x1) << MCLK_AHBMASK_SDHC1_Pos) 220 #define MCLK_AHBMASK_ICM_Pos 19 /**< \brief (MCLK_AHBMASK) ICM AHB Clock Mask */ 221 #define MCLK_AHBMASK_ICM (_U_(0x1) << MCLK_AHBMASK_ICM_Pos) 222 #define MCLK_AHBMASK_PUKCC_Pos 20 /**< \brief (MCLK_AHBMASK) PUKCC AHB Clock Mask */ 223 #define MCLK_AHBMASK_PUKCC (_U_(0x1) << MCLK_AHBMASK_PUKCC_Pos) 224 #define MCLK_AHBMASK_QSPI_2X_Pos 21 /**< \brief (MCLK_AHBMASK) QSPI_2X AHB Clock Mask */ 225 #define MCLK_AHBMASK_QSPI_2X (_U_(0x1) << MCLK_AHBMASK_QSPI_2X_Pos) 226 #define MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos 22 /**< \brief (MCLK_AHBMASK) NVMCTRL_SMEEPROM AHB Clock Mask */ 227 #define MCLK_AHBMASK_NVMCTRL_SMEEPROM (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos) 228 #define MCLK_AHBMASK_NVMCTRL_CACHE_Pos 23 /**< \brief (MCLK_AHBMASK) NVMCTRL_CACHE AHB Clock Mask */ 229 #define MCLK_AHBMASK_NVMCTRL_CACHE (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_CACHE_Pos) 230 #define MCLK_AHBMASK_MASK _U_(0x00F9FFFF) /**< \brief (MCLK_AHBMASK) MASK Register */ 231 232 /* -------- MCLK_APBAMASK : (MCLK Offset: 0x14) (R/W 32) APBA Mask -------- */ 233 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 234 typedef union { 235 struct { 236 uint32_t PAC_:1; /*!< bit: 0 PAC APB Clock Enable */ 237 uint32_t PM_:1; /*!< bit: 1 PM APB Clock Enable */ 238 uint32_t MCLK_:1; /*!< bit: 2 MCLK APB Clock Enable */ 239 uint32_t RSTC_:1; /*!< bit: 3 RSTC APB Clock Enable */ 240 uint32_t OSCCTRL_:1; /*!< bit: 4 OSCCTRL APB Clock Enable */ 241 uint32_t OSC32KCTRL_:1; /*!< bit: 5 OSC32KCTRL APB Clock Enable */ 242 uint32_t SUPC_:1; /*!< bit: 6 SUPC APB Clock Enable */ 243 uint32_t GCLK_:1; /*!< bit: 7 GCLK APB Clock Enable */ 244 uint32_t WDT_:1; /*!< bit: 8 WDT APB Clock Enable */ 245 uint32_t RTC_:1; /*!< bit: 9 RTC APB Clock Enable */ 246 uint32_t EIC_:1; /*!< bit: 10 EIC APB Clock Enable */ 247 uint32_t FREQM_:1; /*!< bit: 11 FREQM APB Clock Enable */ 248 uint32_t SERCOM0_:1; /*!< bit: 12 SERCOM0 APB Clock Enable */ 249 uint32_t SERCOM1_:1; /*!< bit: 13 SERCOM1 APB Clock Enable */ 250 uint32_t TC0_:1; /*!< bit: 14 TC0 APB Clock Enable */ 251 uint32_t TC1_:1; /*!< bit: 15 TC1 APB Clock Enable */ 252 uint32_t :16; /*!< bit: 16..31 Reserved */ 253 } bit; /*!< Structure used for bit access */ 254 uint32_t reg; /*!< Type used for register access */ 255 } MCLK_APBAMASK_Type; 256 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 257 258 #define MCLK_APBAMASK_OFFSET 0x14 /**< \brief (MCLK_APBAMASK offset) APBA Mask */ 259 #define MCLK_APBAMASK_RESETVALUE _U_(0x000007FF) /**< \brief (MCLK_APBAMASK reset_value) APBA Mask */ 260 261 #define MCLK_APBAMASK_PAC_Pos 0 /**< \brief (MCLK_APBAMASK) PAC APB Clock Enable */ 262 #define MCLK_APBAMASK_PAC (_U_(0x1) << MCLK_APBAMASK_PAC_Pos) 263 #define MCLK_APBAMASK_PM_Pos 1 /**< \brief (MCLK_APBAMASK) PM APB Clock Enable */ 264 #define MCLK_APBAMASK_PM (_U_(0x1) << MCLK_APBAMASK_PM_Pos) 265 #define MCLK_APBAMASK_MCLK_Pos 2 /**< \brief (MCLK_APBAMASK) MCLK APB Clock Enable */ 266 #define MCLK_APBAMASK_MCLK (_U_(0x1) << MCLK_APBAMASK_MCLK_Pos) 267 #define MCLK_APBAMASK_RSTC_Pos 3 /**< \brief (MCLK_APBAMASK) RSTC APB Clock Enable */ 268 #define MCLK_APBAMASK_RSTC (_U_(0x1) << MCLK_APBAMASK_RSTC_Pos) 269 #define MCLK_APBAMASK_OSCCTRL_Pos 4 /**< \brief (MCLK_APBAMASK) OSCCTRL APB Clock Enable */ 270 #define MCLK_APBAMASK_OSCCTRL (_U_(0x1) << MCLK_APBAMASK_OSCCTRL_Pos) 271 #define MCLK_APBAMASK_OSC32KCTRL_Pos 5 /**< \brief (MCLK_APBAMASK) OSC32KCTRL APB Clock Enable */ 272 #define MCLK_APBAMASK_OSC32KCTRL (_U_(0x1) << MCLK_APBAMASK_OSC32KCTRL_Pos) 273 #define MCLK_APBAMASK_SUPC_Pos 6 /**< \brief (MCLK_APBAMASK) SUPC APB Clock Enable */ 274 #define MCLK_APBAMASK_SUPC (_U_(0x1) << MCLK_APBAMASK_SUPC_Pos) 275 #define MCLK_APBAMASK_GCLK_Pos 7 /**< \brief (MCLK_APBAMASK) GCLK APB Clock Enable */ 276 #define MCLK_APBAMASK_GCLK (_U_(0x1) << MCLK_APBAMASK_GCLK_Pos) 277 #define MCLK_APBAMASK_WDT_Pos 8 /**< \brief (MCLK_APBAMASK) WDT APB Clock Enable */ 278 #define MCLK_APBAMASK_WDT (_U_(0x1) << MCLK_APBAMASK_WDT_Pos) 279 #define MCLK_APBAMASK_RTC_Pos 9 /**< \brief (MCLK_APBAMASK) RTC APB Clock Enable */ 280 #define MCLK_APBAMASK_RTC (_U_(0x1) << MCLK_APBAMASK_RTC_Pos) 281 #define MCLK_APBAMASK_EIC_Pos 10 /**< \brief (MCLK_APBAMASK) EIC APB Clock Enable */ 282 #define MCLK_APBAMASK_EIC (_U_(0x1) << MCLK_APBAMASK_EIC_Pos) 283 #define MCLK_APBAMASK_FREQM_Pos 11 /**< \brief (MCLK_APBAMASK) FREQM APB Clock Enable */ 284 #define MCLK_APBAMASK_FREQM (_U_(0x1) << MCLK_APBAMASK_FREQM_Pos) 285 #define MCLK_APBAMASK_SERCOM0_Pos 12 /**< \brief (MCLK_APBAMASK) SERCOM0 APB Clock Enable */ 286 #define MCLK_APBAMASK_SERCOM0 (_U_(0x1) << MCLK_APBAMASK_SERCOM0_Pos) 287 #define MCLK_APBAMASK_SERCOM1_Pos 13 /**< \brief (MCLK_APBAMASK) SERCOM1 APB Clock Enable */ 288 #define MCLK_APBAMASK_SERCOM1 (_U_(0x1) << MCLK_APBAMASK_SERCOM1_Pos) 289 #define MCLK_APBAMASK_TC0_Pos 14 /**< \brief (MCLK_APBAMASK) TC0 APB Clock Enable */ 290 #define MCLK_APBAMASK_TC0 (_U_(0x1) << MCLK_APBAMASK_TC0_Pos) 291 #define MCLK_APBAMASK_TC1_Pos 15 /**< \brief (MCLK_APBAMASK) TC1 APB Clock Enable */ 292 #define MCLK_APBAMASK_TC1 (_U_(0x1) << MCLK_APBAMASK_TC1_Pos) 293 #define MCLK_APBAMASK_MASK _U_(0x0000FFFF) /**< \brief (MCLK_APBAMASK) MASK Register */ 294 295 /* -------- MCLK_APBBMASK : (MCLK Offset: 0x18) (R/W 32) APBB Mask -------- */ 296 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 297 typedef union { 298 struct { 299 uint32_t USB_:1; /*!< bit: 0 USB APB Clock Enable */ 300 uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */ 301 uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */ 302 uint32_t :1; /*!< bit: 3 Reserved */ 303 uint32_t PORT_:1; /*!< bit: 4 PORT APB Clock Enable */ 304 uint32_t :1; /*!< bit: 5 Reserved */ 305 uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Clock Enable */ 306 uint32_t EVSYS_:1; /*!< bit: 7 EVSYS APB Clock Enable */ 307 uint32_t :1; /*!< bit: 8 Reserved */ 308 uint32_t SERCOM2_:1; /*!< bit: 9 SERCOM2 APB Clock Enable */ 309 uint32_t SERCOM3_:1; /*!< bit: 10 SERCOM3 APB Clock Enable */ 310 uint32_t TCC0_:1; /*!< bit: 11 TCC0 APB Clock Enable */ 311 uint32_t TCC1_:1; /*!< bit: 12 TCC1 APB Clock Enable */ 312 uint32_t TC2_:1; /*!< bit: 13 TC2 APB Clock Enable */ 313 uint32_t TC3_:1; /*!< bit: 14 TC3 APB Clock Enable */ 314 uint32_t :1; /*!< bit: 15 Reserved */ 315 uint32_t RAMECC_:1; /*!< bit: 16 RAMECC APB Clock Enable */ 316 uint32_t :15; /*!< bit: 17..31 Reserved */ 317 } bit; /*!< Structure used for bit access */ 318 uint32_t reg; /*!< Type used for register access */ 319 } MCLK_APBBMASK_Type; 320 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 321 322 #define MCLK_APBBMASK_OFFSET 0x18 /**< \brief (MCLK_APBBMASK offset) APBB Mask */ 323 #define MCLK_APBBMASK_RESETVALUE _U_(0x00018056) /**< \brief (MCLK_APBBMASK reset_value) APBB Mask */ 324 325 #define MCLK_APBBMASK_USB_Pos 0 /**< \brief (MCLK_APBBMASK) USB APB Clock Enable */ 326 #define MCLK_APBBMASK_USB (_U_(0x1) << MCLK_APBBMASK_USB_Pos) 327 #define MCLK_APBBMASK_DSU_Pos 1 /**< \brief (MCLK_APBBMASK) DSU APB Clock Enable */ 328 #define MCLK_APBBMASK_DSU (_U_(0x1) << MCLK_APBBMASK_DSU_Pos) 329 #define MCLK_APBBMASK_NVMCTRL_Pos 2 /**< \brief (MCLK_APBBMASK) NVMCTRL APB Clock Enable */ 330 #define MCLK_APBBMASK_NVMCTRL (_U_(0x1) << MCLK_APBBMASK_NVMCTRL_Pos) 331 #define MCLK_APBBMASK_PORT_Pos 4 /**< \brief (MCLK_APBBMASK) PORT APB Clock Enable */ 332 #define MCLK_APBBMASK_PORT (_U_(0x1) << MCLK_APBBMASK_PORT_Pos) 333 #define MCLK_APBBMASK_HMATRIX_Pos 6 /**< \brief (MCLK_APBBMASK) HMATRIX APB Clock Enable */ 334 #define MCLK_APBBMASK_HMATRIX (_U_(0x1) << MCLK_APBBMASK_HMATRIX_Pos) 335 #define MCLK_APBBMASK_EVSYS_Pos 7 /**< \brief (MCLK_APBBMASK) EVSYS APB Clock Enable */ 336 #define MCLK_APBBMASK_EVSYS (_U_(0x1) << MCLK_APBBMASK_EVSYS_Pos) 337 #define MCLK_APBBMASK_SERCOM2_Pos 9 /**< \brief (MCLK_APBBMASK) SERCOM2 APB Clock Enable */ 338 #define MCLK_APBBMASK_SERCOM2 (_U_(0x1) << MCLK_APBBMASK_SERCOM2_Pos) 339 #define MCLK_APBBMASK_SERCOM3_Pos 10 /**< \brief (MCLK_APBBMASK) SERCOM3 APB Clock Enable */ 340 #define MCLK_APBBMASK_SERCOM3 (_U_(0x1) << MCLK_APBBMASK_SERCOM3_Pos) 341 #define MCLK_APBBMASK_TCC0_Pos 11 /**< \brief (MCLK_APBBMASK) TCC0 APB Clock Enable */ 342 #define MCLK_APBBMASK_TCC0 (_U_(0x1) << MCLK_APBBMASK_TCC0_Pos) 343 #define MCLK_APBBMASK_TCC1_Pos 12 /**< \brief (MCLK_APBBMASK) TCC1 APB Clock Enable */ 344 #define MCLK_APBBMASK_TCC1 (_U_(0x1) << MCLK_APBBMASK_TCC1_Pos) 345 #define MCLK_APBBMASK_TC2_Pos 13 /**< \brief (MCLK_APBBMASK) TC2 APB Clock Enable */ 346 #define MCLK_APBBMASK_TC2 (_U_(0x1) << MCLK_APBBMASK_TC2_Pos) 347 #define MCLK_APBBMASK_TC3_Pos 14 /**< \brief (MCLK_APBBMASK) TC3 APB Clock Enable */ 348 #define MCLK_APBBMASK_TC3 (_U_(0x1) << MCLK_APBBMASK_TC3_Pos) 349 #define MCLK_APBBMASK_RAMECC_Pos 16 /**< \brief (MCLK_APBBMASK) RAMECC APB Clock Enable */ 350 #define MCLK_APBBMASK_RAMECC (_U_(0x1) << MCLK_APBBMASK_RAMECC_Pos) 351 #define MCLK_APBBMASK_MASK _U_(0x00017ED7) /**< \brief (MCLK_APBBMASK) MASK Register */ 352 353 /* -------- MCLK_APBCMASK : (MCLK Offset: 0x1C) (R/W 32) APBC Mask -------- */ 354 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 355 typedef union { 356 struct { 357 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 358 uint32_t GMAC_:1; /*!< bit: 2 GMAC APB Clock Enable */ 359 uint32_t TCC2_:1; /*!< bit: 3 TCC2 APB Clock Enable */ 360 uint32_t TCC3_:1; /*!< bit: 4 TCC3 APB Clock Enable */ 361 uint32_t TC4_:1; /*!< bit: 5 TC4 APB Clock Enable */ 362 uint32_t TC5_:1; /*!< bit: 6 TC5 APB Clock Enable */ 363 uint32_t PDEC_:1; /*!< bit: 7 PDEC APB Clock Enable */ 364 uint32_t AC_:1; /*!< bit: 8 AC APB Clock Enable */ 365 uint32_t AES_:1; /*!< bit: 9 AES APB Clock Enable */ 366 uint32_t TRNG_:1; /*!< bit: 10 TRNG APB Clock Enable */ 367 uint32_t ICM_:1; /*!< bit: 11 ICM APB Clock Enable */ 368 uint32_t :1; /*!< bit: 12 Reserved */ 369 uint32_t QSPI_:1; /*!< bit: 13 QSPI APB Clock Enable */ 370 uint32_t CCL_:1; /*!< bit: 14 CCL APB Clock Enable */ 371 uint32_t :17; /*!< bit: 15..31 Reserved */ 372 } bit; /*!< Structure used for bit access */ 373 uint32_t reg; /*!< Type used for register access */ 374 } MCLK_APBCMASK_Type; 375 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 376 377 #define MCLK_APBCMASK_OFFSET 0x1C /**< \brief (MCLK_APBCMASK offset) APBC Mask */ 378 #define MCLK_APBCMASK_RESETVALUE _U_(0x00002000) /**< \brief (MCLK_APBCMASK reset_value) APBC Mask */ 379 380 #define MCLK_APBCMASK_GMAC_Pos 2 /**< \brief (MCLK_APBCMASK) GMAC APB Clock Enable */ 381 #define MCLK_APBCMASK_GMAC (_U_(0x1) << MCLK_APBCMASK_GMAC_Pos) 382 #define MCLK_APBCMASK_TCC2_Pos 3 /**< \brief (MCLK_APBCMASK) TCC2 APB Clock Enable */ 383 #define MCLK_APBCMASK_TCC2 (_U_(0x1) << MCLK_APBCMASK_TCC2_Pos) 384 #define MCLK_APBCMASK_TCC3_Pos 4 /**< \brief (MCLK_APBCMASK) TCC3 APB Clock Enable */ 385 #define MCLK_APBCMASK_TCC3 (_U_(0x1) << MCLK_APBCMASK_TCC3_Pos) 386 #define MCLK_APBCMASK_TC4_Pos 5 /**< \brief (MCLK_APBCMASK) TC4 APB Clock Enable */ 387 #define MCLK_APBCMASK_TC4 (_U_(0x1) << MCLK_APBCMASK_TC4_Pos) 388 #define MCLK_APBCMASK_TC5_Pos 6 /**< \brief (MCLK_APBCMASK) TC5 APB Clock Enable */ 389 #define MCLK_APBCMASK_TC5 (_U_(0x1) << MCLK_APBCMASK_TC5_Pos) 390 #define MCLK_APBCMASK_PDEC_Pos 7 /**< \brief (MCLK_APBCMASK) PDEC APB Clock Enable */ 391 #define MCLK_APBCMASK_PDEC (_U_(0x1) << MCLK_APBCMASK_PDEC_Pos) 392 #define MCLK_APBCMASK_AC_Pos 8 /**< \brief (MCLK_APBCMASK) AC APB Clock Enable */ 393 #define MCLK_APBCMASK_AC (_U_(0x1) << MCLK_APBCMASK_AC_Pos) 394 #define MCLK_APBCMASK_AES_Pos 9 /**< \brief (MCLK_APBCMASK) AES APB Clock Enable */ 395 #define MCLK_APBCMASK_AES (_U_(0x1) << MCLK_APBCMASK_AES_Pos) 396 #define MCLK_APBCMASK_TRNG_Pos 10 /**< \brief (MCLK_APBCMASK) TRNG APB Clock Enable */ 397 #define MCLK_APBCMASK_TRNG (_U_(0x1) << MCLK_APBCMASK_TRNG_Pos) 398 #define MCLK_APBCMASK_ICM_Pos 11 /**< \brief (MCLK_APBCMASK) ICM APB Clock Enable */ 399 #define MCLK_APBCMASK_ICM (_U_(0x1) << MCLK_APBCMASK_ICM_Pos) 400 #define MCLK_APBCMASK_QSPI_Pos 13 /**< \brief (MCLK_APBCMASK) QSPI APB Clock Enable */ 401 #define MCLK_APBCMASK_QSPI (_U_(0x1) << MCLK_APBCMASK_QSPI_Pos) 402 #define MCLK_APBCMASK_CCL_Pos 14 /**< \brief (MCLK_APBCMASK) CCL APB Clock Enable */ 403 #define MCLK_APBCMASK_CCL (_U_(0x1) << MCLK_APBCMASK_CCL_Pos) 404 #define MCLK_APBCMASK_MASK _U_(0x00006FFC) /**< \brief (MCLK_APBCMASK) MASK Register */ 405 406 /* -------- MCLK_APBDMASK : (MCLK Offset: 0x20) (R/W 32) APBD Mask -------- */ 407 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 408 typedef union { 409 struct { 410 uint32_t SERCOM4_:1; /*!< bit: 0 SERCOM4 APB Clock Enable */ 411 uint32_t SERCOM5_:1; /*!< bit: 1 SERCOM5 APB Clock Enable */ 412 uint32_t SERCOM6_:1; /*!< bit: 2 SERCOM6 APB Clock Enable */ 413 uint32_t SERCOM7_:1; /*!< bit: 3 SERCOM7 APB Clock Enable */ 414 uint32_t TCC4_:1; /*!< bit: 4 TCC4 APB Clock Enable */ 415 uint32_t TC6_:1; /*!< bit: 5 TC6 APB Clock Enable */ 416 uint32_t TC7_:1; /*!< bit: 6 TC7 APB Clock Enable */ 417 uint32_t ADC0_:1; /*!< bit: 7 ADC0 APB Clock Enable */ 418 uint32_t ADC1_:1; /*!< bit: 8 ADC1 APB Clock Enable */ 419 uint32_t DAC_:1; /*!< bit: 9 DAC APB Clock Enable */ 420 uint32_t I2S_:1; /*!< bit: 10 I2S APB Clock Enable */ 421 uint32_t PCC_:1; /*!< bit: 11 PCC APB Clock Enable */ 422 uint32_t :20; /*!< bit: 12..31 Reserved */ 423 } bit; /*!< Structure used for bit access */ 424 uint32_t reg; /*!< Type used for register access */ 425 } MCLK_APBDMASK_Type; 426 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 427 428 #define MCLK_APBDMASK_OFFSET 0x20 /**< \brief (MCLK_APBDMASK offset) APBD Mask */ 429 #define MCLK_APBDMASK_RESETVALUE _U_(0x00000000) /**< \brief (MCLK_APBDMASK reset_value) APBD Mask */ 430 431 #define MCLK_APBDMASK_SERCOM4_Pos 0 /**< \brief (MCLK_APBDMASK) SERCOM4 APB Clock Enable */ 432 #define MCLK_APBDMASK_SERCOM4 (_U_(0x1) << MCLK_APBDMASK_SERCOM4_Pos) 433 #define MCLK_APBDMASK_SERCOM5_Pos 1 /**< \brief (MCLK_APBDMASK) SERCOM5 APB Clock Enable */ 434 #define MCLK_APBDMASK_SERCOM5 (_U_(0x1) << MCLK_APBDMASK_SERCOM5_Pos) 435 #define MCLK_APBDMASK_SERCOM6_Pos 2 /**< \brief (MCLK_APBDMASK) SERCOM6 APB Clock Enable */ 436 #define MCLK_APBDMASK_SERCOM6 (_U_(0x1) << MCLK_APBDMASK_SERCOM6_Pos) 437 #define MCLK_APBDMASK_SERCOM7_Pos 3 /**< \brief (MCLK_APBDMASK) SERCOM7 APB Clock Enable */ 438 #define MCLK_APBDMASK_SERCOM7 (_U_(0x1) << MCLK_APBDMASK_SERCOM7_Pos) 439 #define MCLK_APBDMASK_TCC4_Pos 4 /**< \brief (MCLK_APBDMASK) TCC4 APB Clock Enable */ 440 #define MCLK_APBDMASK_TCC4 (_U_(0x1) << MCLK_APBDMASK_TCC4_Pos) 441 #define MCLK_APBDMASK_TC6_Pos 5 /**< \brief (MCLK_APBDMASK) TC6 APB Clock Enable */ 442 #define MCLK_APBDMASK_TC6 (_U_(0x1) << MCLK_APBDMASK_TC6_Pos) 443 #define MCLK_APBDMASK_TC7_Pos 6 /**< \brief (MCLK_APBDMASK) TC7 APB Clock Enable */ 444 #define MCLK_APBDMASK_TC7 (_U_(0x1) << MCLK_APBDMASK_TC7_Pos) 445 #define MCLK_APBDMASK_ADC0_Pos 7 /**< \brief (MCLK_APBDMASK) ADC0 APB Clock Enable */ 446 #define MCLK_APBDMASK_ADC0 (_U_(0x1) << MCLK_APBDMASK_ADC0_Pos) 447 #define MCLK_APBDMASK_ADC1_Pos 8 /**< \brief (MCLK_APBDMASK) ADC1 APB Clock Enable */ 448 #define MCLK_APBDMASK_ADC1 (_U_(0x1) << MCLK_APBDMASK_ADC1_Pos) 449 #define MCLK_APBDMASK_DAC_Pos 9 /**< \brief (MCLK_APBDMASK) DAC APB Clock Enable */ 450 #define MCLK_APBDMASK_DAC (_U_(0x1) << MCLK_APBDMASK_DAC_Pos) 451 #define MCLK_APBDMASK_I2S_Pos 10 /**< \brief (MCLK_APBDMASK) I2S APB Clock Enable */ 452 #define MCLK_APBDMASK_I2S (_U_(0x1) << MCLK_APBDMASK_I2S_Pos) 453 #define MCLK_APBDMASK_PCC_Pos 11 /**< \brief (MCLK_APBDMASK) PCC APB Clock Enable */ 454 #define MCLK_APBDMASK_PCC (_U_(0x1) << MCLK_APBDMASK_PCC_Pos) 455 #define MCLK_APBDMASK_MASK _U_(0x00000FFF) /**< \brief (MCLK_APBDMASK) MASK Register */ 456 457 /** \brief MCLK hardware registers */ 458 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 459 typedef struct { 460 RoReg8 Reserved1[0x1]; 461 __IO MCLK_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x01 (R/W 8) Interrupt Enable Clear */ 462 __IO MCLK_INTENSET_Type INTENSET; /**< \brief Offset: 0x02 (R/W 8) Interrupt Enable Set */ 463 __IO MCLK_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x03 (R/W 8) Interrupt Flag Status and Clear */ 464 __I MCLK_HSDIV_Type HSDIV; /**< \brief Offset: 0x04 (R/ 8) HS Clock Division */ 465 __IO MCLK_CPUDIV_Type CPUDIV; /**< \brief Offset: 0x05 (R/W 8) CPU Clock Division */ 466 RoReg8 Reserved2[0xA]; 467 __IO MCLK_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x10 (R/W 32) AHB Mask */ 468 __IO MCLK_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x14 (R/W 32) APBA Mask */ 469 __IO MCLK_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x18 (R/W 32) APBB Mask */ 470 __IO MCLK_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x1C (R/W 32) APBC Mask */ 471 __IO MCLK_APBDMASK_Type APBDMASK; /**< \brief Offset: 0x20 (R/W 32) APBD Mask */ 472 } Mclk; 473 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 474 475 /*@}*/ 476 477 #endif /* _SAME53_MCLK_COMPONENT_ */ 478
