1 /** 2 * \file 3 * 4 * \brief Component description for DSU 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAME51_DSU_COMPONENT_ 31 #define _SAME51_DSU_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR DSU */ 35 /* ========================================================================== */ 36 /** \addtogroup SAME51_DSU Device Service Unit */ 37 /*@{*/ 38 39 #define DSU_U2410 40 #define REV_DSU 0x100 41 42 /* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W 8) Control -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint8_t SWRST:1; /*!< bit: 0 Software Reset */ 47 uint8_t :1; /*!< bit: 1 Reserved */ 48 uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Code */ 49 uint8_t MBIST:1; /*!< bit: 3 Memory built-in self-test */ 50 uint8_t CE:1; /*!< bit: 4 Chip-Erase */ 51 uint8_t :1; /*!< bit: 5 Reserved */ 52 uint8_t ARR:1; /*!< bit: 6 Auxiliary Row Read */ 53 uint8_t SMSA:1; /*!< bit: 7 Start Memory Stream Access */ 54 } bit; /*!< Structure used for bit access */ 55 uint8_t reg; /*!< Type used for register access */ 56 } DSU_CTRL_Type; 57 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 58 59 #define DSU_CTRL_OFFSET 0x0000 /**< \brief (DSU_CTRL offset) Control */ 60 #define DSU_CTRL_RESETVALUE _U_(0x00) /**< \brief (DSU_CTRL reset_value) Control */ 61 62 #define DSU_CTRL_SWRST_Pos 0 /**< \brief (DSU_CTRL) Software Reset */ 63 #define DSU_CTRL_SWRST (_U_(0x1) << DSU_CTRL_SWRST_Pos) 64 #define DSU_CTRL_CRC_Pos 2 /**< \brief (DSU_CTRL) 32-bit Cyclic Redundancy Code */ 65 #define DSU_CTRL_CRC (_U_(0x1) << DSU_CTRL_CRC_Pos) 66 #define DSU_CTRL_MBIST_Pos 3 /**< \brief (DSU_CTRL) Memory built-in self-test */ 67 #define DSU_CTRL_MBIST (_U_(0x1) << DSU_CTRL_MBIST_Pos) 68 #define DSU_CTRL_CE_Pos 4 /**< \brief (DSU_CTRL) Chip-Erase */ 69 #define DSU_CTRL_CE (_U_(0x1) << DSU_CTRL_CE_Pos) 70 #define DSU_CTRL_ARR_Pos 6 /**< \brief (DSU_CTRL) Auxiliary Row Read */ 71 #define DSU_CTRL_ARR (_U_(0x1) << DSU_CTRL_ARR_Pos) 72 #define DSU_CTRL_SMSA_Pos 7 /**< \brief (DSU_CTRL) Start Memory Stream Access */ 73 #define DSU_CTRL_SMSA (_U_(0x1) << DSU_CTRL_SMSA_Pos) 74 #define DSU_CTRL_MASK _U_(0xDD) /**< \brief (DSU_CTRL) MASK Register */ 75 76 /* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W 8) Status A -------- */ 77 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 78 typedef union { 79 struct { 80 uint8_t DONE:1; /*!< bit: 0 Done */ 81 uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */ 82 uint8_t BERR:1; /*!< bit: 2 Bus Error */ 83 uint8_t FAIL:1; /*!< bit: 3 Failure */ 84 uint8_t PERR:1; /*!< bit: 4 Protection Error */ 85 uint8_t :3; /*!< bit: 5.. 7 Reserved */ 86 } bit; /*!< Structure used for bit access */ 87 uint8_t reg; /*!< Type used for register access */ 88 } DSU_STATUSA_Type; 89 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 90 91 #define DSU_STATUSA_OFFSET 0x0001 /**< \brief (DSU_STATUSA offset) Status A */ 92 #define DSU_STATUSA_RESETVALUE _U_(0x00) /**< \brief (DSU_STATUSA reset_value) Status A */ 93 94 #define DSU_STATUSA_DONE_Pos 0 /**< \brief (DSU_STATUSA) Done */ 95 #define DSU_STATUSA_DONE (_U_(0x1) << DSU_STATUSA_DONE_Pos) 96 #define DSU_STATUSA_CRSTEXT_Pos 1 /**< \brief (DSU_STATUSA) CPU Reset Phase Extension */ 97 #define DSU_STATUSA_CRSTEXT (_U_(0x1) << DSU_STATUSA_CRSTEXT_Pos) 98 #define DSU_STATUSA_BERR_Pos 2 /**< \brief (DSU_STATUSA) Bus Error */ 99 #define DSU_STATUSA_BERR (_U_(0x1) << DSU_STATUSA_BERR_Pos) 100 #define DSU_STATUSA_FAIL_Pos 3 /**< \brief (DSU_STATUSA) Failure */ 101 #define DSU_STATUSA_FAIL (_U_(0x1) << DSU_STATUSA_FAIL_Pos) 102 #define DSU_STATUSA_PERR_Pos 4 /**< \brief (DSU_STATUSA) Protection Error */ 103 #define DSU_STATUSA_PERR (_U_(0x1) << DSU_STATUSA_PERR_Pos) 104 #define DSU_STATUSA_MASK _U_(0x1F) /**< \brief (DSU_STATUSA) MASK Register */ 105 106 /* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/ 8) Status B -------- */ 107 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 108 typedef union { 109 struct { 110 uint8_t PROT:1; /*!< bit: 0 Protected */ 111 uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */ 112 uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */ 113 uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */ 114 uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */ 115 uint8_t CELCK:1; /*!< bit: 5 Chip Erase Locked */ 116 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 117 } bit; /*!< Structure used for bit access */ 118 struct { 119 uint8_t :2; /*!< bit: 0.. 1 Reserved */ 120 uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */ 121 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 122 } vec; /*!< Structure used for vec access */ 123 uint8_t reg; /*!< Type used for register access */ 124 } DSU_STATUSB_Type; 125 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 126 127 #define DSU_STATUSB_OFFSET 0x0002 /**< \brief (DSU_STATUSB offset) Status B */ 128 #define DSU_STATUSB_RESETVALUE _U_(0x00) /**< \brief (DSU_STATUSB reset_value) Status B */ 129 130 #define DSU_STATUSB_PROT_Pos 0 /**< \brief (DSU_STATUSB) Protected */ 131 #define DSU_STATUSB_PROT (_U_(0x1) << DSU_STATUSB_PROT_Pos) 132 #define DSU_STATUSB_DBGPRES_Pos 1 /**< \brief (DSU_STATUSB) Debugger Present */ 133 #define DSU_STATUSB_DBGPRES (_U_(0x1) << DSU_STATUSB_DBGPRES_Pos) 134 #define DSU_STATUSB_DCCD0_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel 0 Dirty */ 135 #define DSU_STATUSB_DCCD0 (_U_(1) << DSU_STATUSB_DCCD0_Pos) 136 #define DSU_STATUSB_DCCD1_Pos 3 /**< \brief (DSU_STATUSB) Debug Communication Channel 1 Dirty */ 137 #define DSU_STATUSB_DCCD1 (_U_(1) << DSU_STATUSB_DCCD1_Pos) 138 #define DSU_STATUSB_DCCD_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel x Dirty */ 139 #define DSU_STATUSB_DCCD_Msk (_U_(0x3) << DSU_STATUSB_DCCD_Pos) 140 #define DSU_STATUSB_DCCD(value) (DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos)) 141 #define DSU_STATUSB_HPE_Pos 4 /**< \brief (DSU_STATUSB) Hot-Plugging Enable */ 142 #define DSU_STATUSB_HPE (_U_(0x1) << DSU_STATUSB_HPE_Pos) 143 #define DSU_STATUSB_CELCK_Pos 5 /**< \brief (DSU_STATUSB) Chip Erase Locked */ 144 #define DSU_STATUSB_CELCK (_U_(0x1) << DSU_STATUSB_CELCK_Pos) 145 #define DSU_STATUSB_MASK _U_(0x3F) /**< \brief (DSU_STATUSB) MASK Register */ 146 147 /* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */ 148 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 149 typedef union { 150 struct { 151 uint32_t AMOD:2; /*!< bit: 0.. 1 Access Mode */ 152 uint32_t ADDR:30; /*!< bit: 2..31 Address */ 153 } bit; /*!< Structure used for bit access */ 154 uint32_t reg; /*!< Type used for register access */ 155 } DSU_ADDR_Type; 156 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 157 158 #define DSU_ADDR_OFFSET 0x0004 /**< \brief (DSU_ADDR offset) Address */ 159 #define DSU_ADDR_RESETVALUE _U_(0x00000000) /**< \brief (DSU_ADDR reset_value) Address */ 160 161 #define DSU_ADDR_AMOD_Pos 0 /**< \brief (DSU_ADDR) Access Mode */ 162 #define DSU_ADDR_AMOD_Msk (_U_(0x3) << DSU_ADDR_AMOD_Pos) 163 #define DSU_ADDR_AMOD(value) (DSU_ADDR_AMOD_Msk & ((value) << DSU_ADDR_AMOD_Pos)) 164 #define DSU_ADDR_ADDR_Pos 2 /**< \brief (DSU_ADDR) Address */ 165 #define DSU_ADDR_ADDR_Msk (_U_(0x3FFFFFFF) << DSU_ADDR_ADDR_Pos) 166 #define DSU_ADDR_ADDR(value) (DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos)) 167 #define DSU_ADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_ADDR) MASK Register */ 168 169 /* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */ 170 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 171 typedef union { 172 struct { 173 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 174 uint32_t LENGTH:30; /*!< bit: 2..31 Length */ 175 } bit; /*!< Structure used for bit access */ 176 uint32_t reg; /*!< Type used for register access */ 177 } DSU_LENGTH_Type; 178 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 179 180 #define DSU_LENGTH_OFFSET 0x0008 /**< \brief (DSU_LENGTH offset) Length */ 181 #define DSU_LENGTH_RESETVALUE _U_(0x00000000) /**< \brief (DSU_LENGTH reset_value) Length */ 182 183 #define DSU_LENGTH_LENGTH_Pos 2 /**< \brief (DSU_LENGTH) Length */ 184 #define DSU_LENGTH_LENGTH_Msk (_U_(0x3FFFFFFF) << DSU_LENGTH_LENGTH_Pos) 185 #define DSU_LENGTH_LENGTH(value) (DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos)) 186 #define DSU_LENGTH_MASK _U_(0xFFFFFFFC) /**< \brief (DSU_LENGTH) MASK Register */ 187 188 /* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */ 189 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 190 typedef union { 191 struct { 192 uint32_t DATA:32; /*!< bit: 0..31 Data */ 193 } bit; /*!< Structure used for bit access */ 194 uint32_t reg; /*!< Type used for register access */ 195 } DSU_DATA_Type; 196 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 197 198 #define DSU_DATA_OFFSET 0x000C /**< \brief (DSU_DATA offset) Data */ 199 #define DSU_DATA_RESETVALUE _U_(0x00000000) /**< \brief (DSU_DATA reset_value) Data */ 200 201 #define DSU_DATA_DATA_Pos 0 /**< \brief (DSU_DATA) Data */ 202 #define DSU_DATA_DATA_Msk (_U_(0xFFFFFFFF) << DSU_DATA_DATA_Pos) 203 #define DSU_DATA_DATA(value) (DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos)) 204 #define DSU_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_DATA) MASK Register */ 205 206 /* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */ 207 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 208 typedef union { 209 struct { 210 uint32_t DATA:32; /*!< bit: 0..31 Data */ 211 } bit; /*!< Structure used for bit access */ 212 uint32_t reg; /*!< Type used for register access */ 213 } DSU_DCC_Type; 214 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 215 216 #define DSU_DCC_OFFSET 0x0010 /**< \brief (DSU_DCC offset) Debug Communication Channel n */ 217 #define DSU_DCC_RESETVALUE _U_(0x00000000) /**< \brief (DSU_DCC reset_value) Debug Communication Channel n */ 218 219 #define DSU_DCC_DATA_Pos 0 /**< \brief (DSU_DCC) Data */ 220 #define DSU_DCC_DATA_Msk (_U_(0xFFFFFFFF) << DSU_DCC_DATA_Pos) 221 #define DSU_DCC_DATA(value) (DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos)) 222 #define DSU_DCC_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_DCC) MASK Register */ 223 224 /* -------- DSU_DID : (DSU Offset: 0x0018) (R/ 32) Device Identification -------- */ 225 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 226 typedef union { 227 struct { 228 uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */ 229 uint32_t REVISION:4; /*!< bit: 8..11 Revision Number */ 230 uint32_t DIE:4; /*!< bit: 12..15 Die Number */ 231 uint32_t SERIES:6; /*!< bit: 16..21 Series */ 232 uint32_t :1; /*!< bit: 22 Reserved */ 233 uint32_t FAMILY:5; /*!< bit: 23..27 Family */ 234 uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */ 235 } bit; /*!< Structure used for bit access */ 236 uint32_t reg; /*!< Type used for register access */ 237 } DSU_DID_Type; 238 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 239 240 #define DSU_DID_OFFSET 0x0018 /**< \brief (DSU_DID offset) Device Identification */ 241 242 #define DSU_DID_DEVSEL_Pos 0 /**< \brief (DSU_DID) Device Select */ 243 #define DSU_DID_DEVSEL_Msk (_U_(0xFF) << DSU_DID_DEVSEL_Pos) 244 #define DSU_DID_DEVSEL(value) (DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos)) 245 #define DSU_DID_REVISION_Pos 8 /**< \brief (DSU_DID) Revision Number */ 246 #define DSU_DID_REVISION_Msk (_U_(0xF) << DSU_DID_REVISION_Pos) 247 #define DSU_DID_REVISION(value) (DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos)) 248 #define DSU_DID_DIE_Pos 12 /**< \brief (DSU_DID) Die Number */ 249 #define DSU_DID_DIE_Msk (_U_(0xF) << DSU_DID_DIE_Pos) 250 #define DSU_DID_DIE(value) (DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos)) 251 #define DSU_DID_SERIES_Pos 16 /**< \brief (DSU_DID) Series */ 252 #define DSU_DID_SERIES_Msk (_U_(0x3F) << DSU_DID_SERIES_Pos) 253 #define DSU_DID_SERIES(value) (DSU_DID_SERIES_Msk & ((value) << DSU_DID_SERIES_Pos)) 254 #define DSU_DID_SERIES_0_Val _U_(0x0) /**< \brief (DSU_DID) Cortex-M0+ processor, basic feature set */ 255 #define DSU_DID_SERIES_1_Val _U_(0x1) /**< \brief (DSU_DID) Cortex-M0+ processor, USB */ 256 #define DSU_DID_SERIES_0 (DSU_DID_SERIES_0_Val << DSU_DID_SERIES_Pos) 257 #define DSU_DID_SERIES_1 (DSU_DID_SERIES_1_Val << DSU_DID_SERIES_Pos) 258 #define DSU_DID_FAMILY_Pos 23 /**< \brief (DSU_DID) Family */ 259 #define DSU_DID_FAMILY_Msk (_U_(0x1F) << DSU_DID_FAMILY_Pos) 260 #define DSU_DID_FAMILY(value) (DSU_DID_FAMILY_Msk & ((value) << DSU_DID_FAMILY_Pos)) 261 #define DSU_DID_FAMILY_0_Val _U_(0x0) /**< \brief (DSU_DID) General purpose microcontroller */ 262 #define DSU_DID_FAMILY_1_Val _U_(0x1) /**< \brief (DSU_DID) PicoPower */ 263 #define DSU_DID_FAMILY_0 (DSU_DID_FAMILY_0_Val << DSU_DID_FAMILY_Pos) 264 #define DSU_DID_FAMILY_1 (DSU_DID_FAMILY_1_Val << DSU_DID_FAMILY_Pos) 265 #define DSU_DID_PROCESSOR_Pos 28 /**< \brief (DSU_DID) Processor */ 266 #define DSU_DID_PROCESSOR_Msk (_U_(0xF) << DSU_DID_PROCESSOR_Pos) 267 #define DSU_DID_PROCESSOR(value) (DSU_DID_PROCESSOR_Msk & ((value) << DSU_DID_PROCESSOR_Pos)) 268 #define DSU_DID_PROCESSOR_CM0P_Val _U_(0x1) /**< \brief (DSU_DID) Cortex-M0+ */ 269 #define DSU_DID_PROCESSOR_CM23_Val _U_(0x2) /**< \brief (DSU_DID) Cortex-M23 */ 270 #define DSU_DID_PROCESSOR_CM3_Val _U_(0x3) /**< \brief (DSU_DID) Cortex-M3 */ 271 #define DSU_DID_PROCESSOR_CM4_Val _U_(0x5) /**< \brief (DSU_DID) Cortex-M4 */ 272 #define DSU_DID_PROCESSOR_CM4F_Val _U_(0x6) /**< \brief (DSU_DID) Cortex-M4 with FPU */ 273 #define DSU_DID_PROCESSOR_CM33_Val _U_(0x7) /**< \brief (DSU_DID) Cortex-M33 */ 274 #define DSU_DID_PROCESSOR_CM0P (DSU_DID_PROCESSOR_CM0P_Val << DSU_DID_PROCESSOR_Pos) 275 #define DSU_DID_PROCESSOR_CM23 (DSU_DID_PROCESSOR_CM23_Val << DSU_DID_PROCESSOR_Pos) 276 #define DSU_DID_PROCESSOR_CM3 (DSU_DID_PROCESSOR_CM3_Val << DSU_DID_PROCESSOR_Pos) 277 #define DSU_DID_PROCESSOR_CM4 (DSU_DID_PROCESSOR_CM4_Val << DSU_DID_PROCESSOR_Pos) 278 #define DSU_DID_PROCESSOR_CM4F (DSU_DID_PROCESSOR_CM4F_Val << DSU_DID_PROCESSOR_Pos) 279 #define DSU_DID_PROCESSOR_CM33 (DSU_DID_PROCESSOR_CM33_Val << DSU_DID_PROCESSOR_Pos) 280 #define DSU_DID_MASK _U_(0xFFBFFFFF) /**< \brief (DSU_DID) MASK Register */ 281 282 /* -------- DSU_CFG : (DSU Offset: 0x001C) (R/W 32) Configuration -------- */ 283 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 284 typedef union { 285 struct { 286 uint32_t LQOS:2; /*!< bit: 0.. 1 Latency Quality Of Service */ 287 uint32_t DCCDMALEVEL:2; /*!< bit: 2.. 3 DMA Trigger Level */ 288 uint32_t ETBRAMEN:1; /*!< bit: 4 Trace Control */ 289 uint32_t :27; /*!< bit: 5..31 Reserved */ 290 } bit; /*!< Structure used for bit access */ 291 uint32_t reg; /*!< Type used for register access */ 292 } DSU_CFG_Type; 293 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 294 295 #define DSU_CFG_OFFSET 0x001C /**< \brief (DSU_CFG offset) Configuration */ 296 #define DSU_CFG_RESETVALUE _U_(0x00000002) /**< \brief (DSU_CFG reset_value) Configuration */ 297 298 #define DSU_CFG_LQOS_Pos 0 /**< \brief (DSU_CFG) Latency Quality Of Service */ 299 #define DSU_CFG_LQOS_Msk (_U_(0x3) << DSU_CFG_LQOS_Pos) 300 #define DSU_CFG_LQOS(value) (DSU_CFG_LQOS_Msk & ((value) << DSU_CFG_LQOS_Pos)) 301 #define DSU_CFG_DCCDMALEVEL_Pos 2 /**< \brief (DSU_CFG) DMA Trigger Level */ 302 #define DSU_CFG_DCCDMALEVEL_Msk (_U_(0x3) << DSU_CFG_DCCDMALEVEL_Pos) 303 #define DSU_CFG_DCCDMALEVEL(value) (DSU_CFG_DCCDMALEVEL_Msk & ((value) << DSU_CFG_DCCDMALEVEL_Pos)) 304 #define DSU_CFG_DCCDMALEVEL_EMPTY_Val _U_(0x0) /**< \brief (DSU_CFG) Trigger rises when DCC is empty */ 305 #define DSU_CFG_DCCDMALEVEL_FULL_Val _U_(0x1) /**< \brief (DSU_CFG) Trigger rises when DCC is full */ 306 #define DSU_CFG_DCCDMALEVEL_EMPTY (DSU_CFG_DCCDMALEVEL_EMPTY_Val << DSU_CFG_DCCDMALEVEL_Pos) 307 #define DSU_CFG_DCCDMALEVEL_FULL (DSU_CFG_DCCDMALEVEL_FULL_Val << DSU_CFG_DCCDMALEVEL_Pos) 308 #define DSU_CFG_ETBRAMEN_Pos 4 /**< \brief (DSU_CFG) Trace Control */ 309 #define DSU_CFG_ETBRAMEN (_U_(0x1) << DSU_CFG_ETBRAMEN_Pos) 310 #define DSU_CFG_MASK _U_(0x0000001F) /**< \brief (DSU_CFG) MASK Register */ 311 312 /* -------- DSU_ENTRY0 : (DSU Offset: 0x1000) (R/ 32) CoreSight ROM Table Entry 0 -------- */ 313 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 314 typedef union { 315 struct { 316 uint32_t EPRES:1; /*!< bit: 0 Entry Present */ 317 uint32_t FMT:1; /*!< bit: 1 Format */ 318 uint32_t :10; /*!< bit: 2..11 Reserved */ 319 uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */ 320 } bit; /*!< Structure used for bit access */ 321 uint32_t reg; /*!< Type used for register access */ 322 } DSU_ENTRY0_Type; 323 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 324 325 #define DSU_ENTRY0_OFFSET 0x1000 /**< \brief (DSU_ENTRY0 offset) CoreSight ROM Table Entry 0 */ 326 #define DSU_ENTRY0_RESETVALUE _U_(0x9F0FC002) /**< \brief (DSU_ENTRY0 reset_value) CoreSight ROM Table Entry 0 */ 327 328 #define DSU_ENTRY0_EPRES_Pos 0 /**< \brief (DSU_ENTRY0) Entry Present */ 329 #define DSU_ENTRY0_EPRES (_U_(0x1) << DSU_ENTRY0_EPRES_Pos) 330 #define DSU_ENTRY0_FMT_Pos 1 /**< \brief (DSU_ENTRY0) Format */ 331 #define DSU_ENTRY0_FMT (_U_(0x1) << DSU_ENTRY0_FMT_Pos) 332 #define DSU_ENTRY0_ADDOFF_Pos 12 /**< \brief (DSU_ENTRY0) Address Offset */ 333 #define DSU_ENTRY0_ADDOFF_Msk (_U_(0xFFFFF) << DSU_ENTRY0_ADDOFF_Pos) 334 #define DSU_ENTRY0_ADDOFF(value) (DSU_ENTRY0_ADDOFF_Msk & ((value) << DSU_ENTRY0_ADDOFF_Pos)) 335 #define DSU_ENTRY0_MASK _U_(0xFFFFF003) /**< \brief (DSU_ENTRY0) MASK Register */ 336 337 /* -------- DSU_ENTRY1 : (DSU Offset: 0x1004) (R/ 32) CoreSight ROM Table Entry 1 -------- */ 338 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 339 typedef union { 340 uint32_t reg; /*!< Type used for register access */ 341 } DSU_ENTRY1_Type; 342 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 343 344 #define DSU_ENTRY1_OFFSET 0x1004 /**< \brief (DSU_ENTRY1 offset) CoreSight ROM Table Entry 1 */ 345 #define DSU_ENTRY1_RESETVALUE _U_(0x00000000) /**< \brief (DSU_ENTRY1 reset_value) CoreSight ROM Table Entry 1 */ 346 #define DSU_ENTRY1_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_ENTRY1) MASK Register */ 347 348 /* -------- DSU_END : (DSU Offset: 0x1008) (R/ 32) CoreSight ROM Table End -------- */ 349 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 350 typedef union { 351 struct { 352 uint32_t END:32; /*!< bit: 0..31 End Marker */ 353 } bit; /*!< Structure used for bit access */ 354 uint32_t reg; /*!< Type used for register access */ 355 } DSU_END_Type; 356 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 357 358 #define DSU_END_OFFSET 0x1008 /**< \brief (DSU_END offset) CoreSight ROM Table End */ 359 #define DSU_END_RESETVALUE _U_(0x00000000) /**< \brief (DSU_END reset_value) CoreSight ROM Table End */ 360 361 #define DSU_END_END_Pos 0 /**< \brief (DSU_END) End Marker */ 362 #define DSU_END_END_Msk (_U_(0xFFFFFFFF) << DSU_END_END_Pos) 363 #define DSU_END_END(value) (DSU_END_END_Msk & ((value) << DSU_END_END_Pos)) 364 #define DSU_END_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_END) MASK Register */ 365 366 /* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/ 32) CoreSight ROM Table Memory Type -------- */ 367 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 368 typedef union { 369 struct { 370 uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */ 371 uint32_t :31; /*!< bit: 1..31 Reserved */ 372 } bit; /*!< Structure used for bit access */ 373 uint32_t reg; /*!< Type used for register access */ 374 } DSU_MEMTYPE_Type; 375 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 376 377 #define DSU_MEMTYPE_OFFSET 0x1FCC /**< \brief (DSU_MEMTYPE offset) CoreSight ROM Table Memory Type */ 378 #define DSU_MEMTYPE_RESETVALUE _U_(0x00000000) /**< \brief (DSU_MEMTYPE reset_value) CoreSight ROM Table Memory Type */ 379 380 #define DSU_MEMTYPE_SMEMP_Pos 0 /**< \brief (DSU_MEMTYPE) System Memory Present */ 381 #define DSU_MEMTYPE_SMEMP (_U_(0x1) << DSU_MEMTYPE_SMEMP_Pos) 382 #define DSU_MEMTYPE_MASK _U_(0x00000001) /**< \brief (DSU_MEMTYPE) MASK Register */ 383 384 /* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/ 32) Peripheral Identification 4 -------- */ 385 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 386 typedef union { 387 struct { 388 uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */ 389 uint32_t FKBC:4; /*!< bit: 4.. 7 4KB count */ 390 uint32_t :24; /*!< bit: 8..31 Reserved */ 391 } bit; /*!< Structure used for bit access */ 392 uint32_t reg; /*!< Type used for register access */ 393 } DSU_PID4_Type; 394 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 395 396 #define DSU_PID4_OFFSET 0x1FD0 /**< \brief (DSU_PID4 offset) Peripheral Identification 4 */ 397 #define DSU_PID4_RESETVALUE _U_(0x00000000) /**< \brief (DSU_PID4 reset_value) Peripheral Identification 4 */ 398 399 #define DSU_PID4_JEPCC_Pos 0 /**< \brief (DSU_PID4) JEP-106 Continuation Code */ 400 #define DSU_PID4_JEPCC_Msk (_U_(0xF) << DSU_PID4_JEPCC_Pos) 401 #define DSU_PID4_JEPCC(value) (DSU_PID4_JEPCC_Msk & ((value) << DSU_PID4_JEPCC_Pos)) 402 #define DSU_PID4_FKBC_Pos 4 /**< \brief (DSU_PID4) 4KB count */ 403 #define DSU_PID4_FKBC_Msk (_U_(0xF) << DSU_PID4_FKBC_Pos) 404 #define DSU_PID4_FKBC(value) (DSU_PID4_FKBC_Msk & ((value) << DSU_PID4_FKBC_Pos)) 405 #define DSU_PID4_MASK _U_(0x000000FF) /**< \brief (DSU_PID4) MASK Register */ 406 407 /* -------- DSU_PID5 : (DSU Offset: 0x1FD4) (R/ 32) Peripheral Identification 5 -------- */ 408 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 409 typedef union { 410 uint32_t reg; /*!< Type used for register access */ 411 } DSU_PID5_Type; 412 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 413 414 #define DSU_PID5_OFFSET 0x1FD4 /**< \brief (DSU_PID5 offset) Peripheral Identification 5 */ 415 #define DSU_PID5_RESETVALUE _U_(0x00000000) /**< \brief (DSU_PID5 reset_value) Peripheral Identification 5 */ 416 #define DSU_PID5_MASK _U_(0x00000000) /**< \brief (DSU_PID5) MASK Register */ 417 418 /* -------- DSU_PID6 : (DSU Offset: 0x1FD8) (R/ 32) Peripheral Identification 6 -------- */ 419 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 420 typedef union { 421 uint32_t reg; /*!< Type used for register access */ 422 } DSU_PID6_Type; 423 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 424 425 #define DSU_PID6_OFFSET 0x1FD8 /**< \brief (DSU_PID6 offset) Peripheral Identification 6 */ 426 #define DSU_PID6_RESETVALUE _U_(0x00000000) /**< \brief (DSU_PID6 reset_value) Peripheral Identification 6 */ 427 #define DSU_PID6_MASK _U_(0x00000000) /**< \brief (DSU_PID6) MASK Register */ 428 429 /* -------- DSU_PID7 : (DSU Offset: 0x1FDC) (R/ 32) Peripheral Identification 7 -------- */ 430 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 431 typedef union { 432 uint32_t reg; /*!< Type used for register access */ 433 } DSU_PID7_Type; 434 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 435 436 #define DSU_PID7_OFFSET 0x1FDC /**< \brief (DSU_PID7 offset) Peripheral Identification 7 */ 437 #define DSU_PID7_RESETVALUE _U_(0x00000000) /**< \brief (DSU_PID7 reset_value) Peripheral Identification 7 */ 438 #define DSU_PID7_MASK _U_(0x00000000) /**< \brief (DSU_PID7) MASK Register */ 439 440 /* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/ 32) Peripheral Identification 0 -------- */ 441 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 442 typedef union { 443 struct { 444 uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */ 445 uint32_t :24; /*!< bit: 8..31 Reserved */ 446 } bit; /*!< Structure used for bit access */ 447 uint32_t reg; /*!< Type used for register access */ 448 } DSU_PID0_Type; 449 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 450 451 #define DSU_PID0_OFFSET 0x1FE0 /**< \brief (DSU_PID0 offset) Peripheral Identification 0 */ 452 #define DSU_PID0_RESETVALUE _U_(0x000000D0) /**< \brief (DSU_PID0 reset_value) Peripheral Identification 0 */ 453 454 #define DSU_PID0_PARTNBL_Pos 0 /**< \brief (DSU_PID0) Part Number Low */ 455 #define DSU_PID0_PARTNBL_Msk (_U_(0xFF) << DSU_PID0_PARTNBL_Pos) 456 #define DSU_PID0_PARTNBL(value) (DSU_PID0_PARTNBL_Msk & ((value) << DSU_PID0_PARTNBL_Pos)) 457 #define DSU_PID0_MASK _U_(0x000000FF) /**< \brief (DSU_PID0) MASK Register */ 458 459 /* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/ 32) Peripheral Identification 1 -------- */ 460 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 461 typedef union { 462 struct { 463 uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */ 464 uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */ 465 uint32_t :24; /*!< bit: 8..31 Reserved */ 466 } bit; /*!< Structure used for bit access */ 467 uint32_t reg; /*!< Type used for register access */ 468 } DSU_PID1_Type; 469 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 470 471 #define DSU_PID1_OFFSET 0x1FE4 /**< \brief (DSU_PID1 offset) Peripheral Identification 1 */ 472 #define DSU_PID1_RESETVALUE _U_(0x000000FC) /**< \brief (DSU_PID1 reset_value) Peripheral Identification 1 */ 473 474 #define DSU_PID1_PARTNBH_Pos 0 /**< \brief (DSU_PID1) Part Number High */ 475 #define DSU_PID1_PARTNBH_Msk (_U_(0xF) << DSU_PID1_PARTNBH_Pos) 476 #define DSU_PID1_PARTNBH(value) (DSU_PID1_PARTNBH_Msk & ((value) << DSU_PID1_PARTNBH_Pos)) 477 #define DSU_PID1_JEPIDCL_Pos 4 /**< \brief (DSU_PID1) Low part of the JEP-106 Identity Code */ 478 #define DSU_PID1_JEPIDCL_Msk (_U_(0xF) << DSU_PID1_JEPIDCL_Pos) 479 #define DSU_PID1_JEPIDCL(value) (DSU_PID1_JEPIDCL_Msk & ((value) << DSU_PID1_JEPIDCL_Pos)) 480 #define DSU_PID1_MASK _U_(0x000000FF) /**< \brief (DSU_PID1) MASK Register */ 481 482 /* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/ 32) Peripheral Identification 2 -------- */ 483 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 484 typedef union { 485 struct { 486 uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */ 487 uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */ 488 uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */ 489 uint32_t :24; /*!< bit: 8..31 Reserved */ 490 } bit; /*!< Structure used for bit access */ 491 uint32_t reg; /*!< Type used for register access */ 492 } DSU_PID2_Type; 493 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 494 495 #define DSU_PID2_OFFSET 0x1FE8 /**< \brief (DSU_PID2 offset) Peripheral Identification 2 */ 496 #define DSU_PID2_RESETVALUE _U_(0x00000009) /**< \brief (DSU_PID2 reset_value) Peripheral Identification 2 */ 497 498 #define DSU_PID2_JEPIDCH_Pos 0 /**< \brief (DSU_PID2) JEP-106 Identity Code High */ 499 #define DSU_PID2_JEPIDCH_Msk (_U_(0x7) << DSU_PID2_JEPIDCH_Pos) 500 #define DSU_PID2_JEPIDCH(value) (DSU_PID2_JEPIDCH_Msk & ((value) << DSU_PID2_JEPIDCH_Pos)) 501 #define DSU_PID2_JEPU_Pos 3 /**< \brief (DSU_PID2) JEP-106 Identity Code is used */ 502 #define DSU_PID2_JEPU (_U_(0x1) << DSU_PID2_JEPU_Pos) 503 #define DSU_PID2_REVISION_Pos 4 /**< \brief (DSU_PID2) Revision Number */ 504 #define DSU_PID2_REVISION_Msk (_U_(0xF) << DSU_PID2_REVISION_Pos) 505 #define DSU_PID2_REVISION(value) (DSU_PID2_REVISION_Msk & ((value) << DSU_PID2_REVISION_Pos)) 506 #define DSU_PID2_MASK _U_(0x000000FF) /**< \brief (DSU_PID2) MASK Register */ 507 508 /* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/ 32) Peripheral Identification 3 -------- */ 509 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 510 typedef union { 511 struct { 512 uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */ 513 uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */ 514 uint32_t :24; /*!< bit: 8..31 Reserved */ 515 } bit; /*!< Structure used for bit access */ 516 uint32_t reg; /*!< Type used for register access */ 517 } DSU_PID3_Type; 518 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 519 520 #define DSU_PID3_OFFSET 0x1FEC /**< \brief (DSU_PID3 offset) Peripheral Identification 3 */ 521 #define DSU_PID3_RESETVALUE _U_(0x00000000) /**< \brief (DSU_PID3 reset_value) Peripheral Identification 3 */ 522 523 #define DSU_PID3_CUSMOD_Pos 0 /**< \brief (DSU_PID3) ARM CUSMOD */ 524 #define DSU_PID3_CUSMOD_Msk (_U_(0xF) << DSU_PID3_CUSMOD_Pos) 525 #define DSU_PID3_CUSMOD(value) (DSU_PID3_CUSMOD_Msk & ((value) << DSU_PID3_CUSMOD_Pos)) 526 #define DSU_PID3_REVAND_Pos 4 /**< \brief (DSU_PID3) Revision Number */ 527 #define DSU_PID3_REVAND_Msk (_U_(0xF) << DSU_PID3_REVAND_Pos) 528 #define DSU_PID3_REVAND(value) (DSU_PID3_REVAND_Msk & ((value) << DSU_PID3_REVAND_Pos)) 529 #define DSU_PID3_MASK _U_(0x000000FF) /**< \brief (DSU_PID3) MASK Register */ 530 531 /* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/ 32) Component Identification 0 -------- */ 532 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 533 typedef union { 534 struct { 535 uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */ 536 uint32_t :24; /*!< bit: 8..31 Reserved */ 537 } bit; /*!< Structure used for bit access */ 538 uint32_t reg; /*!< Type used for register access */ 539 } DSU_CID0_Type; 540 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 541 542 #define DSU_CID0_OFFSET 0x1FF0 /**< \brief (DSU_CID0 offset) Component Identification 0 */ 543 #define DSU_CID0_RESETVALUE _U_(0x0000000D) /**< \brief (DSU_CID0 reset_value) Component Identification 0 */ 544 545 #define DSU_CID0_PREAMBLEB0_Pos 0 /**< \brief (DSU_CID0) Preamble Byte 0 */ 546 #define DSU_CID0_PREAMBLEB0_Msk (_U_(0xFF) << DSU_CID0_PREAMBLEB0_Pos) 547 #define DSU_CID0_PREAMBLEB0(value) (DSU_CID0_PREAMBLEB0_Msk & ((value) << DSU_CID0_PREAMBLEB0_Pos)) 548 #define DSU_CID0_MASK _U_(0x000000FF) /**< \brief (DSU_CID0) MASK Register */ 549 550 /* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/ 32) Component Identification 1 -------- */ 551 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 552 typedef union { 553 struct { 554 uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */ 555 uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */ 556 uint32_t :24; /*!< bit: 8..31 Reserved */ 557 } bit; /*!< Structure used for bit access */ 558 uint32_t reg; /*!< Type used for register access */ 559 } DSU_CID1_Type; 560 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 561 562 #define DSU_CID1_OFFSET 0x1FF4 /**< \brief (DSU_CID1 offset) Component Identification 1 */ 563 #define DSU_CID1_RESETVALUE _U_(0x00000010) /**< \brief (DSU_CID1 reset_value) Component Identification 1 */ 564 565 #define DSU_CID1_PREAMBLE_Pos 0 /**< \brief (DSU_CID1) Preamble */ 566 #define DSU_CID1_PREAMBLE_Msk (_U_(0xF) << DSU_CID1_PREAMBLE_Pos) 567 #define DSU_CID1_PREAMBLE(value) (DSU_CID1_PREAMBLE_Msk & ((value) << DSU_CID1_PREAMBLE_Pos)) 568 #define DSU_CID1_CCLASS_Pos 4 /**< \brief (DSU_CID1) Component Class */ 569 #define DSU_CID1_CCLASS_Msk (_U_(0xF) << DSU_CID1_CCLASS_Pos) 570 #define DSU_CID1_CCLASS(value) (DSU_CID1_CCLASS_Msk & ((value) << DSU_CID1_CCLASS_Pos)) 571 #define DSU_CID1_MASK _U_(0x000000FF) /**< \brief (DSU_CID1) MASK Register */ 572 573 /* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/ 32) Component Identification 2 -------- */ 574 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 575 typedef union { 576 struct { 577 uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */ 578 uint32_t :24; /*!< bit: 8..31 Reserved */ 579 } bit; /*!< Structure used for bit access */ 580 uint32_t reg; /*!< Type used for register access */ 581 } DSU_CID2_Type; 582 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 583 584 #define DSU_CID2_OFFSET 0x1FF8 /**< \brief (DSU_CID2 offset) Component Identification 2 */ 585 #define DSU_CID2_RESETVALUE _U_(0x00000005) /**< \brief (DSU_CID2 reset_value) Component Identification 2 */ 586 587 #define DSU_CID2_PREAMBLEB2_Pos 0 /**< \brief (DSU_CID2) Preamble Byte 2 */ 588 #define DSU_CID2_PREAMBLEB2_Msk (_U_(0xFF) << DSU_CID2_PREAMBLEB2_Pos) 589 #define DSU_CID2_PREAMBLEB2(value) (DSU_CID2_PREAMBLEB2_Msk & ((value) << DSU_CID2_PREAMBLEB2_Pos)) 590 #define DSU_CID2_MASK _U_(0x000000FF) /**< \brief (DSU_CID2) MASK Register */ 591 592 /* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/ 32) Component Identification 3 -------- */ 593 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 594 typedef union { 595 struct { 596 uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */ 597 uint32_t :24; /*!< bit: 8..31 Reserved */ 598 } bit; /*!< Structure used for bit access */ 599 uint32_t reg; /*!< Type used for register access */ 600 } DSU_CID3_Type; 601 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 602 603 #define DSU_CID3_OFFSET 0x1FFC /**< \brief (DSU_CID3 offset) Component Identification 3 */ 604 #define DSU_CID3_RESETVALUE _U_(0x000000B1) /**< \brief (DSU_CID3 reset_value) Component Identification 3 */ 605 606 #define DSU_CID3_PREAMBLEB3_Pos 0 /**< \brief (DSU_CID3) Preamble Byte 3 */ 607 #define DSU_CID3_PREAMBLEB3_Msk (_U_(0xFF) << DSU_CID3_PREAMBLEB3_Pos) 608 #define DSU_CID3_PREAMBLEB3(value) (DSU_CID3_PREAMBLEB3_Msk & ((value) << DSU_CID3_PREAMBLEB3_Pos)) 609 #define DSU_CID3_MASK _U_(0x000000FF) /**< \brief (DSU_CID3) MASK Register */ 610 611 /** \brief DSU hardware registers */ 612 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 613 typedef struct { 614 __O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */ 615 __IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */ 616 __I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */ 617 RoReg8 Reserved1[0x1]; 618 __IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */ 619 __IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */ 620 __IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */ 621 __IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */ 622 __I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */ 623 __IO DSU_CFG_Type CFG; /**< \brief Offset: 0x001C (R/W 32) Configuration */ 624 RoReg8 Reserved2[0xFE0]; 625 __I DSU_ENTRY0_Type ENTRY0; /**< \brief Offset: 0x1000 (R/ 32) CoreSight ROM Table Entry 0 */ 626 __I DSU_ENTRY1_Type ENTRY1; /**< \brief Offset: 0x1004 (R/ 32) CoreSight ROM Table Entry 1 */ 627 __I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) CoreSight ROM Table End */ 628 RoReg8 Reserved3[0xFC0]; 629 __I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) CoreSight ROM Table Memory Type */ 630 __I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */ 631 __I DSU_PID5_Type PID5; /**< \brief Offset: 0x1FD4 (R/ 32) Peripheral Identification 5 */ 632 __I DSU_PID6_Type PID6; /**< \brief Offset: 0x1FD8 (R/ 32) Peripheral Identification 6 */ 633 __I DSU_PID7_Type PID7; /**< \brief Offset: 0x1FDC (R/ 32) Peripheral Identification 7 */ 634 __I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */ 635 __I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */ 636 __I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */ 637 __I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */ 638 __I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */ 639 __I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */ 640 __I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */ 641 __I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */ 642 } Dsu; 643 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 644 645 /*@}*/ 646 647 #endif /* _SAME51_DSU_COMPONENT_ */ 648
