1 /** 2 * \file 3 * 4 * \brief Instance description for TCC3 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMD51_TCC3_INSTANCE_ 31 #define _SAMD51_TCC3_INSTANCE_ 32 33 /* ========== Register definition for TCC3 peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_TCC3_CTRLA (0x42001000) /**< \brief (TCC3) Control A */ 36 #define REG_TCC3_CTRLBCLR (0x42001004) /**< \brief (TCC3) Control B Clear */ 37 #define REG_TCC3_CTRLBSET (0x42001005) /**< \brief (TCC3) Control B Set */ 38 #define REG_TCC3_SYNCBUSY (0x42001008) /**< \brief (TCC3) Synchronization Busy */ 39 #define REG_TCC3_FCTRLA (0x4200100C) /**< \brief (TCC3) Recoverable Fault A Configuration */ 40 #define REG_TCC3_FCTRLB (0x42001010) /**< \brief (TCC3) Recoverable Fault B Configuration */ 41 #define REG_TCC3_DRVCTRL (0x42001018) /**< \brief (TCC3) Driver Control */ 42 #define REG_TCC3_DBGCTRL (0x4200101E) /**< \brief (TCC3) Debug Control */ 43 #define REG_TCC3_EVCTRL (0x42001020) /**< \brief (TCC3) Event Control */ 44 #define REG_TCC3_INTENCLR (0x42001024) /**< \brief (TCC3) Interrupt Enable Clear */ 45 #define REG_TCC3_INTENSET (0x42001028) /**< \brief (TCC3) Interrupt Enable Set */ 46 #define REG_TCC3_INTFLAG (0x4200102C) /**< \brief (TCC3) Interrupt Flag Status and Clear */ 47 #define REG_TCC3_STATUS (0x42001030) /**< \brief (TCC3) Status */ 48 #define REG_TCC3_COUNT (0x42001034) /**< \brief (TCC3) Count */ 49 #define REG_TCC3_WAVE (0x4200103C) /**< \brief (TCC3) Waveform Control */ 50 #define REG_TCC3_PER (0x42001040) /**< \brief (TCC3) Period */ 51 #define REG_TCC3_CC0 (0x42001044) /**< \brief (TCC3) Compare and Capture 0 */ 52 #define REG_TCC3_CC1 (0x42001048) /**< \brief (TCC3) Compare and Capture 1 */ 53 #define REG_TCC3_PERBUF (0x4200106C) /**< \brief (TCC3) Period Buffer */ 54 #define REG_TCC3_CCBUF0 (0x42001070) /**< \brief (TCC3) Compare and Capture Buffer 0 */ 55 #define REG_TCC3_CCBUF1 (0x42001074) /**< \brief (TCC3) Compare and Capture Buffer 1 */ 56 #else 57 #define REG_TCC3_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (TCC3) Control A */ 58 #define REG_TCC3_CTRLBCLR (*(RwReg8 *)0x42001004UL) /**< \brief (TCC3) Control B Clear */ 59 #define REG_TCC3_CTRLBSET (*(RwReg8 *)0x42001005UL) /**< \brief (TCC3) Control B Set */ 60 #define REG_TCC3_SYNCBUSY (*(RoReg *)0x42001008UL) /**< \brief (TCC3) Synchronization Busy */ 61 #define REG_TCC3_FCTRLA (*(RwReg *)0x4200100CUL) /**< \brief (TCC3) Recoverable Fault A Configuration */ 62 #define REG_TCC3_FCTRLB (*(RwReg *)0x42001010UL) /**< \brief (TCC3) Recoverable Fault B Configuration */ 63 #define REG_TCC3_DRVCTRL (*(RwReg *)0x42001018UL) /**< \brief (TCC3) Driver Control */ 64 #define REG_TCC3_DBGCTRL (*(RwReg8 *)0x4200101EUL) /**< \brief (TCC3) Debug Control */ 65 #define REG_TCC3_EVCTRL (*(RwReg *)0x42001020UL) /**< \brief (TCC3) Event Control */ 66 #define REG_TCC3_INTENCLR (*(RwReg *)0x42001024UL) /**< \brief (TCC3) Interrupt Enable Clear */ 67 #define REG_TCC3_INTENSET (*(RwReg *)0x42001028UL) /**< \brief (TCC3) Interrupt Enable Set */ 68 #define REG_TCC3_INTFLAG (*(RwReg *)0x4200102CUL) /**< \brief (TCC3) Interrupt Flag Status and Clear */ 69 #define REG_TCC3_STATUS (*(RwReg *)0x42001030UL) /**< \brief (TCC3) Status */ 70 #define REG_TCC3_COUNT (*(RwReg *)0x42001034UL) /**< \brief (TCC3) Count */ 71 #define REG_TCC3_WAVE (*(RwReg *)0x4200103CUL) /**< \brief (TCC3) Waveform Control */ 72 #define REG_TCC3_PER (*(RwReg *)0x42001040UL) /**< \brief (TCC3) Period */ 73 #define REG_TCC3_CC0 (*(RwReg *)0x42001044UL) /**< \brief (TCC3) Compare and Capture 0 */ 74 #define REG_TCC3_CC1 (*(RwReg *)0x42001048UL) /**< \brief (TCC3) Compare and Capture 1 */ 75 #define REG_TCC3_PERBUF (*(RwReg *)0x4200106CUL) /**< \brief (TCC3) Period Buffer */ 76 #define REG_TCC3_CCBUF0 (*(RwReg *)0x42001070UL) /**< \brief (TCC3) Compare and Capture Buffer 0 */ 77 #define REG_TCC3_CCBUF1 (*(RwReg *)0x42001074UL) /**< \brief (TCC3) Compare and Capture Buffer 1 */ 78 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 79 80 /* ========== Instance parameters for TCC3 peripheral ========== */ 81 #define TCC3_CC_NUM 2 // Number of Compare/Capture units 82 #define TCC3_DITHERING 0 // Dithering feature implemented 83 #define TCC3_DMAC_ID_MC_0 39 84 #define TCC3_DMAC_ID_MC_1 40 85 #define TCC3_DMAC_ID_MC_LSB 39 86 #define TCC3_DMAC_ID_MC_MSB 40 87 #define TCC3_DMAC_ID_MC_SIZE 2 88 #define TCC3_DMAC_ID_OVF 38 // DMA overflow/underflow/retrigger trigger 89 #define TCC3_DTI 0 // Dead-Time-Insertion feature implemented 90 #define TCC3_EXT 0 // Coding of implemented extended features 91 #define TCC3_GCLK_ID 29 // Index of Generic Clock 92 #define TCC3_MASTER_SLAVE_MODE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave 93 #define TCC3_OTMX 0 // Output Matrix feature implemented 94 #define TCC3_OW_NUM 2 // Number of Output Waveforms 95 #define TCC3_PG 0 // Pattern Generation feature implemented 96 #define TCC3_SIZE 16 97 #define TCC3_SWAP 0 // DTI outputs swap feature implemented 98 99 #endif /* _SAMD51_TCC3_INSTANCE_ */ 100
