1 /** 2 * \file 3 * 4 * \brief Instance description for TCC1 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMD51_TCC1_INSTANCE_ 31 #define _SAMD51_TCC1_INSTANCE_ 32 33 /* ========== Register definition for TCC1 peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_TCC1_CTRLA (0x41018000) /**< \brief (TCC1) Control A */ 36 #define REG_TCC1_CTRLBCLR (0x41018004) /**< \brief (TCC1) Control B Clear */ 37 #define REG_TCC1_CTRLBSET (0x41018005) /**< \brief (TCC1) Control B Set */ 38 #define REG_TCC1_SYNCBUSY (0x41018008) /**< \brief (TCC1) Synchronization Busy */ 39 #define REG_TCC1_FCTRLA (0x4101800C) /**< \brief (TCC1) Recoverable Fault A Configuration */ 40 #define REG_TCC1_FCTRLB (0x41018010) /**< \brief (TCC1) Recoverable Fault B Configuration */ 41 #define REG_TCC1_WEXCTRL (0x41018014) /**< \brief (TCC1) Waveform Extension Configuration */ 42 #define REG_TCC1_DRVCTRL (0x41018018) /**< \brief (TCC1) Driver Control */ 43 #define REG_TCC1_DBGCTRL (0x4101801E) /**< \brief (TCC1) Debug Control */ 44 #define REG_TCC1_EVCTRL (0x41018020) /**< \brief (TCC1) Event Control */ 45 #define REG_TCC1_INTENCLR (0x41018024) /**< \brief (TCC1) Interrupt Enable Clear */ 46 #define REG_TCC1_INTENSET (0x41018028) /**< \brief (TCC1) Interrupt Enable Set */ 47 #define REG_TCC1_INTFLAG (0x4101802C) /**< \brief (TCC1) Interrupt Flag Status and Clear */ 48 #define REG_TCC1_STATUS (0x41018030) /**< \brief (TCC1) Status */ 49 #define REG_TCC1_COUNT (0x41018034) /**< \brief (TCC1) Count */ 50 #define REG_TCC1_PATT (0x41018038) /**< \brief (TCC1) Pattern */ 51 #define REG_TCC1_WAVE (0x4101803C) /**< \brief (TCC1) Waveform Control */ 52 #define REG_TCC1_PER (0x41018040) /**< \brief (TCC1) Period */ 53 #define REG_TCC1_CC0 (0x41018044) /**< \brief (TCC1) Compare and Capture 0 */ 54 #define REG_TCC1_CC1 (0x41018048) /**< \brief (TCC1) Compare and Capture 1 */ 55 #define REG_TCC1_CC2 (0x4101804C) /**< \brief (TCC1) Compare and Capture 2 */ 56 #define REG_TCC1_CC3 (0x41018050) /**< \brief (TCC1) Compare and Capture 3 */ 57 #define REG_TCC1_PATTBUF (0x41018064) /**< \brief (TCC1) Pattern Buffer */ 58 #define REG_TCC1_PERBUF (0x4101806C) /**< \brief (TCC1) Period Buffer */ 59 #define REG_TCC1_CCBUF0 (0x41018070) /**< \brief (TCC1) Compare and Capture Buffer 0 */ 60 #define REG_TCC1_CCBUF1 (0x41018074) /**< \brief (TCC1) Compare and Capture Buffer 1 */ 61 #define REG_TCC1_CCBUF2 (0x41018078) /**< \brief (TCC1) Compare and Capture Buffer 2 */ 62 #define REG_TCC1_CCBUF3 (0x4101807C) /**< \brief (TCC1) Compare and Capture Buffer 3 */ 63 #else 64 #define REG_TCC1_CTRLA (*(RwReg *)0x41018000UL) /**< \brief (TCC1) Control A */ 65 #define REG_TCC1_CTRLBCLR (*(RwReg8 *)0x41018004UL) /**< \brief (TCC1) Control B Clear */ 66 #define REG_TCC1_CTRLBSET (*(RwReg8 *)0x41018005UL) /**< \brief (TCC1) Control B Set */ 67 #define REG_TCC1_SYNCBUSY (*(RoReg *)0x41018008UL) /**< \brief (TCC1) Synchronization Busy */ 68 #define REG_TCC1_FCTRLA (*(RwReg *)0x4101800CUL) /**< \brief (TCC1) Recoverable Fault A Configuration */ 69 #define REG_TCC1_FCTRLB (*(RwReg *)0x41018010UL) /**< \brief (TCC1) Recoverable Fault B Configuration */ 70 #define REG_TCC1_WEXCTRL (*(RwReg *)0x41018014UL) /**< \brief (TCC1) Waveform Extension Configuration */ 71 #define REG_TCC1_DRVCTRL (*(RwReg *)0x41018018UL) /**< \brief (TCC1) Driver Control */ 72 #define REG_TCC1_DBGCTRL (*(RwReg8 *)0x4101801EUL) /**< \brief (TCC1) Debug Control */ 73 #define REG_TCC1_EVCTRL (*(RwReg *)0x41018020UL) /**< \brief (TCC1) Event Control */ 74 #define REG_TCC1_INTENCLR (*(RwReg *)0x41018024UL) /**< \brief (TCC1) Interrupt Enable Clear */ 75 #define REG_TCC1_INTENSET (*(RwReg *)0x41018028UL) /**< \brief (TCC1) Interrupt Enable Set */ 76 #define REG_TCC1_INTFLAG (*(RwReg *)0x4101802CUL) /**< \brief (TCC1) Interrupt Flag Status and Clear */ 77 #define REG_TCC1_STATUS (*(RwReg *)0x41018030UL) /**< \brief (TCC1) Status */ 78 #define REG_TCC1_COUNT (*(RwReg *)0x41018034UL) /**< \brief (TCC1) Count */ 79 #define REG_TCC1_PATT (*(RwReg16*)0x41018038UL) /**< \brief (TCC1) Pattern */ 80 #define REG_TCC1_WAVE (*(RwReg *)0x4101803CUL) /**< \brief (TCC1) Waveform Control */ 81 #define REG_TCC1_PER (*(RwReg *)0x41018040UL) /**< \brief (TCC1) Period */ 82 #define REG_TCC1_CC0 (*(RwReg *)0x41018044UL) /**< \brief (TCC1) Compare and Capture 0 */ 83 #define REG_TCC1_CC1 (*(RwReg *)0x41018048UL) /**< \brief (TCC1) Compare and Capture 1 */ 84 #define REG_TCC1_CC2 (*(RwReg *)0x4101804CUL) /**< \brief (TCC1) Compare and Capture 2 */ 85 #define REG_TCC1_CC3 (*(RwReg *)0x41018050UL) /**< \brief (TCC1) Compare and Capture 3 */ 86 #define REG_TCC1_PATTBUF (*(RwReg16*)0x41018064UL) /**< \brief (TCC1) Pattern Buffer */ 87 #define REG_TCC1_PERBUF (*(RwReg *)0x4101806CUL) /**< \brief (TCC1) Period Buffer */ 88 #define REG_TCC1_CCBUF0 (*(RwReg *)0x41018070UL) /**< \brief (TCC1) Compare and Capture Buffer 0 */ 89 #define REG_TCC1_CCBUF1 (*(RwReg *)0x41018074UL) /**< \brief (TCC1) Compare and Capture Buffer 1 */ 90 #define REG_TCC1_CCBUF2 (*(RwReg *)0x41018078UL) /**< \brief (TCC1) Compare and Capture Buffer 2 */ 91 #define REG_TCC1_CCBUF3 (*(RwReg *)0x4101807CUL) /**< \brief (TCC1) Compare and Capture Buffer 3 */ 92 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 93 94 /* ========== Instance parameters for TCC1 peripheral ========== */ 95 #define TCC1_CC_NUM 4 // Number of Compare/Capture units 96 #define TCC1_DITHERING 1 // Dithering feature implemented 97 #define TCC1_DMAC_ID_MC_0 30 98 #define TCC1_DMAC_ID_MC_1 31 99 #define TCC1_DMAC_ID_MC_2 32 100 #define TCC1_DMAC_ID_MC_3 33 101 #define TCC1_DMAC_ID_MC_LSB 30 102 #define TCC1_DMAC_ID_MC_MSB 33 103 #define TCC1_DMAC_ID_MC_SIZE 4 104 #define TCC1_DMAC_ID_OVF 29 // DMA overflow/underflow/retrigger trigger 105 #define TCC1_DTI 1 // Dead-Time-Insertion feature implemented 106 #define TCC1_EXT 31 // Coding of implemented extended features 107 #define TCC1_GCLK_ID 25 // Index of Generic Clock 108 #define TCC1_MASTER_SLAVE_MODE 2 // TCC type 0 : NA, 1 : Master, 2 : Slave 109 #define TCC1_OTMX 1 // Output Matrix feature implemented 110 #define TCC1_OW_NUM 8 // Number of Output Waveforms 111 #define TCC1_PG 1 // Pattern Generation feature implemented 112 #define TCC1_SIZE 24 113 #define TCC1_SWAP 1 // DTI outputs swap feature implemented 114 115 #endif /* _SAMD51_TCC1_INSTANCE_ */ 116
