1 /** 2 * \file 3 * 4 * \brief Instance description for CAN0 5 * 6 * Copyright (c) 2016 Atmel Corporation. All rights reserved. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions are met: 14 * 15 * 1. Redistributions of source code must retain the above copyright notice, 16 * this list of conditions and the following disclaimer. 17 * 18 * 2. Redistributions in binary form must reproduce the above copyright notice, 19 * this list of conditions and the following disclaimer in the documentation 20 * and/or other materials provided with the distribution. 21 * 22 * 3. The name of Atmel may not be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * 4. This software may only be redistributed and used in connection with an 26 * Atmel microcontroller product. 27 * 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 * 40 * \asf_license_stop 41 * 42 */ 43 44 #ifndef _SAMD51_CAN0_INSTANCE_ 45 #define _SAMD51_CAN0_INSTANCE_ 46 47 /* ========== Register definition for CAN0 peripheral ========== */ 48 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 49 #define REG_CAN0_CREL (0x42000000U) /**< \brief (CAN0) Core Release */ 50 #define REG_CAN0_ENDN (0x42000004U) /**< \brief (CAN0) Endian */ 51 #define REG_CAN0_MRCFG (0x42000008U) /**< \brief (CAN0) Message RAM Configuration */ 52 #define REG_CAN0_DBTP (0x4200000CU) /**< \brief (CAN0) Fast Bit Timing and Prescaler */ 53 #define REG_CAN0_TEST (0x42000010U) /**< \brief (CAN0) Test */ 54 #define REG_CAN0_RWD (0x42000014U) /**< \brief (CAN0) RAM Watchdog */ 55 #define REG_CAN0_CCCR (0x42000018U) /**< \brief (CAN0) CC Control */ 56 #define REG_CAN0_NBTP (0x4200001CU) /**< \brief (CAN0) Nominal Bit Timing and Prescaler */ 57 #define REG_CAN0_TSCC (0x42000020U) /**< \brief (CAN0) Timestamp Counter Configuration */ 58 #define REG_CAN0_TSCV (0x42000024U) /**< \brief (CAN0) Timestamp Counter Value */ 59 #define REG_CAN0_TOCC (0x42000028U) /**< \brief (CAN0) Timeout Counter Configuration */ 60 #define REG_CAN0_TOCV (0x4200002CU) /**< \brief (CAN0) Timeout Counter Value */ 61 #define REG_CAN0_ECR (0x42000040U) /**< \brief (CAN0) Error Counter */ 62 #define REG_CAN0_PSR (0x42000044U) /**< \brief (CAN0) Protocol Status */ 63 #define REG_CAN0_TDCR (0x42000048U) /**< \brief (CAN0) Extended ID Filter Configuration */ 64 #define REG_CAN0_IR (0x42000050U) /**< \brief (CAN0) Interrupt */ 65 #define REG_CAN0_IE (0x42000054U) /**< \brief (CAN0) Interrupt Enable */ 66 #define REG_CAN0_ILS (0x42000058U) /**< \brief (CAN0) Interrupt Line Select */ 67 #define REG_CAN0_ILE (0x4200005CU) /**< \brief (CAN0) Interrupt Line Enable */ 68 #define REG_CAN0_GFC (0x42000080U) /**< \brief (CAN0) Global Filter Configuration */ 69 #define REG_CAN0_SIDFC (0x42000084U) /**< \brief (CAN0) Standard ID Filter Configuration */ 70 #define REG_CAN0_XIDFC (0x42000088U) /**< \brief (CAN0) Extended ID Filter Configuration */ 71 #define REG_CAN0_XIDAM (0x42000090U) /**< \brief (CAN0) Extended ID AND Mask */ 72 #define REG_CAN0_HPMS (0x42000094U) /**< \brief (CAN0) High Priority Message Status */ 73 #define REG_CAN0_NDAT1 (0x42000098U) /**< \brief (CAN0) New Data 1 */ 74 #define REG_CAN0_NDAT2 (0x4200009CU) /**< \brief (CAN0) New Data 2 */ 75 #define REG_CAN0_RXF0C (0x420000A0U) /**< \brief (CAN0) Rx FIFO 0 Configuration */ 76 #define REG_CAN0_RXF0S (0x420000A4U) /**< \brief (CAN0) Rx FIFO 0 Status */ 77 #define REG_CAN0_RXF0A (0x420000A8U) /**< \brief (CAN0) Rx FIFO 0 Acknowledge */ 78 #define REG_CAN0_RXBC (0x420000ACU) /**< \brief (CAN0) Rx Buffer Configuration */ 79 #define REG_CAN0_RXF1C (0x420000B0U) /**< \brief (CAN0) Rx FIFO 1 Configuration */ 80 #define REG_CAN0_RXF1S (0x420000B4U) /**< \brief (CAN0) Rx FIFO 1 Status */ 81 #define REG_CAN0_RXF1A (0x420000B8U) /**< \brief (CAN0) Rx FIFO 1 Acknowledge */ 82 #define REG_CAN0_RXESC (0x420000BCU) /**< \brief (CAN0) Rx Buffer / FIFO Element Size Configuration */ 83 #define REG_CAN0_TXBC (0x420000C0U) /**< \brief (CAN0) Tx Buffer Configuration */ 84 #define REG_CAN0_TXFQS (0x420000C4U) /**< \brief (CAN0) Tx FIFO / Queue Status */ 85 #define REG_CAN0_TXESC (0x420000C8U) /**< \brief (CAN0) Tx Buffer Element Size Configuration */ 86 #define REG_CAN0_TXBRP (0x420000CCU) /**< \brief (CAN0) Tx Buffer Request Pending */ 87 #define REG_CAN0_TXBAR (0x420000D0U) /**< \brief (CAN0) Tx Buffer Add Request */ 88 #define REG_CAN0_TXBCR (0x420000D4U) /**< \brief (CAN0) Tx Buffer Cancellation Request */ 89 #define REG_CAN0_TXBTO (0x420000D8U) /**< \brief (CAN0) Tx Buffer Transmission Occurred */ 90 #define REG_CAN0_TXBCF (0x420000DCU) /**< \brief (CAN0) Tx Buffer Cancellation Finished */ 91 #define REG_CAN0_TXBTIE (0x420000E0U) /**< \brief (CAN0) Tx Buffer Transmission Interrupt Enable */ 92 #define REG_CAN0_TXBCIE (0x420000E4U) /**< \brief (CAN0) Tx Buffer Cancellation Finished Interrupt Enable */ 93 #define REG_CAN0_TXEFC (0x420000F0U) /**< \brief (CAN0) Tx Event FIFO Configuration */ 94 #define REG_CAN0_TXEFS (0x420000F4U) /**< \brief (CAN0) Tx Event FIFO Status */ 95 #define REG_CAN0_TXEFA (0x420000F8U) /**< \brief (CAN0) Tx Event FIFO Acknowledge */ 96 #else 97 #define REG_CAN0_CREL (*(RoReg *)0x42000000U) /**< \brief (CAN0) Core Release */ 98 #define REG_CAN0_ENDN (*(RoReg *)0x42000004U) /**< \brief (CAN0) Endian */ 99 #define REG_CAN0_MRCFG (*(RwReg *)0x42000008U) /**< \brief (CAN0) Message RAM Configuration */ 100 #define REG_CAN0_DBTP (*(RwReg *)0x4200000CU) /**< \brief (CAN0) Fast Bit Timing and Prescaler */ 101 #define REG_CAN0_TEST (*(RwReg *)0x42000010U) /**< \brief (CAN0) Test */ 102 #define REG_CAN0_RWD (*(RwReg *)0x42000014U) /**< \brief (CAN0) RAM Watchdog */ 103 #define REG_CAN0_CCCR (*(RwReg *)0x42000018U) /**< \brief (CAN0) CC Control */ 104 #define REG_CAN0_NBTP (*(RwReg *)0x4200001CU) /**< \brief (CAN0) Nominal Bit Timing and Prescaler */ 105 #define REG_CAN0_TSCC (*(RwReg *)0x42000020U) /**< \brief (CAN0) Timestamp Counter Configuration */ 106 #define REG_CAN0_TSCV (*(RoReg *)0x42000024U) /**< \brief (CAN0) Timestamp Counter Value */ 107 #define REG_CAN0_TOCC (*(RwReg *)0x42000028U) /**< \brief (CAN0) Timeout Counter Configuration */ 108 #define REG_CAN0_TOCV (*(RwReg *)0x4200002CU) /**< \brief (CAN0) Timeout Counter Value */ 109 #define REG_CAN0_ECR (*(RoReg *)0x42000040U) /**< \brief (CAN0) Error Counter */ 110 #define REG_CAN0_PSR (*(RoReg *)0x42000044U) /**< \brief (CAN0) Protocol Status */ 111 #define REG_CAN0_TDCR (*(RwReg *)0x42000048U) /**< \brief (CAN0) Extended ID Filter Configuration */ 112 #define REG_CAN0_IR (*(RwReg *)0x42000050U) /**< \brief (CAN0) Interrupt */ 113 #define REG_CAN0_IE (*(RwReg *)0x42000054U) /**< \brief (CAN0) Interrupt Enable */ 114 #define REG_CAN0_ILS (*(RwReg *)0x42000058U) /**< \brief (CAN0) Interrupt Line Select */ 115 #define REG_CAN0_ILE (*(RwReg *)0x4200005CU) /**< \brief (CAN0) Interrupt Line Enable */ 116 #define REG_CAN0_GFC (*(RwReg *)0x42000080U) /**< \brief (CAN0) Global Filter Configuration */ 117 #define REG_CAN0_SIDFC (*(RwReg *)0x42000084U) /**< \brief (CAN0) Standard ID Filter Configuration */ 118 #define REG_CAN0_XIDFC (*(RwReg *)0x42000088U) /**< \brief (CAN0) Extended ID Filter Configuration */ 119 #define REG_CAN0_XIDAM (*(RwReg *)0x42000090U) /**< \brief (CAN0) Extended ID AND Mask */ 120 #define REG_CAN0_HPMS (*(RoReg *)0x42000094U) /**< \brief (CAN0) High Priority Message Status */ 121 #define REG_CAN0_NDAT1 (*(RwReg *)0x42000098U) /**< \brief (CAN0) New Data 1 */ 122 #define REG_CAN0_NDAT2 (*(RwReg *)0x4200009CU) /**< \brief (CAN0) New Data 2 */ 123 #define REG_CAN0_RXF0C (*(RwReg *)0x420000A0U) /**< \brief (CAN0) Rx FIFO 0 Configuration */ 124 #define REG_CAN0_RXF0S (*(RoReg *)0x420000A4U) /**< \brief (CAN0) Rx FIFO 0 Status */ 125 #define REG_CAN0_RXF0A (*(RwReg *)0x420000A8U) /**< \brief (CAN0) Rx FIFO 0 Acknowledge */ 126 #define REG_CAN0_RXBC (*(RwReg *)0x420000ACU) /**< \brief (CAN0) Rx Buffer Configuration */ 127 #define REG_CAN0_RXF1C (*(RwReg *)0x420000B0U) /**< \brief (CAN0) Rx FIFO 1 Configuration */ 128 #define REG_CAN0_RXF1S (*(RoReg *)0x420000B4U) /**< \brief (CAN0) Rx FIFO 1 Status */ 129 #define REG_CAN0_RXF1A (*(RwReg *)0x420000B8U) /**< \brief (CAN0) Rx FIFO 1 Acknowledge */ 130 #define REG_CAN0_RXESC (*(RwReg *)0x420000BCU) /**< \brief (CAN0) Rx Buffer / FIFO Element Size Configuration */ 131 #define REG_CAN0_TXBC (*(RwReg *)0x420000C0U) /**< \brief (CAN0) Tx Buffer Configuration */ 132 #define REG_CAN0_TXFQS (*(RoReg *)0x420000C4U) /**< \brief (CAN0) Tx FIFO / Queue Status */ 133 #define REG_CAN0_TXESC (*(RwReg *)0x420000C8U) /**< \brief (CAN0) Tx Buffer Element Size Configuration */ 134 #define REG_CAN0_TXBRP (*(RoReg *)0x420000CCU) /**< \brief (CAN0) Tx Buffer Request Pending */ 135 #define REG_CAN0_TXBAR (*(RwReg *)0x420000D0U) /**< \brief (CAN0) Tx Buffer Add Request */ 136 #define REG_CAN0_TXBCR (*(RwReg *)0x420000D4U) /**< \brief (CAN0) Tx Buffer Cancellation Request */ 137 #define REG_CAN0_TXBTO (*(RoReg *)0x420000D8U) /**< \brief (CAN0) Tx Buffer Transmission Occurred */ 138 #define REG_CAN0_TXBCF (*(RoReg *)0x420000DCU) /**< \brief (CAN0) Tx Buffer Cancellation Finished */ 139 #define REG_CAN0_TXBTIE (*(RwReg *)0x420000E0U) /**< \brief (CAN0) Tx Buffer Transmission Interrupt Enable */ 140 #define REG_CAN0_TXBCIE (*(RwReg *)0x420000E4U) /**< \brief (CAN0) Tx Buffer Cancellation Finished Interrupt Enable */ 141 #define REG_CAN0_TXEFC (*(RwReg *)0x420000F0U) /**< \brief (CAN0) Tx Event FIFO Configuration */ 142 #define REG_CAN0_TXEFS (*(RoReg *)0x420000F4U) /**< \brief (CAN0) Tx Event FIFO Status */ 143 #define REG_CAN0_TXEFA (*(RwReg *)0x420000F8U) /**< \brief (CAN0) Tx Event FIFO Acknowledge */ 144 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 145 146 /* ========== Instance parameters for CAN0 peripheral ========== */ 147 #define CAN0_CLK_AHB_ID 17 // Index of AHB clock 148 #define CAN0_DMAC_ID_DEBUG 20 // DMA CAN Debug Req 149 #define CAN0_GCLK_ID 27 // Index of Generic Clock 150 #define CAN0_MSG_RAM_ADDR 0x20000000 151 #define CAN0_QOS_RESET_VAL 1 // QOS reset value 152 153 #endif /* _SAMD51_CAN0_INSTANCE_ */ 154
