1 /** 2 * \file 3 * 4 * \brief Instance description for TC5 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAMD21_TC5_INSTANCE_ 30 #define _SAMD21_TC5_INSTANCE_ 31 32 /* ========== Register definition for TC5 peripheral ========== */ 33 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 #define REG_TC5_CTRLA (0x42003400) /**< \brief (TC5) Control A */ 35 #define REG_TC5_READREQ (0x42003402) /**< \brief (TC5) Read Request */ 36 #define REG_TC5_CTRLBCLR (0x42003404) /**< \brief (TC5) Control B Clear */ 37 #define REG_TC5_CTRLBSET (0x42003405) /**< \brief (TC5) Control B Set */ 38 #define REG_TC5_CTRLC (0x42003406) /**< \brief (TC5) Control C */ 39 #define REG_TC5_DBGCTRL (0x42003408) /**< \brief (TC5) Debug Control */ 40 #define REG_TC5_EVCTRL (0x4200340A) /**< \brief (TC5) Event Control */ 41 #define REG_TC5_INTENCLR (0x4200340C) /**< \brief (TC5) Interrupt Enable Clear */ 42 #define REG_TC5_INTENSET (0x4200340D) /**< \brief (TC5) Interrupt Enable Set */ 43 #define REG_TC5_INTFLAG (0x4200340E) /**< \brief (TC5) Interrupt Flag Status and Clear */ 44 #define REG_TC5_STATUS (0x4200340F) /**< \brief (TC5) Status */ 45 #define REG_TC5_COUNT16_COUNT (0x42003410) /**< \brief (TC5) COUNT16 Counter Value */ 46 #define REG_TC5_COUNT16_CC0 (0x42003418) /**< \brief (TC5) COUNT16 Compare/Capture 0 */ 47 #define REG_TC5_COUNT16_CC1 (0x4200341A) /**< \brief (TC5) COUNT16 Compare/Capture 1 */ 48 #define REG_TC5_COUNT32_COUNT (0x42003410) /**< \brief (TC5) COUNT32 Counter Value */ 49 #define REG_TC5_COUNT32_CC0 (0x42003418) /**< \brief (TC5) COUNT32 Compare/Capture 0 */ 50 #define REG_TC5_COUNT32_CC1 (0x4200341C) /**< \brief (TC5) COUNT32 Compare/Capture 1 */ 51 #define REG_TC5_COUNT8_COUNT (0x42003410) /**< \brief (TC5) COUNT8 Counter Value */ 52 #define REG_TC5_COUNT8_PER (0x42003414) /**< \brief (TC5) COUNT8 Period Value */ 53 #define REG_TC5_COUNT8_CC0 (0x42003418) /**< \brief (TC5) COUNT8 Compare/Capture 0 */ 54 #define REG_TC5_COUNT8_CC1 (0x42003419) /**< \brief (TC5) COUNT8 Compare/Capture 1 */ 55 #else 56 #define REG_TC5_CTRLA (*(RwReg16*)0x42003400UL) /**< \brief (TC5) Control A */ 57 #define REG_TC5_READREQ (*(RwReg16*)0x42003402UL) /**< \brief (TC5) Read Request */ 58 #define REG_TC5_CTRLBCLR (*(RwReg8 *)0x42003404UL) /**< \brief (TC5) Control B Clear */ 59 #define REG_TC5_CTRLBSET (*(RwReg8 *)0x42003405UL) /**< \brief (TC5) Control B Set */ 60 #define REG_TC5_CTRLC (*(RwReg8 *)0x42003406UL) /**< \brief (TC5) Control C */ 61 #define REG_TC5_DBGCTRL (*(RwReg8 *)0x42003408UL) /**< \brief (TC5) Debug Control */ 62 #define REG_TC5_EVCTRL (*(RwReg16*)0x4200340AUL) /**< \brief (TC5) Event Control */ 63 #define REG_TC5_INTENCLR (*(RwReg8 *)0x4200340CUL) /**< \brief (TC5) Interrupt Enable Clear */ 64 #define REG_TC5_INTENSET (*(RwReg8 *)0x4200340DUL) /**< \brief (TC5) Interrupt Enable Set */ 65 #define REG_TC5_INTFLAG (*(RwReg8 *)0x4200340EUL) /**< \brief (TC5) Interrupt Flag Status and Clear */ 66 #define REG_TC5_STATUS (*(RoReg8 *)0x4200340FUL) /**< \brief (TC5) Status */ 67 #define REG_TC5_COUNT16_COUNT (*(RwReg16*)0x42003410UL) /**< \brief (TC5) COUNT16 Counter Value */ 68 #define REG_TC5_COUNT16_CC0 (*(RwReg16*)0x42003418UL) /**< \brief (TC5) COUNT16 Compare/Capture 0 */ 69 #define REG_TC5_COUNT16_CC1 (*(RwReg16*)0x4200341AUL) /**< \brief (TC5) COUNT16 Compare/Capture 1 */ 70 #define REG_TC5_COUNT32_COUNT (*(RwReg *)0x42003410UL) /**< \brief (TC5) COUNT32 Counter Value */ 71 #define REG_TC5_COUNT32_CC0 (*(RwReg *)0x42003418UL) /**< \brief (TC5) COUNT32 Compare/Capture 0 */ 72 #define REG_TC5_COUNT32_CC1 (*(RwReg *)0x4200341CUL) /**< \brief (TC5) COUNT32 Compare/Capture 1 */ 73 #define REG_TC5_COUNT8_COUNT (*(RwReg8 *)0x42003410UL) /**< \brief (TC5) COUNT8 Counter Value */ 74 #define REG_TC5_COUNT8_PER (*(RwReg8 *)0x42003414UL) /**< \brief (TC5) COUNT8 Period Value */ 75 #define REG_TC5_COUNT8_CC0 (*(RwReg8 *)0x42003418UL) /**< \brief (TC5) COUNT8 Compare/Capture 0 */ 76 #define REG_TC5_COUNT8_CC1 (*(RwReg8 *)0x42003419UL) /**< \brief (TC5) COUNT8 Compare/Capture 1 */ 77 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 78 79 /* ========== Instance parameters for TC5 peripheral ========== */ 80 #define TC5_CC8_NUM 2 // Number of 8-bit Counters 81 #define TC5_CC16_NUM 2 // Number of 16-bit Counters 82 #define TC5_CC32_NUM 2 // Number of 32-bit Counters 83 #define TC5_DITHERING_EXT 0 // Dithering feature implemented 84 #define TC5_DMAC_ID_MC_0 31 85 #define TC5_DMAC_ID_MC_1 32 86 #define TC5_DMAC_ID_MC_LSB 31 87 #define TC5_DMAC_ID_MC_MSB 32 88 #define TC5_DMAC_ID_MC_SIZE 2 89 #define TC5_DMAC_ID_OVF 30 // Indexes of DMA Overflow trigger 90 #define TC5_GCLK_ID 28 // Index of Generic Clock 91 #define TC5_MASTER 0 92 #define TC5_OW_NUM 2 // Number of Output Waveforms 93 #define TC5_PERIOD_EXT 0 // Period feature implemented 94 #define TC5_SHADOW_EXT 0 // Shadow feature implemented 95 96 #endif /* _SAMD21_TC5_INSTANCE_ */ 97
