1 /** 2 * \file 3 * 4 * \brief Instance description for I2S 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAMD21_I2S_INSTANCE_ 30 #define _SAMD21_I2S_INSTANCE_ 31 32 /* ========== Register definition for I2S peripheral ========== */ 33 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 #define REG_I2S_CTRLA (0x42005000) /**< \brief (I2S) Control A */ 35 #define REG_I2S_CLKCTRL0 (0x42005004) /**< \brief (I2S) Clock Unit 0 Control */ 36 #define REG_I2S_CLKCTRL1 (0x42005008) /**< \brief (I2S) Clock Unit 1 Control */ 37 #define REG_I2S_INTENCLR (0x4200500C) /**< \brief (I2S) Interrupt Enable Clear */ 38 #define REG_I2S_INTENSET (0x42005010) /**< \brief (I2S) Interrupt Enable Set */ 39 #define REG_I2S_INTFLAG (0x42005014) /**< \brief (I2S) Interrupt Flag Status and Clear */ 40 #define REG_I2S_SYNCBUSY (0x42005018) /**< \brief (I2S) Synchronization Status */ 41 #define REG_I2S_SERCTRL0 (0x42005020) /**< \brief (I2S) Serializer 0 Control */ 42 #define REG_I2S_SERCTRL1 (0x42005024) /**< \brief (I2S) Serializer 1 Control */ 43 #define REG_I2S_DATA0 (0x42005030) /**< \brief (I2S) Data 0 */ 44 #define REG_I2S_DATA1 (0x42005034) /**< \brief (I2S) Data 1 */ 45 #else 46 #define REG_I2S_CTRLA (*(RwReg8 *)0x42005000UL) /**< \brief (I2S) Control A */ 47 #define REG_I2S_CLKCTRL0 (*(RwReg *)0x42005004UL) /**< \brief (I2S) Clock Unit 0 Control */ 48 #define REG_I2S_CLKCTRL1 (*(RwReg *)0x42005008UL) /**< \brief (I2S) Clock Unit 1 Control */ 49 #define REG_I2S_INTENCLR (*(RwReg16*)0x4200500CUL) /**< \brief (I2S) Interrupt Enable Clear */ 50 #define REG_I2S_INTENSET (*(RwReg16*)0x42005010UL) /**< \brief (I2S) Interrupt Enable Set */ 51 #define REG_I2S_INTFLAG (*(RwReg16*)0x42005014UL) /**< \brief (I2S) Interrupt Flag Status and Clear */ 52 #define REG_I2S_SYNCBUSY (*(RoReg16*)0x42005018UL) /**< \brief (I2S) Synchronization Status */ 53 #define REG_I2S_SERCTRL0 (*(RwReg *)0x42005020UL) /**< \brief (I2S) Serializer 0 Control */ 54 #define REG_I2S_SERCTRL1 (*(RwReg *)0x42005024UL) /**< \brief (I2S) Serializer 1 Control */ 55 #define REG_I2S_DATA0 (*(RwReg *)0x42005030UL) /**< \brief (I2S) Data 0 */ 56 #define REG_I2S_DATA1 (*(RwReg *)0x42005034UL) /**< \brief (I2S) Data 1 */ 57 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 58 59 /* ========== Instance parameters for I2S peripheral ========== */ 60 #define I2S_CLK_NUM 2 // Number of clock units 61 #define I2S_DMAC_ID_RX_0 41 62 #define I2S_DMAC_ID_RX_1 42 63 #define I2S_DMAC_ID_RX_LSB 41 64 #define I2S_DMAC_ID_RX_MSB 42 65 #define I2S_DMAC_ID_RX_SIZE 2 66 #define I2S_DMAC_ID_TX_0 43 67 #define I2S_DMAC_ID_TX_1 44 68 #define I2S_DMAC_ID_TX_LSB 43 69 #define I2S_DMAC_ID_TX_MSB 44 70 #define I2S_DMAC_ID_TX_SIZE 2 71 #define I2S_GCLK_ID_0 35 72 #define I2S_GCLK_ID_1 36 73 #define I2S_GCLK_ID_LSB 35 74 #define I2S_GCLK_ID_MSB 36 75 #define I2S_GCLK_ID_SIZE 2 76 #define I2S_MAX_SLOTS 8 // Max number of data slots in frame 77 #define I2S_SER_NUM 2 // Number of serializers 78 79 #endif /* _SAMD21_I2S_INSTANCE_ */ 80
