1 /** 2 * \file 3 * 4 * \brief Instance description for GCLK 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAMD21_GCLK_INSTANCE_ 30 #define _SAMD21_GCLK_INSTANCE_ 31 32 /* ========== Register definition for GCLK peripheral ========== */ 33 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 #define REG_GCLK_CTRL (0x40000C00) /**< \brief (GCLK) Control */ 35 #define REG_GCLK_STATUS (0x40000C01) /**< \brief (GCLK) Status */ 36 #define REG_GCLK_CLKCTRL (0x40000C02) /**< \brief (GCLK) Generic Clock Control */ 37 #define REG_GCLK_GENCTRL (0x40000C04) /**< \brief (GCLK) Generic Clock Generator Control */ 38 #define REG_GCLK_GENDIV (0x40000C08) /**< \brief (GCLK) Generic Clock Generator Division */ 39 #else 40 #define REG_GCLK_CTRL (*(RwReg8 *)0x40000C00UL) /**< \brief (GCLK) Control */ 41 #define REG_GCLK_STATUS (*(RoReg8 *)0x40000C01UL) /**< \brief (GCLK) Status */ 42 #define REG_GCLK_CLKCTRL (*(RwReg16*)0x40000C02UL) /**< \brief (GCLK) Generic Clock Control */ 43 #define REG_GCLK_GENCTRL (*(RwReg *)0x40000C04UL) /**< \brief (GCLK) Generic Clock Generator Control */ 44 #define REG_GCLK_GENDIV (*(RwReg *)0x40000C08UL) /**< \brief (GCLK) Generic Clock Generator Division */ 45 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 46 47 /* ========== Instance parameters for GCLK peripheral ========== */ 48 #define GCLK_GENDIV_BITS 16 49 #define GCLK_GEN_NUM 9 // Number of Generic Clock Generators 50 #define GCLK_GEN_NUM_MSB 8 // Number of Generic Clock Generators - 1 51 #define GCLK_GEN_SOURCE_NUM_MSB 8 // Number of Generic Clock Sources - 1 52 #define GCLK_NUM 37 // Number of Generic Clock Users 53 #define GCLK_SOURCE_DFLL48M 7 54 #define GCLK_SOURCE_FDPLL 8 55 #define GCLK_SOURCE_GCLKGEN1 2 56 #define GCLK_SOURCE_GCLKIN 1 57 #define GCLK_SOURCE_NUM 9 // Number of Generic Clock Sources 58 #define GCLK_SOURCE_OSCULP32K 3 59 #define GCLK_SOURCE_OSC8M 6 60 #define GCLK_SOURCE_OSC32K 4 61 #define GCLK_SOURCE_XOSC 0 62 #define GCLK_SOURCE_XOSC32K 5 63 64 #endif /* _SAMD21_GCLK_INSTANCE_ */ 65
