1 /** 2 * \file 3 * 4 * \brief Instance description for EIC 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAMD21_EIC_INSTANCE_ 30 #define _SAMD21_EIC_INSTANCE_ 31 32 /* ========== Register definition for EIC peripheral ========== */ 33 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 #define REG_EIC_CTRL (0x40001800) /**< \brief (EIC) Control */ 35 #define REG_EIC_STATUS (0x40001801) /**< \brief (EIC) Status */ 36 #define REG_EIC_NMICTRL (0x40001802) /**< \brief (EIC) Non-Maskable Interrupt Control */ 37 #define REG_EIC_NMIFLAG (0x40001803) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */ 38 #define REG_EIC_EVCTRL (0x40001804) /**< \brief (EIC) Event Control */ 39 #define REG_EIC_INTENCLR (0x40001808) /**< \brief (EIC) Interrupt Enable Clear */ 40 #define REG_EIC_INTENSET (0x4000180C) /**< \brief (EIC) Interrupt Enable Set */ 41 #define REG_EIC_INTFLAG (0x40001810) /**< \brief (EIC) Interrupt Flag Status and Clear */ 42 #define REG_EIC_WAKEUP (0x40001814) /**< \brief (EIC) Wake-Up Enable */ 43 #define REG_EIC_CONFIG0 (0x40001818) /**< \brief (EIC) Configuration 0 */ 44 #define REG_EIC_CONFIG1 (0x4000181C) /**< \brief (EIC) Configuration 1 */ 45 #else 46 #define REG_EIC_CTRL (*(RwReg8 *)0x40001800UL) /**< \brief (EIC) Control */ 47 #define REG_EIC_STATUS (*(RoReg8 *)0x40001801UL) /**< \brief (EIC) Status */ 48 #define REG_EIC_NMICTRL (*(RwReg8 *)0x40001802UL) /**< \brief (EIC) Non-Maskable Interrupt Control */ 49 #define REG_EIC_NMIFLAG (*(RwReg8 *)0x40001803UL) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */ 50 #define REG_EIC_EVCTRL (*(RwReg *)0x40001804UL) /**< \brief (EIC) Event Control */ 51 #define REG_EIC_INTENCLR (*(RwReg *)0x40001808UL) /**< \brief (EIC) Interrupt Enable Clear */ 52 #define REG_EIC_INTENSET (*(RwReg *)0x4000180CUL) /**< \brief (EIC) Interrupt Enable Set */ 53 #define REG_EIC_INTFLAG (*(RwReg *)0x40001810UL) /**< \brief (EIC) Interrupt Flag Status and Clear */ 54 #define REG_EIC_WAKEUP (*(RwReg *)0x40001814UL) /**< \brief (EIC) Wake-Up Enable */ 55 #define REG_EIC_CONFIG0 (*(RwReg *)0x40001818UL) /**< \brief (EIC) Configuration 0 */ 56 #define REG_EIC_CONFIG1 (*(RwReg *)0x4000181CUL) /**< \brief (EIC) Configuration 1 */ 57 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 58 59 /* ========== Instance parameters for EIC peripheral ========== */ 60 #define EIC_CONFIG_NUM 2 // Number of CONFIG registers 61 #define EIC_GCLK_ID 5 // Index of Generic Clock 62 63 #endif /* _SAMD21_EIC_INSTANCE_ */ 64
