1 /** 2 * \file 3 * 4 * \brief Component description for PAC 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAMD21_PAC_COMPONENT_ 30 #define _SAMD21_PAC_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR PAC */ 34 /* ========================================================================== */ 35 /** \addtogroup SAMD21_PAC Peripheral Access Controller */ 36 /*@{*/ 37 38 #define PAC_U2211 39 #define REV_PAC 0x101 40 41 /* -------- PAC_WPCLR : (PAC Offset: 0x0) (R/W 32) Write Protection Clear -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t :1; /*!< bit: 0 Reserved */ 46 uint32_t WP:31; /*!< bit: 1..31 Write Protection Clear */ 47 } bit; /*!< Structure used for bit access */ 48 uint32_t reg; /*!< Type used for register access */ 49 } PAC_WPCLR_Type; 50 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 51 52 #define PAC_WPCLR_OFFSET 0x0 /**< \brief (PAC_WPCLR offset) Write Protection Clear */ 53 #define PAC_WPCLR_RESETVALUE _U_(0x00000000) /**< \brief (PAC_WPCLR reset_value) Write Protection Clear */ 54 55 #define PAC_WPCLR_WP_Pos 1 /**< \brief (PAC_WPCLR) Write Protection Clear */ 56 #define PAC_WPCLR_WP_Msk (_U_(0x7FFFFFFF) << PAC_WPCLR_WP_Pos) 57 #define PAC_WPCLR_WP(value) (PAC_WPCLR_WP_Msk & ((value) << PAC_WPCLR_WP_Pos)) 58 #define PAC_WPCLR_MASK _U_(0xFFFFFFFE) /**< \brief (PAC_WPCLR) MASK Register */ 59 60 /* -------- PAC_WPSET : (PAC Offset: 0x4) (R/W 32) Write Protection Set -------- */ 61 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 62 typedef union { 63 struct { 64 uint32_t :1; /*!< bit: 0 Reserved */ 65 uint32_t WP:31; /*!< bit: 1..31 Write Protection Set */ 66 } bit; /*!< Structure used for bit access */ 67 uint32_t reg; /*!< Type used for register access */ 68 } PAC_WPSET_Type; 69 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 70 71 #define PAC_WPSET_OFFSET 0x4 /**< \brief (PAC_WPSET offset) Write Protection Set */ 72 #define PAC_WPSET_RESETVALUE _U_(0x00000000) /**< \brief (PAC_WPSET reset_value) Write Protection Set */ 73 74 #define PAC_WPSET_WP_Pos 1 /**< \brief (PAC_WPSET) Write Protection Set */ 75 #define PAC_WPSET_WP_Msk (_U_(0x7FFFFFFF) << PAC_WPSET_WP_Pos) 76 #define PAC_WPSET_WP(value) (PAC_WPSET_WP_Msk & ((value) << PAC_WPSET_WP_Pos)) 77 #define PAC_WPSET_MASK _U_(0xFFFFFFFE) /**< \brief (PAC_WPSET) MASK Register */ 78 79 /** \brief PAC hardware registers */ 80 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 81 typedef struct { 82 __IO PAC_WPCLR_Type WPCLR; /**< \brief Offset: 0x0 (R/W 32) Write Protection Clear */ 83 __IO PAC_WPSET_Type WPSET; /**< \brief Offset: 0x4 (R/W 32) Write Protection Set */ 84 } Pac; 85 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 86 87 /*@}*/ 88 89 #endif /* _SAMD21_PAC_COMPONENT_ */ 90
