1 /** 2 * \file 3 * 4 * \brief Component description for I2S 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAMD21_I2S_COMPONENT_ 30 #define _SAMD21_I2S_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR I2S */ 34 /* ========================================================================== */ 35 /** \addtogroup SAMD21_I2S Inter-IC Sound Interface */ 36 /*@{*/ 37 38 #define I2S_U2224 39 #define REV_I2S 0x102 40 41 /* -------- I2S_CTRLA : (I2S Offset: 0x00) (R/W 8) Control A -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint8_t SWRST:1; /*!< bit: 0 Software Reset */ 46 uint8_t ENABLE:1; /*!< bit: 1 Enable */ 47 uint8_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable */ 48 uint8_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable */ 49 uint8_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable */ 50 uint8_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable */ 51 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 52 } bit; /*!< Structure used for bit access */ 53 struct { 54 uint8_t :2; /*!< bit: 0.. 1 Reserved */ 55 uint8_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable */ 56 uint8_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable */ 57 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 58 } vec; /*!< Structure used for vec access */ 59 uint8_t reg; /*!< Type used for register access */ 60 } I2S_CTRLA_Type; 61 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 62 63 #define I2S_CTRLA_OFFSET 0x00 /**< \brief (I2S_CTRLA offset) Control A */ 64 #define I2S_CTRLA_RESETVALUE _U_(0x00) /**< \brief (I2S_CTRLA reset_value) Control A */ 65 66 #define I2S_CTRLA_SWRST_Pos 0 /**< \brief (I2S_CTRLA) Software Reset */ 67 #define I2S_CTRLA_SWRST (_U_(0x1) << I2S_CTRLA_SWRST_Pos) 68 #define I2S_CTRLA_ENABLE_Pos 1 /**< \brief (I2S_CTRLA) Enable */ 69 #define I2S_CTRLA_ENABLE (_U_(0x1) << I2S_CTRLA_ENABLE_Pos) 70 #define I2S_CTRLA_CKEN0_Pos 2 /**< \brief (I2S_CTRLA) Clock Unit 0 Enable */ 71 #define I2S_CTRLA_CKEN0 (1 << I2S_CTRLA_CKEN0_Pos) 72 #define I2S_CTRLA_CKEN1_Pos 3 /**< \brief (I2S_CTRLA) Clock Unit 1 Enable */ 73 #define I2S_CTRLA_CKEN1 (1 << I2S_CTRLA_CKEN1_Pos) 74 #define I2S_CTRLA_CKEN_Pos 2 /**< \brief (I2S_CTRLA) Clock Unit x Enable */ 75 #define I2S_CTRLA_CKEN_Msk (_U_(0x3) << I2S_CTRLA_CKEN_Pos) 76 #define I2S_CTRLA_CKEN(value) (I2S_CTRLA_CKEN_Msk & ((value) << I2S_CTRLA_CKEN_Pos)) 77 #define I2S_CTRLA_SEREN0_Pos 4 /**< \brief (I2S_CTRLA) Serializer 0 Enable */ 78 #define I2S_CTRLA_SEREN0 (1 << I2S_CTRLA_SEREN0_Pos) 79 #define I2S_CTRLA_SEREN1_Pos 5 /**< \brief (I2S_CTRLA) Serializer 1 Enable */ 80 #define I2S_CTRLA_SEREN1 (1 << I2S_CTRLA_SEREN1_Pos) 81 #define I2S_CTRLA_SEREN_Pos 4 /**< \brief (I2S_CTRLA) Serializer x Enable */ 82 #define I2S_CTRLA_SEREN_Msk (_U_(0x3) << I2S_CTRLA_SEREN_Pos) 83 #define I2S_CTRLA_SEREN(value) (I2S_CTRLA_SEREN_Msk & ((value) << I2S_CTRLA_SEREN_Pos)) 84 #define I2S_CTRLA_MASK _U_(0x3F) /**< \brief (I2S_CTRLA) MASK Register */ 85 86 /* -------- I2S_CLKCTRL : (I2S Offset: 0x04) (R/W 32) Clock Unit n Control -------- */ 87 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 88 typedef union { 89 struct { 90 uint32_t SLOTSIZE:2; /*!< bit: 0.. 1 Slot Size */ 91 uint32_t NBSLOTS:3; /*!< bit: 2.. 4 Number of Slots in Frame */ 92 uint32_t FSWIDTH:2; /*!< bit: 5.. 6 Frame Sync Width */ 93 uint32_t BITDELAY:1; /*!< bit: 7 Data Delay from Frame Sync */ 94 uint32_t FSSEL:1; /*!< bit: 8 Frame Sync Select */ 95 uint32_t :2; /*!< bit: 9..10 Reserved */ 96 uint32_t FSINV:1; /*!< bit: 11 Frame Sync Invert */ 97 uint32_t SCKSEL:1; /*!< bit: 12 Serial Clock Select */ 98 uint32_t :3; /*!< bit: 13..15 Reserved */ 99 uint32_t MCKSEL:1; /*!< bit: 16 Master Clock Select */ 100 uint32_t :1; /*!< bit: 17 Reserved */ 101 uint32_t MCKEN:1; /*!< bit: 18 Master Clock Enable */ 102 uint32_t MCKDIV:5; /*!< bit: 19..23 Master Clock Division Factor */ 103 uint32_t MCKOUTDIV:5; /*!< bit: 24..28 Master Clock Output Division Factor */ 104 uint32_t FSOUTINV:1; /*!< bit: 29 Frame Sync Output Invert */ 105 uint32_t SCKOUTINV:1; /*!< bit: 30 Serial Clock Output Invert */ 106 uint32_t MCKOUTINV:1; /*!< bit: 31 Master Clock Output Invert */ 107 } bit; /*!< Structure used for bit access */ 108 uint32_t reg; /*!< Type used for register access */ 109 } I2S_CLKCTRL_Type; 110 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 111 112 #define I2S_CLKCTRL_OFFSET 0x04 /**< \brief (I2S_CLKCTRL offset) Clock Unit n Control */ 113 #define I2S_CLKCTRL_RESETVALUE _U_(0x00000000) /**< \brief (I2S_CLKCTRL reset_value) Clock Unit n Control */ 114 115 #define I2S_CLKCTRL_SLOTSIZE_Pos 0 /**< \brief (I2S_CLKCTRL) Slot Size */ 116 #define I2S_CLKCTRL_SLOTSIZE_Msk (_U_(0x3) << I2S_CLKCTRL_SLOTSIZE_Pos) 117 #define I2S_CLKCTRL_SLOTSIZE(value) (I2S_CLKCTRL_SLOTSIZE_Msk & ((value) << I2S_CLKCTRL_SLOTSIZE_Pos)) 118 #define I2S_CLKCTRL_SLOTSIZE_8_Val _U_(0x0) /**< \brief (I2S_CLKCTRL) 8-bit Slot for Clock Unit n */ 119 #define I2S_CLKCTRL_SLOTSIZE_16_Val _U_(0x1) /**< \brief (I2S_CLKCTRL) 16-bit Slot for Clock Unit n */ 120 #define I2S_CLKCTRL_SLOTSIZE_24_Val _U_(0x2) /**< \brief (I2S_CLKCTRL) 24-bit Slot for Clock Unit n */ 121 #define I2S_CLKCTRL_SLOTSIZE_32_Val _U_(0x3) /**< \brief (I2S_CLKCTRL) 32-bit Slot for Clock Unit n */ 122 #define I2S_CLKCTRL_SLOTSIZE_8 (I2S_CLKCTRL_SLOTSIZE_8_Val << I2S_CLKCTRL_SLOTSIZE_Pos) 123 #define I2S_CLKCTRL_SLOTSIZE_16 (I2S_CLKCTRL_SLOTSIZE_16_Val << I2S_CLKCTRL_SLOTSIZE_Pos) 124 #define I2S_CLKCTRL_SLOTSIZE_24 (I2S_CLKCTRL_SLOTSIZE_24_Val << I2S_CLKCTRL_SLOTSIZE_Pos) 125 #define I2S_CLKCTRL_SLOTSIZE_32 (I2S_CLKCTRL_SLOTSIZE_32_Val << I2S_CLKCTRL_SLOTSIZE_Pos) 126 #define I2S_CLKCTRL_NBSLOTS_Pos 2 /**< \brief (I2S_CLKCTRL) Number of Slots in Frame */ 127 #define I2S_CLKCTRL_NBSLOTS_Msk (_U_(0x7) << I2S_CLKCTRL_NBSLOTS_Pos) 128 #define I2S_CLKCTRL_NBSLOTS(value) (I2S_CLKCTRL_NBSLOTS_Msk & ((value) << I2S_CLKCTRL_NBSLOTS_Pos)) 129 #define I2S_CLKCTRL_FSWIDTH_Pos 5 /**< \brief (I2S_CLKCTRL) Frame Sync Width */ 130 #define I2S_CLKCTRL_FSWIDTH_Msk (_U_(0x3) << I2S_CLKCTRL_FSWIDTH_Pos) 131 #define I2S_CLKCTRL_FSWIDTH(value) (I2S_CLKCTRL_FSWIDTH_Msk & ((value) << I2S_CLKCTRL_FSWIDTH_Pos)) 132 #define I2S_CLKCTRL_FSWIDTH_SLOT_Val _U_(0x0) /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Slot wide (default for I2S protocol) */ 133 #define I2S_CLKCTRL_FSWIDTH_HALF_Val _U_(0x1) /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is half a Frame wide */ 134 #define I2S_CLKCTRL_FSWIDTH_BIT_Val _U_(0x2) /**< \brief (I2S_CLKCTRL) Frame Sync Pulse is 1 Bit wide */ 135 #define I2S_CLKCTRL_FSWIDTH_BURST_Val _U_(0x3) /**< \brief (I2S_CLKCTRL) Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested */ 136 #define I2S_CLKCTRL_FSWIDTH_SLOT (I2S_CLKCTRL_FSWIDTH_SLOT_Val << I2S_CLKCTRL_FSWIDTH_Pos) 137 #define I2S_CLKCTRL_FSWIDTH_HALF (I2S_CLKCTRL_FSWIDTH_HALF_Val << I2S_CLKCTRL_FSWIDTH_Pos) 138 #define I2S_CLKCTRL_FSWIDTH_BIT (I2S_CLKCTRL_FSWIDTH_BIT_Val << I2S_CLKCTRL_FSWIDTH_Pos) 139 #define I2S_CLKCTRL_FSWIDTH_BURST (I2S_CLKCTRL_FSWIDTH_BURST_Val << I2S_CLKCTRL_FSWIDTH_Pos) 140 #define I2S_CLKCTRL_BITDELAY_Pos 7 /**< \brief (I2S_CLKCTRL) Data Delay from Frame Sync */ 141 #define I2S_CLKCTRL_BITDELAY (_U_(0x1) << I2S_CLKCTRL_BITDELAY_Pos) 142 #define I2S_CLKCTRL_BITDELAY_LJ_Val _U_(0x0) /**< \brief (I2S_CLKCTRL) Left Justified (0 Bit Delay) */ 143 #define I2S_CLKCTRL_BITDELAY_I2S_Val _U_(0x1) /**< \brief (I2S_CLKCTRL) I2S (1 Bit Delay) */ 144 #define I2S_CLKCTRL_BITDELAY_LJ (I2S_CLKCTRL_BITDELAY_LJ_Val << I2S_CLKCTRL_BITDELAY_Pos) 145 #define I2S_CLKCTRL_BITDELAY_I2S (I2S_CLKCTRL_BITDELAY_I2S_Val << I2S_CLKCTRL_BITDELAY_Pos) 146 #define I2S_CLKCTRL_FSSEL_Pos 8 /**< \brief (I2S_CLKCTRL) Frame Sync Select */ 147 #define I2S_CLKCTRL_FSSEL (_U_(0x1) << I2S_CLKCTRL_FSSEL_Pos) 148 #define I2S_CLKCTRL_FSSEL_SCKDIV_Val _U_(0x0) /**< \brief (I2S_CLKCTRL) Divided Serial Clock n is used as Frame Sync n source */ 149 #define I2S_CLKCTRL_FSSEL_FSPIN_Val _U_(0x1) /**< \brief (I2S_CLKCTRL) FSn input pin is used as Frame Sync n source */ 150 #define I2S_CLKCTRL_FSSEL_SCKDIV (I2S_CLKCTRL_FSSEL_SCKDIV_Val << I2S_CLKCTRL_FSSEL_Pos) 151 #define I2S_CLKCTRL_FSSEL_FSPIN (I2S_CLKCTRL_FSSEL_FSPIN_Val << I2S_CLKCTRL_FSSEL_Pos) 152 #define I2S_CLKCTRL_FSINV_Pos 11 /**< \brief (I2S_CLKCTRL) Frame Sync Invert */ 153 #define I2S_CLKCTRL_FSINV (_U_(0x1) << I2S_CLKCTRL_FSINV_Pos) 154 #define I2S_CLKCTRL_SCKSEL_Pos 12 /**< \brief (I2S_CLKCTRL) Serial Clock Select */ 155 #define I2S_CLKCTRL_SCKSEL (_U_(0x1) << I2S_CLKCTRL_SCKSEL_Pos) 156 #define I2S_CLKCTRL_SCKSEL_MCKDIV_Val _U_(0x0) /**< \brief (I2S_CLKCTRL) Divided Master Clock n is used as Serial Clock n source */ 157 #define I2S_CLKCTRL_SCKSEL_SCKPIN_Val _U_(0x1) /**< \brief (I2S_CLKCTRL) SCKn input pin is used as Serial Clock n source */ 158 #define I2S_CLKCTRL_SCKSEL_MCKDIV (I2S_CLKCTRL_SCKSEL_MCKDIV_Val << I2S_CLKCTRL_SCKSEL_Pos) 159 #define I2S_CLKCTRL_SCKSEL_SCKPIN (I2S_CLKCTRL_SCKSEL_SCKPIN_Val << I2S_CLKCTRL_SCKSEL_Pos) 160 #define I2S_CLKCTRL_MCKSEL_Pos 16 /**< \brief (I2S_CLKCTRL) Master Clock Select */ 161 #define I2S_CLKCTRL_MCKSEL (_U_(0x1) << I2S_CLKCTRL_MCKSEL_Pos) 162 #define I2S_CLKCTRL_MCKSEL_GCLK_Val _U_(0x0) /**< \brief (I2S_CLKCTRL) GCLK_I2S_n is used as Master Clock n source */ 163 #define I2S_CLKCTRL_MCKSEL_MCKPIN_Val _U_(0x1) /**< \brief (I2S_CLKCTRL) MCKn input pin is used as Master Clock n source */ 164 #define I2S_CLKCTRL_MCKSEL_GCLK (I2S_CLKCTRL_MCKSEL_GCLK_Val << I2S_CLKCTRL_MCKSEL_Pos) 165 #define I2S_CLKCTRL_MCKSEL_MCKPIN (I2S_CLKCTRL_MCKSEL_MCKPIN_Val << I2S_CLKCTRL_MCKSEL_Pos) 166 #define I2S_CLKCTRL_MCKEN_Pos 18 /**< \brief (I2S_CLKCTRL) Master Clock Enable */ 167 #define I2S_CLKCTRL_MCKEN (_U_(0x1) << I2S_CLKCTRL_MCKEN_Pos) 168 #define I2S_CLKCTRL_MCKDIV_Pos 19 /**< \brief (I2S_CLKCTRL) Master Clock Division Factor */ 169 #define I2S_CLKCTRL_MCKDIV_Msk (_U_(0x1F) << I2S_CLKCTRL_MCKDIV_Pos) 170 #define I2S_CLKCTRL_MCKDIV(value) (I2S_CLKCTRL_MCKDIV_Msk & ((value) << I2S_CLKCTRL_MCKDIV_Pos)) 171 #define I2S_CLKCTRL_MCKOUTDIV_Pos 24 /**< \brief (I2S_CLKCTRL) Master Clock Output Division Factor */ 172 #define I2S_CLKCTRL_MCKOUTDIV_Msk (_U_(0x1F) << I2S_CLKCTRL_MCKOUTDIV_Pos) 173 #define I2S_CLKCTRL_MCKOUTDIV(value) (I2S_CLKCTRL_MCKOUTDIV_Msk & ((value) << I2S_CLKCTRL_MCKOUTDIV_Pos)) 174 #define I2S_CLKCTRL_FSOUTINV_Pos 29 /**< \brief (I2S_CLKCTRL) Frame Sync Output Invert */ 175 #define I2S_CLKCTRL_FSOUTINV (_U_(0x1) << I2S_CLKCTRL_FSOUTINV_Pos) 176 #define I2S_CLKCTRL_SCKOUTINV_Pos 30 /**< \brief (I2S_CLKCTRL) Serial Clock Output Invert */ 177 #define I2S_CLKCTRL_SCKOUTINV (_U_(0x1) << I2S_CLKCTRL_SCKOUTINV_Pos) 178 #define I2S_CLKCTRL_MCKOUTINV_Pos 31 /**< \brief (I2S_CLKCTRL) Master Clock Output Invert */ 179 #define I2S_CLKCTRL_MCKOUTINV (_U_(0x1) << I2S_CLKCTRL_MCKOUTINV_Pos) 180 #define I2S_CLKCTRL_MASK _U_(0xFFFD19FF) /**< \brief (I2S_CLKCTRL) MASK Register */ 181 182 /* -------- I2S_INTENCLR : (I2S Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */ 183 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 184 typedef union { 185 struct { 186 uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */ 187 uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */ 188 uint16_t :2; /*!< bit: 2.. 3 Reserved */ 189 uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */ 190 uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */ 191 uint16_t :2; /*!< bit: 6.. 7 Reserved */ 192 uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */ 193 uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */ 194 uint16_t :2; /*!< bit: 10..11 Reserved */ 195 uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */ 196 uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */ 197 uint16_t :2; /*!< bit: 14..15 Reserved */ 198 } bit; /*!< Structure used for bit access */ 199 struct { 200 uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */ 201 uint16_t :2; /*!< bit: 2.. 3 Reserved */ 202 uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */ 203 uint16_t :2; /*!< bit: 6.. 7 Reserved */ 204 uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */ 205 uint16_t :2; /*!< bit: 10..11 Reserved */ 206 uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */ 207 uint16_t :2; /*!< bit: 14..15 Reserved */ 208 } vec; /*!< Structure used for vec access */ 209 uint16_t reg; /*!< Type used for register access */ 210 } I2S_INTENCLR_Type; 211 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 212 213 #define I2S_INTENCLR_OFFSET 0x0C /**< \brief (I2S_INTENCLR offset) Interrupt Enable Clear */ 214 #define I2S_INTENCLR_RESETVALUE _U_(0x0000) /**< \brief (I2S_INTENCLR reset_value) Interrupt Enable Clear */ 215 216 #define I2S_INTENCLR_RXRDY0_Pos 0 /**< \brief (I2S_INTENCLR) Receive Ready 0 Interrupt Enable */ 217 #define I2S_INTENCLR_RXRDY0 (1 << I2S_INTENCLR_RXRDY0_Pos) 218 #define I2S_INTENCLR_RXRDY1_Pos 1 /**< \brief (I2S_INTENCLR) Receive Ready 1 Interrupt Enable */ 219 #define I2S_INTENCLR_RXRDY1 (1 << I2S_INTENCLR_RXRDY1_Pos) 220 #define I2S_INTENCLR_RXRDY_Pos 0 /**< \brief (I2S_INTENCLR) Receive Ready x Interrupt Enable */ 221 #define I2S_INTENCLR_RXRDY_Msk (_U_(0x3) << I2S_INTENCLR_RXRDY_Pos) 222 #define I2S_INTENCLR_RXRDY(value) (I2S_INTENCLR_RXRDY_Msk & ((value) << I2S_INTENCLR_RXRDY_Pos)) 223 #define I2S_INTENCLR_RXOR0_Pos 4 /**< \brief (I2S_INTENCLR) Receive Overrun 0 Interrupt Enable */ 224 #define I2S_INTENCLR_RXOR0 (1 << I2S_INTENCLR_RXOR0_Pos) 225 #define I2S_INTENCLR_RXOR1_Pos 5 /**< \brief (I2S_INTENCLR) Receive Overrun 1 Interrupt Enable */ 226 #define I2S_INTENCLR_RXOR1 (1 << I2S_INTENCLR_RXOR1_Pos) 227 #define I2S_INTENCLR_RXOR_Pos 4 /**< \brief (I2S_INTENCLR) Receive Overrun x Interrupt Enable */ 228 #define I2S_INTENCLR_RXOR_Msk (_U_(0x3) << I2S_INTENCLR_RXOR_Pos) 229 #define I2S_INTENCLR_RXOR(value) (I2S_INTENCLR_RXOR_Msk & ((value) << I2S_INTENCLR_RXOR_Pos)) 230 #define I2S_INTENCLR_TXRDY0_Pos 8 /**< \brief (I2S_INTENCLR) Transmit Ready 0 Interrupt Enable */ 231 #define I2S_INTENCLR_TXRDY0 (1 << I2S_INTENCLR_TXRDY0_Pos) 232 #define I2S_INTENCLR_TXRDY1_Pos 9 /**< \brief (I2S_INTENCLR) Transmit Ready 1 Interrupt Enable */ 233 #define I2S_INTENCLR_TXRDY1 (1 << I2S_INTENCLR_TXRDY1_Pos) 234 #define I2S_INTENCLR_TXRDY_Pos 8 /**< \brief (I2S_INTENCLR) Transmit Ready x Interrupt Enable */ 235 #define I2S_INTENCLR_TXRDY_Msk (_U_(0x3) << I2S_INTENCLR_TXRDY_Pos) 236 #define I2S_INTENCLR_TXRDY(value) (I2S_INTENCLR_TXRDY_Msk & ((value) << I2S_INTENCLR_TXRDY_Pos)) 237 #define I2S_INTENCLR_TXUR0_Pos 12 /**< \brief (I2S_INTENCLR) Transmit Underrun 0 Interrupt Enable */ 238 #define I2S_INTENCLR_TXUR0 (1 << I2S_INTENCLR_TXUR0_Pos) 239 #define I2S_INTENCLR_TXUR1_Pos 13 /**< \brief (I2S_INTENCLR) Transmit Underrun 1 Interrupt Enable */ 240 #define I2S_INTENCLR_TXUR1 (1 << I2S_INTENCLR_TXUR1_Pos) 241 #define I2S_INTENCLR_TXUR_Pos 12 /**< \brief (I2S_INTENCLR) Transmit Underrun x Interrupt Enable */ 242 #define I2S_INTENCLR_TXUR_Msk (_U_(0x3) << I2S_INTENCLR_TXUR_Pos) 243 #define I2S_INTENCLR_TXUR(value) (I2S_INTENCLR_TXUR_Msk & ((value) << I2S_INTENCLR_TXUR_Pos)) 244 #define I2S_INTENCLR_MASK _U_(0x3333) /**< \brief (I2S_INTENCLR) MASK Register */ 245 246 /* -------- I2S_INTENSET : (I2S Offset: 0x10) (R/W 16) Interrupt Enable Set -------- */ 247 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 248 typedef union { 249 struct { 250 uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */ 251 uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */ 252 uint16_t :2; /*!< bit: 2.. 3 Reserved */ 253 uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */ 254 uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */ 255 uint16_t :2; /*!< bit: 6.. 7 Reserved */ 256 uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */ 257 uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */ 258 uint16_t :2; /*!< bit: 10..11 Reserved */ 259 uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */ 260 uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */ 261 uint16_t :2; /*!< bit: 14..15 Reserved */ 262 } bit; /*!< Structure used for bit access */ 263 struct { 264 uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */ 265 uint16_t :2; /*!< bit: 2.. 3 Reserved */ 266 uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */ 267 uint16_t :2; /*!< bit: 6.. 7 Reserved */ 268 uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */ 269 uint16_t :2; /*!< bit: 10..11 Reserved */ 270 uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */ 271 uint16_t :2; /*!< bit: 14..15 Reserved */ 272 } vec; /*!< Structure used for vec access */ 273 uint16_t reg; /*!< Type used for register access */ 274 } I2S_INTENSET_Type; 275 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 276 277 #define I2S_INTENSET_OFFSET 0x10 /**< \brief (I2S_INTENSET offset) Interrupt Enable Set */ 278 #define I2S_INTENSET_RESETVALUE _U_(0x0000) /**< \brief (I2S_INTENSET reset_value) Interrupt Enable Set */ 279 280 #define I2S_INTENSET_RXRDY0_Pos 0 /**< \brief (I2S_INTENSET) Receive Ready 0 Interrupt Enable */ 281 #define I2S_INTENSET_RXRDY0 (1 << I2S_INTENSET_RXRDY0_Pos) 282 #define I2S_INTENSET_RXRDY1_Pos 1 /**< \brief (I2S_INTENSET) Receive Ready 1 Interrupt Enable */ 283 #define I2S_INTENSET_RXRDY1 (1 << I2S_INTENSET_RXRDY1_Pos) 284 #define I2S_INTENSET_RXRDY_Pos 0 /**< \brief (I2S_INTENSET) Receive Ready x Interrupt Enable */ 285 #define I2S_INTENSET_RXRDY_Msk (_U_(0x3) << I2S_INTENSET_RXRDY_Pos) 286 #define I2S_INTENSET_RXRDY(value) (I2S_INTENSET_RXRDY_Msk & ((value) << I2S_INTENSET_RXRDY_Pos)) 287 #define I2S_INTENSET_RXOR0_Pos 4 /**< \brief (I2S_INTENSET) Receive Overrun 0 Interrupt Enable */ 288 #define I2S_INTENSET_RXOR0 (1 << I2S_INTENSET_RXOR0_Pos) 289 #define I2S_INTENSET_RXOR1_Pos 5 /**< \brief (I2S_INTENSET) Receive Overrun 1 Interrupt Enable */ 290 #define I2S_INTENSET_RXOR1 (1 << I2S_INTENSET_RXOR1_Pos) 291 #define I2S_INTENSET_RXOR_Pos 4 /**< \brief (I2S_INTENSET) Receive Overrun x Interrupt Enable */ 292 #define I2S_INTENSET_RXOR_Msk (_U_(0x3) << I2S_INTENSET_RXOR_Pos) 293 #define I2S_INTENSET_RXOR(value) (I2S_INTENSET_RXOR_Msk & ((value) << I2S_INTENSET_RXOR_Pos)) 294 #define I2S_INTENSET_TXRDY0_Pos 8 /**< \brief (I2S_INTENSET) Transmit Ready 0 Interrupt Enable */ 295 #define I2S_INTENSET_TXRDY0 (1 << I2S_INTENSET_TXRDY0_Pos) 296 #define I2S_INTENSET_TXRDY1_Pos 9 /**< \brief (I2S_INTENSET) Transmit Ready 1 Interrupt Enable */ 297 #define I2S_INTENSET_TXRDY1 (1 << I2S_INTENSET_TXRDY1_Pos) 298 #define I2S_INTENSET_TXRDY_Pos 8 /**< \brief (I2S_INTENSET) Transmit Ready x Interrupt Enable */ 299 #define I2S_INTENSET_TXRDY_Msk (_U_(0x3) << I2S_INTENSET_TXRDY_Pos) 300 #define I2S_INTENSET_TXRDY(value) (I2S_INTENSET_TXRDY_Msk & ((value) << I2S_INTENSET_TXRDY_Pos)) 301 #define I2S_INTENSET_TXUR0_Pos 12 /**< \brief (I2S_INTENSET) Transmit Underrun 0 Interrupt Enable */ 302 #define I2S_INTENSET_TXUR0 (1 << I2S_INTENSET_TXUR0_Pos) 303 #define I2S_INTENSET_TXUR1_Pos 13 /**< \brief (I2S_INTENSET) Transmit Underrun 1 Interrupt Enable */ 304 #define I2S_INTENSET_TXUR1 (1 << I2S_INTENSET_TXUR1_Pos) 305 #define I2S_INTENSET_TXUR_Pos 12 /**< \brief (I2S_INTENSET) Transmit Underrun x Interrupt Enable */ 306 #define I2S_INTENSET_TXUR_Msk (_U_(0x3) << I2S_INTENSET_TXUR_Pos) 307 #define I2S_INTENSET_TXUR(value) (I2S_INTENSET_TXUR_Msk & ((value) << I2S_INTENSET_TXUR_Pos)) 308 #define I2S_INTENSET_MASK _U_(0x3333) /**< \brief (I2S_INTENSET) MASK Register */ 309 310 /* -------- I2S_INTFLAG : (I2S Offset: 0x14) (R/W 16) Interrupt Flag Status and Clear -------- */ 311 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 312 typedef union { // __I to avoid read-modify-write on write-to-clear register 313 struct { 314 __I uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 */ 315 __I uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 */ 316 __I uint16_t Reserved1:2; /*!< bit: 2.. 3 Reserved */ 317 __I uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 */ 318 __I uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 */ 319 __I uint16_t Reserved2:2; /*!< bit: 6.. 7 Reserved */ 320 __I uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 */ 321 __I uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 */ 322 __I uint16_t Reserved3:2; /*!< bit: 10..11 Reserved */ 323 __I uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 */ 324 __I uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 */ 325 __I uint16_t Reserved4:2; /*!< bit: 14..15 Reserved */ 326 } bit; /*!< Structure used for bit access */ 327 struct { 328 __I uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x */ 329 __I uint16_t Reserved1:2; /*!< bit: 2.. 3 Reserved */ 330 __I uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x */ 331 __I uint16_t Reserved2:2; /*!< bit: 6.. 7 Reserved */ 332 __I uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x */ 333 __I uint16_t Reserved3:2; /*!< bit: 10..11 Reserved */ 334 __I uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x */ 335 __I uint16_t Reserved4:2; /*!< bit: 14..15 Reserved */ 336 } vec; /*!< Structure used for vec access */ 337 uint16_t reg; /*!< Type used for register access */ 338 } I2S_INTFLAG_Type; 339 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 340 341 #define I2S_INTFLAG_OFFSET 0x14 /**< \brief (I2S_INTFLAG offset) Interrupt Flag Status and Clear */ 342 #define I2S_INTFLAG_RESETVALUE _U_(0x0000) /**< \brief (I2S_INTFLAG reset_value) Interrupt Flag Status and Clear */ 343 344 #define I2S_INTFLAG_RXRDY0_Pos 0 /**< \brief (I2S_INTFLAG) Receive Ready 0 */ 345 #define I2S_INTFLAG_RXRDY0 (1 << I2S_INTFLAG_RXRDY0_Pos) 346 #define I2S_INTFLAG_RXRDY1_Pos 1 /**< \brief (I2S_INTFLAG) Receive Ready 1 */ 347 #define I2S_INTFLAG_RXRDY1 (1 << I2S_INTFLAG_RXRDY1_Pos) 348 #define I2S_INTFLAG_RXRDY_Pos 0 /**< \brief (I2S_INTFLAG) Receive Ready x */ 349 #define I2S_INTFLAG_RXRDY_Msk (_U_(0x3) << I2S_INTFLAG_RXRDY_Pos) 350 #define I2S_INTFLAG_RXRDY(value) (I2S_INTFLAG_RXRDY_Msk & ((value) << I2S_INTFLAG_RXRDY_Pos)) 351 #define I2S_INTFLAG_RXOR0_Pos 4 /**< \brief (I2S_INTFLAG) Receive Overrun 0 */ 352 #define I2S_INTFLAG_RXOR0 (1 << I2S_INTFLAG_RXOR0_Pos) 353 #define I2S_INTFLAG_RXOR1_Pos 5 /**< \brief (I2S_INTFLAG) Receive Overrun 1 */ 354 #define I2S_INTFLAG_RXOR1 (1 << I2S_INTFLAG_RXOR1_Pos) 355 #define I2S_INTFLAG_RXOR_Pos 4 /**< \brief (I2S_INTFLAG) Receive Overrun x */ 356 #define I2S_INTFLAG_RXOR_Msk (_U_(0x3) << I2S_INTFLAG_RXOR_Pos) 357 #define I2S_INTFLAG_RXOR(value) (I2S_INTFLAG_RXOR_Msk & ((value) << I2S_INTFLAG_RXOR_Pos)) 358 #define I2S_INTFLAG_TXRDY0_Pos 8 /**< \brief (I2S_INTFLAG) Transmit Ready 0 */ 359 #define I2S_INTFLAG_TXRDY0 (1 << I2S_INTFLAG_TXRDY0_Pos) 360 #define I2S_INTFLAG_TXRDY1_Pos 9 /**< \brief (I2S_INTFLAG) Transmit Ready 1 */ 361 #define I2S_INTFLAG_TXRDY1 (1 << I2S_INTFLAG_TXRDY1_Pos) 362 #define I2S_INTFLAG_TXRDY_Pos 8 /**< \brief (I2S_INTFLAG) Transmit Ready x */ 363 #define I2S_INTFLAG_TXRDY_Msk (_U_(0x3) << I2S_INTFLAG_TXRDY_Pos) 364 #define I2S_INTFLAG_TXRDY(value) (I2S_INTFLAG_TXRDY_Msk & ((value) << I2S_INTFLAG_TXRDY_Pos)) 365 #define I2S_INTFLAG_TXUR0_Pos 12 /**< \brief (I2S_INTFLAG) Transmit Underrun 0 */ 366 #define I2S_INTFLAG_TXUR0 (1 << I2S_INTFLAG_TXUR0_Pos) 367 #define I2S_INTFLAG_TXUR1_Pos 13 /**< \brief (I2S_INTFLAG) Transmit Underrun 1 */ 368 #define I2S_INTFLAG_TXUR1 (1 << I2S_INTFLAG_TXUR1_Pos) 369 #define I2S_INTFLAG_TXUR_Pos 12 /**< \brief (I2S_INTFLAG) Transmit Underrun x */ 370 #define I2S_INTFLAG_TXUR_Msk (_U_(0x3) << I2S_INTFLAG_TXUR_Pos) 371 #define I2S_INTFLAG_TXUR(value) (I2S_INTFLAG_TXUR_Msk & ((value) << I2S_INTFLAG_TXUR_Pos)) 372 #define I2S_INTFLAG_MASK _U_(0x3333) /**< \brief (I2S_INTFLAG) MASK Register */ 373 374 /* -------- I2S_SYNCBUSY : (I2S Offset: 0x18) (R/ 16) Synchronization Status -------- */ 375 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 376 typedef union { 377 struct { 378 uint16_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Status */ 379 uint16_t ENABLE:1; /*!< bit: 1 Enable Synchronization Status */ 380 uint16_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable Synchronization Status */ 381 uint16_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable Synchronization Status */ 382 uint16_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable Synchronization Status */ 383 uint16_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable Synchronization Status */ 384 uint16_t :2; /*!< bit: 6.. 7 Reserved */ 385 uint16_t DATA0:1; /*!< bit: 8 Data 0 Synchronization Status */ 386 uint16_t DATA1:1; /*!< bit: 9 Data 1 Synchronization Status */ 387 uint16_t :6; /*!< bit: 10..15 Reserved */ 388 } bit; /*!< Structure used for bit access */ 389 struct { 390 uint16_t :2; /*!< bit: 0.. 1 Reserved */ 391 uint16_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable Synchronization Status */ 392 uint16_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable Synchronization Status */ 393 uint16_t :2; /*!< bit: 6.. 7 Reserved */ 394 uint16_t DATA:2; /*!< bit: 8.. 9 Data x Synchronization Status */ 395 uint16_t :6; /*!< bit: 10..15 Reserved */ 396 } vec; /*!< Structure used for vec access */ 397 uint16_t reg; /*!< Type used for register access */ 398 } I2S_SYNCBUSY_Type; 399 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 400 401 #define I2S_SYNCBUSY_OFFSET 0x18 /**< \brief (I2S_SYNCBUSY offset) Synchronization Status */ 402 #define I2S_SYNCBUSY_RESETVALUE _U_(0x0000) /**< \brief (I2S_SYNCBUSY reset_value) Synchronization Status */ 403 404 #define I2S_SYNCBUSY_SWRST_Pos 0 /**< \brief (I2S_SYNCBUSY) Software Reset Synchronization Status */ 405 #define I2S_SYNCBUSY_SWRST (_U_(0x1) << I2S_SYNCBUSY_SWRST_Pos) 406 #define I2S_SYNCBUSY_ENABLE_Pos 1 /**< \brief (I2S_SYNCBUSY) Enable Synchronization Status */ 407 #define I2S_SYNCBUSY_ENABLE (_U_(0x1) << I2S_SYNCBUSY_ENABLE_Pos) 408 #define I2S_SYNCBUSY_CKEN0_Pos 2 /**< \brief (I2S_SYNCBUSY) Clock Unit 0 Enable Synchronization Status */ 409 #define I2S_SYNCBUSY_CKEN0 (1 << I2S_SYNCBUSY_CKEN0_Pos) 410 #define I2S_SYNCBUSY_CKEN1_Pos 3 /**< \brief (I2S_SYNCBUSY) Clock Unit 1 Enable Synchronization Status */ 411 #define I2S_SYNCBUSY_CKEN1 (1 << I2S_SYNCBUSY_CKEN1_Pos) 412 #define I2S_SYNCBUSY_CKEN_Pos 2 /**< \brief (I2S_SYNCBUSY) Clock Unit x Enable Synchronization Status */ 413 #define I2S_SYNCBUSY_CKEN_Msk (_U_(0x3) << I2S_SYNCBUSY_CKEN_Pos) 414 #define I2S_SYNCBUSY_CKEN(value) (I2S_SYNCBUSY_CKEN_Msk & ((value) << I2S_SYNCBUSY_CKEN_Pos)) 415 #define I2S_SYNCBUSY_SEREN0_Pos 4 /**< \brief (I2S_SYNCBUSY) Serializer 0 Enable Synchronization Status */ 416 #define I2S_SYNCBUSY_SEREN0 (1 << I2S_SYNCBUSY_SEREN0_Pos) 417 #define I2S_SYNCBUSY_SEREN1_Pos 5 /**< \brief (I2S_SYNCBUSY) Serializer 1 Enable Synchronization Status */ 418 #define I2S_SYNCBUSY_SEREN1 (1 << I2S_SYNCBUSY_SEREN1_Pos) 419 #define I2S_SYNCBUSY_SEREN_Pos 4 /**< \brief (I2S_SYNCBUSY) Serializer x Enable Synchronization Status */ 420 #define I2S_SYNCBUSY_SEREN_Msk (_U_(0x3) << I2S_SYNCBUSY_SEREN_Pos) 421 #define I2S_SYNCBUSY_SEREN(value) (I2S_SYNCBUSY_SEREN_Msk & ((value) << I2S_SYNCBUSY_SEREN_Pos)) 422 #define I2S_SYNCBUSY_DATA0_Pos 8 /**< \brief (I2S_SYNCBUSY) Data 0 Synchronization Status */ 423 #define I2S_SYNCBUSY_DATA0 (1 << I2S_SYNCBUSY_DATA0_Pos) 424 #define I2S_SYNCBUSY_DATA1_Pos 9 /**< \brief (I2S_SYNCBUSY) Data 1 Synchronization Status */ 425 #define I2S_SYNCBUSY_DATA1 (1 << I2S_SYNCBUSY_DATA1_Pos) 426 #define I2S_SYNCBUSY_DATA_Pos 8 /**< \brief (I2S_SYNCBUSY) Data x Synchronization Status */ 427 #define I2S_SYNCBUSY_DATA_Msk (_U_(0x3) << I2S_SYNCBUSY_DATA_Pos) 428 #define I2S_SYNCBUSY_DATA(value) (I2S_SYNCBUSY_DATA_Msk & ((value) << I2S_SYNCBUSY_DATA_Pos)) 429 #define I2S_SYNCBUSY_MASK _U_(0x033F) /**< \brief (I2S_SYNCBUSY) MASK Register */ 430 431 /* -------- I2S_SERCTRL : (I2S Offset: 0x20) (R/W 32) Serializer n Control -------- */ 432 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 433 typedef union { 434 struct { 435 uint32_t SERMODE:2; /*!< bit: 0.. 1 Serializer Mode */ 436 uint32_t TXDEFAULT:2; /*!< bit: 2.. 3 Line Default Line when Slot Disabled */ 437 uint32_t TXSAME:1; /*!< bit: 4 Transmit Data when Underrun */ 438 uint32_t CLKSEL:1; /*!< bit: 5 Clock Unit Selection */ 439 uint32_t :1; /*!< bit: 6 Reserved */ 440 uint32_t SLOTADJ:1; /*!< bit: 7 Data Slot Formatting Adjust */ 441 uint32_t DATASIZE:3; /*!< bit: 8..10 Data Word Size */ 442 uint32_t :1; /*!< bit: 11 Reserved */ 443 uint32_t WORDADJ:1; /*!< bit: 12 Data Word Formatting Adjust */ 444 uint32_t EXTEND:2; /*!< bit: 13..14 Data Formatting Bit Extension */ 445 uint32_t BITREV:1; /*!< bit: 15 Data Formatting Bit Reverse */ 446 uint32_t SLOTDIS0:1; /*!< bit: 16 Slot 0 Disabled for this Serializer */ 447 uint32_t SLOTDIS1:1; /*!< bit: 17 Slot 1 Disabled for this Serializer */ 448 uint32_t SLOTDIS2:1; /*!< bit: 18 Slot 2 Disabled for this Serializer */ 449 uint32_t SLOTDIS3:1; /*!< bit: 19 Slot 3 Disabled for this Serializer */ 450 uint32_t SLOTDIS4:1; /*!< bit: 20 Slot 4 Disabled for this Serializer */ 451 uint32_t SLOTDIS5:1; /*!< bit: 21 Slot 5 Disabled for this Serializer */ 452 uint32_t SLOTDIS6:1; /*!< bit: 22 Slot 6 Disabled for this Serializer */ 453 uint32_t SLOTDIS7:1; /*!< bit: 23 Slot 7 Disabled for this Serializer */ 454 uint32_t MONO:1; /*!< bit: 24 Mono Mode */ 455 uint32_t DMA:1; /*!< bit: 25 Single or Multiple DMA Channels */ 456 uint32_t RXLOOP:1; /*!< bit: 26 Loop-back Test Mode */ 457 uint32_t :5; /*!< bit: 27..31 Reserved */ 458 } bit; /*!< Structure used for bit access */ 459 struct { 460 uint32_t :16; /*!< bit: 0..15 Reserved */ 461 uint32_t SLOTDIS:8; /*!< bit: 16..23 Slot x Disabled for this Serializer */ 462 uint32_t :8; /*!< bit: 24..31 Reserved */ 463 } vec; /*!< Structure used for vec access */ 464 uint32_t reg; /*!< Type used for register access */ 465 } I2S_SERCTRL_Type; 466 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 467 468 #define I2S_SERCTRL_OFFSET 0x20 /**< \brief (I2S_SERCTRL offset) Serializer n Control */ 469 #define I2S_SERCTRL_RESETVALUE _U_(0x00000000) /**< \brief (I2S_SERCTRL reset_value) Serializer n Control */ 470 471 #define I2S_SERCTRL_SERMODE_Pos 0 /**< \brief (I2S_SERCTRL) Serializer Mode */ 472 #define I2S_SERCTRL_SERMODE_Msk (_U_(0x3) << I2S_SERCTRL_SERMODE_Pos) 473 #define I2S_SERCTRL_SERMODE(value) (I2S_SERCTRL_SERMODE_Msk & ((value) << I2S_SERCTRL_SERMODE_Pos)) 474 #define I2S_SERCTRL_SERMODE_RX_Val _U_(0x0) /**< \brief (I2S_SERCTRL) Receive */ 475 #define I2S_SERCTRL_SERMODE_TX_Val _U_(0x1) /**< \brief (I2S_SERCTRL) Transmit */ 476 #define I2S_SERCTRL_SERMODE_PDM2_Val _U_(0x2) /**< \brief (I2S_SERCTRL) Receive one PDM data on each serial clock edge */ 477 #define I2S_SERCTRL_SERMODE_RX (I2S_SERCTRL_SERMODE_RX_Val << I2S_SERCTRL_SERMODE_Pos) 478 #define I2S_SERCTRL_SERMODE_TX (I2S_SERCTRL_SERMODE_TX_Val << I2S_SERCTRL_SERMODE_Pos) 479 #define I2S_SERCTRL_SERMODE_PDM2 (I2S_SERCTRL_SERMODE_PDM2_Val << I2S_SERCTRL_SERMODE_Pos) 480 #define I2S_SERCTRL_TXDEFAULT_Pos 2 /**< \brief (I2S_SERCTRL) Line Default Line when Slot Disabled */ 481 #define I2S_SERCTRL_TXDEFAULT_Msk (_U_(0x3) << I2S_SERCTRL_TXDEFAULT_Pos) 482 #define I2S_SERCTRL_TXDEFAULT(value) (I2S_SERCTRL_TXDEFAULT_Msk & ((value) << I2S_SERCTRL_TXDEFAULT_Pos)) 483 #define I2S_SERCTRL_TXDEFAULT_ZERO_Val _U_(0x0) /**< \brief (I2S_SERCTRL) Output Default Value is 0 */ 484 #define I2S_SERCTRL_TXDEFAULT_ONE_Val _U_(0x1) /**< \brief (I2S_SERCTRL) Output Default Value is 1 */ 485 #define I2S_SERCTRL_TXDEFAULT_HIZ_Val _U_(0x3) /**< \brief (I2S_SERCTRL) Output Default Value is high impedance */ 486 #define I2S_SERCTRL_TXDEFAULT_ZERO (I2S_SERCTRL_TXDEFAULT_ZERO_Val << I2S_SERCTRL_TXDEFAULT_Pos) 487 #define I2S_SERCTRL_TXDEFAULT_ONE (I2S_SERCTRL_TXDEFAULT_ONE_Val << I2S_SERCTRL_TXDEFAULT_Pos) 488 #define I2S_SERCTRL_TXDEFAULT_HIZ (I2S_SERCTRL_TXDEFAULT_HIZ_Val << I2S_SERCTRL_TXDEFAULT_Pos) 489 #define I2S_SERCTRL_TXSAME_Pos 4 /**< \brief (I2S_SERCTRL) Transmit Data when Underrun */ 490 #define I2S_SERCTRL_TXSAME (_U_(0x1) << I2S_SERCTRL_TXSAME_Pos) 491 #define I2S_SERCTRL_TXSAME_ZERO_Val _U_(0x0) /**< \brief (I2S_SERCTRL) Zero data transmitted in case of underrun */ 492 #define I2S_SERCTRL_TXSAME_SAME_Val _U_(0x1) /**< \brief (I2S_SERCTRL) Last data transmitted in case of underrun */ 493 #define I2S_SERCTRL_TXSAME_ZERO (I2S_SERCTRL_TXSAME_ZERO_Val << I2S_SERCTRL_TXSAME_Pos) 494 #define I2S_SERCTRL_TXSAME_SAME (I2S_SERCTRL_TXSAME_SAME_Val << I2S_SERCTRL_TXSAME_Pos) 495 #define I2S_SERCTRL_CLKSEL_Pos 5 /**< \brief (I2S_SERCTRL) Clock Unit Selection */ 496 #define I2S_SERCTRL_CLKSEL (_U_(0x1) << I2S_SERCTRL_CLKSEL_Pos) 497 #define I2S_SERCTRL_CLKSEL_CLK0_Val _U_(0x0) /**< \brief (I2S_SERCTRL) Use Clock Unit 0 */ 498 #define I2S_SERCTRL_CLKSEL_CLK1_Val _U_(0x1) /**< \brief (I2S_SERCTRL) Use Clock Unit 1 */ 499 #define I2S_SERCTRL_CLKSEL_CLK0 (I2S_SERCTRL_CLKSEL_CLK0_Val << I2S_SERCTRL_CLKSEL_Pos) 500 #define I2S_SERCTRL_CLKSEL_CLK1 (I2S_SERCTRL_CLKSEL_CLK1_Val << I2S_SERCTRL_CLKSEL_Pos) 501 #define I2S_SERCTRL_SLOTADJ_Pos 7 /**< \brief (I2S_SERCTRL) Data Slot Formatting Adjust */ 502 #define I2S_SERCTRL_SLOTADJ (_U_(0x1) << I2S_SERCTRL_SLOTADJ_Pos) 503 #define I2S_SERCTRL_SLOTADJ_RIGHT_Val _U_(0x0) /**< \brief (I2S_SERCTRL) Data is right adjusted in slot */ 504 #define I2S_SERCTRL_SLOTADJ_LEFT_Val _U_(0x1) /**< \brief (I2S_SERCTRL) Data is left adjusted in slot */ 505 #define I2S_SERCTRL_SLOTADJ_RIGHT (I2S_SERCTRL_SLOTADJ_RIGHT_Val << I2S_SERCTRL_SLOTADJ_Pos) 506 #define I2S_SERCTRL_SLOTADJ_LEFT (I2S_SERCTRL_SLOTADJ_LEFT_Val << I2S_SERCTRL_SLOTADJ_Pos) 507 #define I2S_SERCTRL_DATASIZE_Pos 8 /**< \brief (I2S_SERCTRL) Data Word Size */ 508 #define I2S_SERCTRL_DATASIZE_Msk (_U_(0x7) << I2S_SERCTRL_DATASIZE_Pos) 509 #define I2S_SERCTRL_DATASIZE(value) (I2S_SERCTRL_DATASIZE_Msk & ((value) << I2S_SERCTRL_DATASIZE_Pos)) 510 #define I2S_SERCTRL_DATASIZE_32_Val _U_(0x0) /**< \brief (I2S_SERCTRL) 32 bits */ 511 #define I2S_SERCTRL_DATASIZE_24_Val _U_(0x1) /**< \brief (I2S_SERCTRL) 24 bits */ 512 #define I2S_SERCTRL_DATASIZE_20_Val _U_(0x2) /**< \brief (I2S_SERCTRL) 20 bits */ 513 #define I2S_SERCTRL_DATASIZE_18_Val _U_(0x3) /**< \brief (I2S_SERCTRL) 18 bits */ 514 #define I2S_SERCTRL_DATASIZE_16_Val _U_(0x4) /**< \brief (I2S_SERCTRL) 16 bits */ 515 #define I2S_SERCTRL_DATASIZE_16C_Val _U_(0x5) /**< \brief (I2S_SERCTRL) 16 bits compact stereo */ 516 #define I2S_SERCTRL_DATASIZE_8_Val _U_(0x6) /**< \brief (I2S_SERCTRL) 8 bits */ 517 #define I2S_SERCTRL_DATASIZE_8C_Val _U_(0x7) /**< \brief (I2S_SERCTRL) 8 bits compact stereo */ 518 #define I2S_SERCTRL_DATASIZE_32 (I2S_SERCTRL_DATASIZE_32_Val << I2S_SERCTRL_DATASIZE_Pos) 519 #define I2S_SERCTRL_DATASIZE_24 (I2S_SERCTRL_DATASIZE_24_Val << I2S_SERCTRL_DATASIZE_Pos) 520 #define I2S_SERCTRL_DATASIZE_20 (I2S_SERCTRL_DATASIZE_20_Val << I2S_SERCTRL_DATASIZE_Pos) 521 #define I2S_SERCTRL_DATASIZE_18 (I2S_SERCTRL_DATASIZE_18_Val << I2S_SERCTRL_DATASIZE_Pos) 522 #define I2S_SERCTRL_DATASIZE_16 (I2S_SERCTRL_DATASIZE_16_Val << I2S_SERCTRL_DATASIZE_Pos) 523 #define I2S_SERCTRL_DATASIZE_16C (I2S_SERCTRL_DATASIZE_16C_Val << I2S_SERCTRL_DATASIZE_Pos) 524 #define I2S_SERCTRL_DATASIZE_8 (I2S_SERCTRL_DATASIZE_8_Val << I2S_SERCTRL_DATASIZE_Pos) 525 #define I2S_SERCTRL_DATASIZE_8C (I2S_SERCTRL_DATASIZE_8C_Val << I2S_SERCTRL_DATASIZE_Pos) 526 #define I2S_SERCTRL_WORDADJ_Pos 12 /**< \brief (I2S_SERCTRL) Data Word Formatting Adjust */ 527 #define I2S_SERCTRL_WORDADJ (_U_(0x1) << I2S_SERCTRL_WORDADJ_Pos) 528 #define I2S_SERCTRL_WORDADJ_RIGHT_Val _U_(0x0) /**< \brief (I2S_SERCTRL) Data is right adjusted in word */ 529 #define I2S_SERCTRL_WORDADJ_LEFT_Val _U_(0x1) /**< \brief (I2S_SERCTRL) Data is left adjusted in word */ 530 #define I2S_SERCTRL_WORDADJ_RIGHT (I2S_SERCTRL_WORDADJ_RIGHT_Val << I2S_SERCTRL_WORDADJ_Pos) 531 #define I2S_SERCTRL_WORDADJ_LEFT (I2S_SERCTRL_WORDADJ_LEFT_Val << I2S_SERCTRL_WORDADJ_Pos) 532 #define I2S_SERCTRL_EXTEND_Pos 13 /**< \brief (I2S_SERCTRL) Data Formatting Bit Extension */ 533 #define I2S_SERCTRL_EXTEND_Msk (_U_(0x3) << I2S_SERCTRL_EXTEND_Pos) 534 #define I2S_SERCTRL_EXTEND(value) (I2S_SERCTRL_EXTEND_Msk & ((value) << I2S_SERCTRL_EXTEND_Pos)) 535 #define I2S_SERCTRL_EXTEND_ZERO_Val _U_(0x0) /**< \brief (I2S_SERCTRL) Extend with zeroes */ 536 #define I2S_SERCTRL_EXTEND_ONE_Val _U_(0x1) /**< \brief (I2S_SERCTRL) Extend with ones */ 537 #define I2S_SERCTRL_EXTEND_MSBIT_Val _U_(0x2) /**< \brief (I2S_SERCTRL) Extend with Most Significant Bit */ 538 #define I2S_SERCTRL_EXTEND_LSBIT_Val _U_(0x3) /**< \brief (I2S_SERCTRL) Extend with Least Significant Bit */ 539 #define I2S_SERCTRL_EXTEND_ZERO (I2S_SERCTRL_EXTEND_ZERO_Val << I2S_SERCTRL_EXTEND_Pos) 540 #define I2S_SERCTRL_EXTEND_ONE (I2S_SERCTRL_EXTEND_ONE_Val << I2S_SERCTRL_EXTEND_Pos) 541 #define I2S_SERCTRL_EXTEND_MSBIT (I2S_SERCTRL_EXTEND_MSBIT_Val << I2S_SERCTRL_EXTEND_Pos) 542 #define I2S_SERCTRL_EXTEND_LSBIT (I2S_SERCTRL_EXTEND_LSBIT_Val << I2S_SERCTRL_EXTEND_Pos) 543 #define I2S_SERCTRL_BITREV_Pos 15 /**< \brief (I2S_SERCTRL) Data Formatting Bit Reverse */ 544 #define I2S_SERCTRL_BITREV (_U_(0x1) << I2S_SERCTRL_BITREV_Pos) 545 #define I2S_SERCTRL_BITREV_MSBIT_Val _U_(0x0) /**< \brief (I2S_SERCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) */ 546 #define I2S_SERCTRL_BITREV_LSBIT_Val _U_(0x1) /**< \brief (I2S_SERCTRL) Transfer Data Least Significant Bit (LSB) first */ 547 #define I2S_SERCTRL_BITREV_MSBIT (I2S_SERCTRL_BITREV_MSBIT_Val << I2S_SERCTRL_BITREV_Pos) 548 #define I2S_SERCTRL_BITREV_LSBIT (I2S_SERCTRL_BITREV_LSBIT_Val << I2S_SERCTRL_BITREV_Pos) 549 #define I2S_SERCTRL_SLOTDIS0_Pos 16 /**< \brief (I2S_SERCTRL) Slot 0 Disabled for this Serializer */ 550 #define I2S_SERCTRL_SLOTDIS0 (1 << I2S_SERCTRL_SLOTDIS0_Pos) 551 #define I2S_SERCTRL_SLOTDIS1_Pos 17 /**< \brief (I2S_SERCTRL) Slot 1 Disabled for this Serializer */ 552 #define I2S_SERCTRL_SLOTDIS1 (1 << I2S_SERCTRL_SLOTDIS1_Pos) 553 #define I2S_SERCTRL_SLOTDIS2_Pos 18 /**< \brief (I2S_SERCTRL) Slot 2 Disabled for this Serializer */ 554 #define I2S_SERCTRL_SLOTDIS2 (1 << I2S_SERCTRL_SLOTDIS2_Pos) 555 #define I2S_SERCTRL_SLOTDIS3_Pos 19 /**< \brief (I2S_SERCTRL) Slot 3 Disabled for this Serializer */ 556 #define I2S_SERCTRL_SLOTDIS3 (1 << I2S_SERCTRL_SLOTDIS3_Pos) 557 #define I2S_SERCTRL_SLOTDIS4_Pos 20 /**< \brief (I2S_SERCTRL) Slot 4 Disabled for this Serializer */ 558 #define I2S_SERCTRL_SLOTDIS4 (1 << I2S_SERCTRL_SLOTDIS4_Pos) 559 #define I2S_SERCTRL_SLOTDIS5_Pos 21 /**< \brief (I2S_SERCTRL) Slot 5 Disabled for this Serializer */ 560 #define I2S_SERCTRL_SLOTDIS5 (1 << I2S_SERCTRL_SLOTDIS5_Pos) 561 #define I2S_SERCTRL_SLOTDIS6_Pos 22 /**< \brief (I2S_SERCTRL) Slot 6 Disabled for this Serializer */ 562 #define I2S_SERCTRL_SLOTDIS6 (1 << I2S_SERCTRL_SLOTDIS6_Pos) 563 #define I2S_SERCTRL_SLOTDIS7_Pos 23 /**< \brief (I2S_SERCTRL) Slot 7 Disabled for this Serializer */ 564 #define I2S_SERCTRL_SLOTDIS7 (1 << I2S_SERCTRL_SLOTDIS7_Pos) 565 #define I2S_SERCTRL_SLOTDIS_Pos 16 /**< \brief (I2S_SERCTRL) Slot x Disabled for this Serializer */ 566 #define I2S_SERCTRL_SLOTDIS_Msk (_U_(0xFF) << I2S_SERCTRL_SLOTDIS_Pos) 567 #define I2S_SERCTRL_SLOTDIS(value) (I2S_SERCTRL_SLOTDIS_Msk & ((value) << I2S_SERCTRL_SLOTDIS_Pos)) 568 #define I2S_SERCTRL_MONO_Pos 24 /**< \brief (I2S_SERCTRL) Mono Mode */ 569 #define I2S_SERCTRL_MONO (_U_(0x1) << I2S_SERCTRL_MONO_Pos) 570 #define I2S_SERCTRL_MONO_STEREO_Val _U_(0x0) /**< \brief (I2S_SERCTRL) Normal mode */ 571 #define I2S_SERCTRL_MONO_MONO_Val _U_(0x1) /**< \brief (I2S_SERCTRL) Left channel data is duplicated to right channel */ 572 #define I2S_SERCTRL_MONO_STEREO (I2S_SERCTRL_MONO_STEREO_Val << I2S_SERCTRL_MONO_Pos) 573 #define I2S_SERCTRL_MONO_MONO (I2S_SERCTRL_MONO_MONO_Val << I2S_SERCTRL_MONO_Pos) 574 #define I2S_SERCTRL_DMA_Pos 25 /**< \brief (I2S_SERCTRL) Single or Multiple DMA Channels */ 575 #define I2S_SERCTRL_DMA (_U_(0x1) << I2S_SERCTRL_DMA_Pos) 576 #define I2S_SERCTRL_DMA_SINGLE_Val _U_(0x0) /**< \brief (I2S_SERCTRL) Single DMA channel */ 577 #define I2S_SERCTRL_DMA_MULTIPLE_Val _U_(0x1) /**< \brief (I2S_SERCTRL) One DMA channel per data channel */ 578 #define I2S_SERCTRL_DMA_SINGLE (I2S_SERCTRL_DMA_SINGLE_Val << I2S_SERCTRL_DMA_Pos) 579 #define I2S_SERCTRL_DMA_MULTIPLE (I2S_SERCTRL_DMA_MULTIPLE_Val << I2S_SERCTRL_DMA_Pos) 580 #define I2S_SERCTRL_RXLOOP_Pos 26 /**< \brief (I2S_SERCTRL) Loop-back Test Mode */ 581 #define I2S_SERCTRL_RXLOOP (_U_(0x1) << I2S_SERCTRL_RXLOOP_Pos) 582 #define I2S_SERCTRL_MASK _U_(0x07FFF7BF) /**< \brief (I2S_SERCTRL) MASK Register */ 583 584 /* -------- I2S_DATA : (I2S Offset: 0x30) (R/W 32) Data n -------- */ 585 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 586 typedef union { 587 struct { 588 uint32_t DATA:32; /*!< bit: 0..31 Sample Data */ 589 } bit; /*!< Structure used for bit access */ 590 uint32_t reg; /*!< Type used for register access */ 591 } I2S_DATA_Type; 592 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 593 594 #define I2S_DATA_OFFSET 0x30 /**< \brief (I2S_DATA offset) Data n */ 595 #define I2S_DATA_RESETVALUE _U_(0x00000000) /**< \brief (I2S_DATA reset_value) Data n */ 596 597 #define I2S_DATA_DATA_Pos 0 /**< \brief (I2S_DATA) Sample Data */ 598 #define I2S_DATA_DATA_Msk (_U_(0xFFFFFFFF) << I2S_DATA_DATA_Pos) 599 #define I2S_DATA_DATA(value) (I2S_DATA_DATA_Msk & ((value) << I2S_DATA_DATA_Pos)) 600 #define I2S_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (I2S_DATA) MASK Register */ 601 602 /** \brief I2S hardware registers */ 603 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 604 typedef struct { 605 __IO I2S_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ 606 RoReg8 Reserved1[0x3]; 607 __IO I2S_CLKCTRL_Type CLKCTRL[2]; /**< \brief Offset: 0x04 (R/W 32) Clock Unit n Control */ 608 __IO I2S_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */ 609 RoReg8 Reserved2[0x2]; 610 __IO I2S_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 16) Interrupt Enable Set */ 611 RoReg8 Reserved3[0x2]; 612 __IO I2S_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 16) Interrupt Flag Status and Clear */ 613 RoReg8 Reserved4[0x2]; 614 __I I2S_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x18 (R/ 16) Synchronization Status */ 615 RoReg8 Reserved5[0x6]; 616 __IO I2S_SERCTRL_Type SERCTRL[2]; /**< \brief Offset: 0x20 (R/W 32) Serializer n Control */ 617 RoReg8 Reserved6[0x8]; 618 __IO I2S_DATA_Type DATA[2]; /**< \brief Offset: 0x30 (R/W 32) Data n */ 619 } I2s; 620 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 621 622 /*@}*/ 623 624 #endif /* _SAMD21_I2S_COMPONENT_ */ 625
