1 /** 2 * \file 3 * 4 * \brief Header file for SAMD20E17 5 * 6 * Copyright (c) 2017 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMD20E17_ 31 #define _SAMD20E17_ 32 33 /** 34 * \ingroup SAMD20_definitions 35 * \addtogroup SAMD20E17_definitions SAMD20E17 definitions 36 * This file defines all structures and symbols for SAMD20E17: 37 * - registers and bitfields 38 * - peripheral base address 39 * - peripheral ID 40 * - PIO definitions 41 */ 42 /*@{*/ 43 44 #ifdef __cplusplus 45 extern "C" { 46 #endif 47 48 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 49 #include <stdint.h> 50 #ifndef __cplusplus 51 typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ 52 typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ 53 typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ 54 #else 55 typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ 56 typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ 57 typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ 58 #endif 59 typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ 60 typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ 61 typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ 62 typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ 63 typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ 64 typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ 65 #endif 66 67 #if !defined(SKIP_INTEGER_LITERALS) 68 #if defined(_U_) || defined(_L_) || defined(_UL_) 69 #error "Integer Literals macros already defined elsewhere" 70 #endif 71 72 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 73 /* Macros that deal with adding suffixes to integer literal constants for C/C++ */ 74 #define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ 75 #define _L_(x) x ## L /**< C code: Long integer literal constant value */ 76 #define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ 77 #else /* Assembler */ 78 #define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ 79 #define _L_(x) x /**< Assembler: Long integer literal constant value */ 80 #define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ 81 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 82 #endif /* SKIP_INTEGER_LITERALS */ 83 84 /* ************************************************************************** */ 85 /** CMSIS DEFINITIONS FOR SAMD20E17 */ 86 /* ************************************************************************** */ 87 /** \defgroup SAMD20E17_cmsis CMSIS Definitions */ 88 /*@{*/ 89 90 /** Interrupt Number Definition */ 91 typedef enum IRQn 92 { 93 /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ 94 NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ 95 HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ 96 SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ 97 PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ 98 SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ 99 /****** SAMD20E17-specific Interrupt Numbers ***********************/ 100 PM_IRQn = 0, /**< 0 SAMD20E17 Power Manager (PM) */ 101 SYSCTRL_IRQn = 1, /**< 1 SAMD20E17 System Control (SYSCTRL) */ 102 WDT_IRQn = 2, /**< 2 SAMD20E17 Watchdog Timer (WDT) */ 103 RTC_IRQn = 3, /**< 3 SAMD20E17 Real-Time Counter (RTC) */ 104 EIC_IRQn = 4, /**< 4 SAMD20E17 External Interrupt Controller (EIC) */ 105 NVMCTRL_IRQn = 5, /**< 5 SAMD20E17 Non-Volatile Memory Controller (NVMCTRL) */ 106 EVSYS_IRQn = 6, /**< 6 SAMD20E17 Event System Interface (EVSYS) */ 107 SERCOM0_IRQn = 7, /**< 7 SAMD20E17 Serial Communication Interface 0 (SERCOM0) */ 108 SERCOM1_IRQn = 8, /**< 8 SAMD20E17 Serial Communication Interface 1 (SERCOM1) */ 109 SERCOM2_IRQn = 9, /**< 9 SAMD20E17 Serial Communication Interface 2 (SERCOM2) */ 110 SERCOM3_IRQn = 10, /**< 10 SAMD20E17 Serial Communication Interface 3 (SERCOM3) */ 111 TC0_IRQn = 13, /**< 13 SAMD20E17 Basic Timer Counter 0 (TC0) */ 112 TC1_IRQn = 14, /**< 14 SAMD20E17 Basic Timer Counter 1 (TC1) */ 113 TC2_IRQn = 15, /**< 15 SAMD20E17 Basic Timer Counter 2 (TC2) */ 114 TC3_IRQn = 16, /**< 16 SAMD20E17 Basic Timer Counter 3 (TC3) */ 115 TC4_IRQn = 17, /**< 17 SAMD20E17 Basic Timer Counter 4 (TC4) */ 116 TC5_IRQn = 18, /**< 18 SAMD20E17 Basic Timer Counter 5 (TC5) */ 117 ADC_IRQn = 21, /**< 21 SAMD20E17 Analog Digital Converter (ADC) */ 118 AC_IRQn = 22, /**< 22 SAMD20E17 Analog Comparators (AC) */ 119 DAC_IRQn = 23, /**< 23 SAMD20E17 Digital Analog Converter (DAC) */ 120 PTC_IRQn = 24, /**< 24 SAMD20E17 Peripheral Touch Controller (PTC) */ 121 122 PERIPH_COUNT_IRQn = 25 /**< Number of peripheral IDs */ 123 } IRQn_Type; 124 125 typedef struct _DeviceVectors 126 { 127 /* Stack pointer */ 128 void* pvStack; 129 130 /* Cortex-M handlers */ 131 void* pfnReset_Handler; 132 void* pfnNMI_Handler; 133 void* pfnHardFault_Handler; 134 void* pvReservedM12; 135 void* pvReservedM11; 136 void* pvReservedM10; 137 void* pvReservedM9; 138 void* pvReservedM8; 139 void* pvReservedM7; 140 void* pvReservedM6; 141 void* pfnSVC_Handler; 142 void* pvReservedM4; 143 void* pvReservedM3; 144 void* pfnPendSV_Handler; 145 void* pfnSysTick_Handler; 146 147 /* Peripheral handlers */ 148 void* pfnPM_Handler; /* 0 Power Manager */ 149 void* pfnSYSCTRL_Handler; /* 1 System Control */ 150 void* pfnWDT_Handler; /* 2 Watchdog Timer */ 151 void* pfnRTC_Handler; /* 3 Real-Time Counter */ 152 void* pfnEIC_Handler; /* 4 External Interrupt Controller */ 153 void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ 154 void* pfnEVSYS_Handler; /* 6 Event System Interface */ 155 void* pfnSERCOM0_Handler; /* 7 Serial Communication Interface 0 */ 156 void* pfnSERCOM1_Handler; /* 8 Serial Communication Interface 1 */ 157 void* pfnSERCOM2_Handler; /* 9 Serial Communication Interface 2 */ 158 void* pfnSERCOM3_Handler; /* 10 Serial Communication Interface 3 */ 159 void* pvReserved11; 160 void* pvReserved12; 161 void* pfnTC0_Handler; /* 13 Basic Timer Counter 0 */ 162 void* pfnTC1_Handler; /* 14 Basic Timer Counter 1 */ 163 void* pfnTC2_Handler; /* 15 Basic Timer Counter 2 */ 164 void* pfnTC3_Handler; /* 16 Basic Timer Counter 3 */ 165 void* pfnTC4_Handler; /* 17 Basic Timer Counter 4 */ 166 void* pfnTC5_Handler; /* 18 Basic Timer Counter 5 */ 167 void* pvReserved19; 168 void* pvReserved20; 169 void* pfnADC_Handler; /* 21 Analog Digital Converter */ 170 void* pfnAC_Handler; /* 22 Analog Comparators */ 171 void* pfnDAC_Handler; /* 23 Digital Analog Converter */ 172 void* pfnPTC_Handler; /* 24 Peripheral Touch Controller */ 173 } DeviceVectors; 174 175 /* Cortex-M0+ processor handlers */ 176 void Reset_Handler ( void ); 177 void NMI_Handler ( void ); 178 void HardFault_Handler ( void ); 179 void SVC_Handler ( void ); 180 void PendSV_Handler ( void ); 181 void SysTick_Handler ( void ); 182 183 /* Peripherals handlers */ 184 void PM_Handler ( void ); 185 void SYSCTRL_Handler ( void ); 186 void WDT_Handler ( void ); 187 void RTC_Handler ( void ); 188 void EIC_Handler ( void ); 189 void NVMCTRL_Handler ( void ); 190 void EVSYS_Handler ( void ); 191 void SERCOM0_Handler ( void ); 192 void SERCOM1_Handler ( void ); 193 void SERCOM2_Handler ( void ); 194 void SERCOM3_Handler ( void ); 195 void TC0_Handler ( void ); 196 void TC1_Handler ( void ); 197 void TC2_Handler ( void ); 198 void TC3_Handler ( void ); 199 void TC4_Handler ( void ); 200 void TC5_Handler ( void ); 201 void ADC_Handler ( void ); 202 void AC_Handler ( void ); 203 void DAC_Handler ( void ); 204 void PTC_Handler ( void ); 205 206 /* 207 * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals 208 */ 209 210 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ 211 #define __MPU_PRESENT 0 /*!< MPU present or not */ 212 #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ 213 #define __VTOR_PRESENT 1 /*!< VTOR present or not */ 214 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 215 216 /** 217 * \brief CMSIS includes 218 */ 219 220 #include <core_cm0plus.h> 221 #if !defined DONT_USE_CMSIS_INIT 222 #include "system_samd20.h" 223 #endif /* DONT_USE_CMSIS_INIT */ 224 225 /*@}*/ 226 227 /* ************************************************************************** */ 228 /** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD20E17 */ 229 /* ************************************************************************** */ 230 /** \defgroup SAMD20E17_api Peripheral Software API */ 231 /*@{*/ 232 233 #include "component/ac.h" 234 #include "component/adc.h" 235 #include "component/dac.h" 236 #include "component/dsu.h" 237 #include "component/eic.h" 238 #include "component/evsys.h" 239 #include "component/gclk.h" 240 #include "component/nvmctrl.h" 241 #include "component/pac.h" 242 #include "component/pm.h" 243 #include "component/port.h" 244 #include "component/rtc.h" 245 #include "component/sercom.h" 246 #include "component/sysctrl.h" 247 #include "component/tc.h" 248 #include "component/wdt.h" 249 /*@}*/ 250 251 /* ************************************************************************** */ 252 /** REGISTERS ACCESS DEFINITIONS FOR SAMD20E17 */ 253 /* ************************************************************************** */ 254 /** \defgroup SAMD20E17_reg Registers Access Definitions */ 255 /*@{*/ 256 257 #include "instance/ac.h" 258 #include "instance/adc.h" 259 #include "instance/dac.h" 260 #include "instance/dsu.h" 261 #include "instance/eic.h" 262 #include "instance/evsys.h" 263 #include "instance/gclk.h" 264 #include "instance/nvmctrl.h" 265 #include "instance/pac0.h" 266 #include "instance/pac1.h" 267 #include "instance/pac2.h" 268 #include "instance/pm.h" 269 #include "instance/port.h" 270 #include "instance/rtc.h" 271 #include "instance/sercom0.h" 272 #include "instance/sercom1.h" 273 #include "instance/sercom2.h" 274 #include "instance/sercom3.h" 275 #include "instance/sysctrl.h" 276 #include "instance/tc0.h" 277 #include "instance/tc1.h" 278 #include "instance/tc2.h" 279 #include "instance/tc3.h" 280 #include "instance/tc4.h" 281 #include "instance/tc5.h" 282 #include "instance/wdt.h" 283 /*@}*/ 284 285 /* ************************************************************************** */ 286 /** PERIPHERAL ID DEFINITIONS FOR SAMD20E17 */ 287 /* ************************************************************************** */ 288 /** \defgroup SAMD20E17_id Peripheral Ids Definitions */ 289 /*@{*/ 290 291 // Peripheral instances on HPB0 bridge 292 #define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ 293 #define ID_PM 1 /**< \brief Power Manager (PM) */ 294 #define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ 295 #define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ 296 #define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ 297 #define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ 298 #define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ 299 300 // Peripheral instances on HPB1 bridge 301 #define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ 302 #define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ 303 #define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ 304 #define ID_PORT 35 /**< \brief Port Module (PORT) */ 305 306 // Peripheral instances on HPB2 bridge 307 #define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ 308 #define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ 309 #define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ 310 #define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ 311 #define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ 312 #define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ 313 #define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ 314 #define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ 315 #define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ 316 #define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ 317 #define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ 318 #define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ 319 #define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ 320 #define ID_AC 81 /**< \brief Analog Comparators (AC) */ 321 #define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ 322 #define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ 323 324 #define ID_PERIPH_COUNT 84 /**< \brief Max number of peripheral IDs */ 325 /*@}*/ 326 327 /* ************************************************************************** */ 328 /** BASE ADDRESS DEFINITIONS FOR SAMD20E17 */ 329 /* ************************************************************************** */ 330 /** \defgroup SAMD20E17_base Peripheral Base Address Definitions */ 331 /*@{*/ 332 333 #if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) 334 #define AC (0x42004400) /**< \brief (AC) APB Base Address */ 335 #define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ 336 #define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ 337 #define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ 338 #define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ 339 #define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ 340 #define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ 341 #define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ 342 #define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ 343 #define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ 344 #define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ 345 #define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ 346 #define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ 347 #define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ 348 #define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ 349 #define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ 350 #define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ 351 #define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ 352 #define PM (0x40000400) /**< \brief (PM) APB Base Address */ 353 #define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ 354 #define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ 355 #define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ 356 #define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ 357 #define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ 358 #define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ 359 #define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ 360 #define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ 361 #define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ 362 #define TC0 (0x42002000) /**< \brief (TC0) APB Base Address */ 363 #define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ 364 #define TC2 (0x42002800) /**< \brief (TC2) APB Base Address */ 365 #define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ 366 #define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ 367 #define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ 368 #define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ 369 #else 370 #define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ 371 #define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ 372 #define AC_INSTS { AC } /**< \brief (AC) Instances List */ 373 374 #define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ 375 #define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ 376 #define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ 377 378 #define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ 379 #define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ 380 #define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ 381 382 #define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ 383 #define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ 384 #define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ 385 386 #define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ 387 #define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ 388 #define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ 389 390 #define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ 391 #define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ 392 #define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ 393 394 #define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ 395 #define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ 396 #define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ 397 398 #define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ 399 #define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ 400 #define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ 401 #define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ 402 #define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ 403 #define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ 404 #define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ 405 #define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ 406 #define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ 407 #define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ 408 409 #define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ 410 #define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ 411 #define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ 412 #define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ 413 #define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ 414 415 #define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ 416 #define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ 417 #define PM_INSTS { PM } /**< \brief (PM) Instances List */ 418 419 #define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ 420 #define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ 421 #define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ 422 #define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ 423 #define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ 424 #define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ 425 426 #define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ 427 #define PTC_GCLK_ID 27 428 #define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ 429 #define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ 430 431 #define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ 432 #define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ 433 #define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ 434 435 #define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ 436 #define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ 437 #define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ 438 #define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ 439 #define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ 440 #define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ 441 442 #define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ 443 #define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ 444 #define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ 445 446 #define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ 447 #define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ 448 #define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ 449 #define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ 450 #define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ 451 #define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ 452 #define TC_INST_NUM 6 /**< \brief (TC) Number of instances */ 453 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */ 454 455 #define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ 456 #define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ 457 #define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ 458 459 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 460 /*@}*/ 461 462 /* ************************************************************************** */ 463 /** PORT DEFINITIONS FOR SAMD20E17 */ 464 /* ************************************************************************** */ 465 /** \defgroup SAMD20E17_port PORT Definitions */ 466 /*@{*/ 467 468 #include "pio/samd20e17.h" 469 /*@}*/ 470 471 /* ************************************************************************** */ 472 /** MEMORY MAPPING DEFINITIONS FOR SAMD20E17 */ 473 /* ************************************************************************** */ 474 475 #define FLASH_SIZE _UL_(0x00020000) /* 128 kB */ 476 #define FLASH_PAGE_SIZE 64 477 #define FLASH_NB_OF_PAGES 2048 478 #define FLASH_USER_PAGE_SIZE 64 479 #define HRAMC0_SIZE _UL_(0x00004000) /* 16 kB */ 480 481 #define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ 482 #define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ 483 #define HRAMC0_ADDR _UL_(0x20000000) /**< HRAMC0 base address */ 484 #define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ 485 #define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ 486 #define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ 487 #define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ 488 489 #define DSU_DID_RESETVALUE _UL_(0x1000140B) 490 #define PORT_GROUPS 1 491 492 /* ************************************************************************** */ 493 /** ELECTRICAL DEFINITIONS FOR SAMD20E17 */ 494 /* ************************************************************************** */ 495 496 497 #ifdef __cplusplus 498 } 499 #endif 500 501 /*@}*/ 502 503 #endif /* SAMD20E17_H */ 504
