1 /** 2 * \file 3 * 4 * \brief Instance description for GCLK 5 * 6 * Copyright (c) 2017 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMD20_GCLK_INSTANCE_ 31 #define _SAMD20_GCLK_INSTANCE_ 32 33 /* ========== Register definition for GCLK peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_GCLK_CTRL (0x40000C00) /**< \brief (GCLK) Control */ 36 #define REG_GCLK_STATUS (0x40000C01) /**< \brief (GCLK) Status */ 37 #define REG_GCLK_CLKCTRL (0x40000C02) /**< \brief (GCLK) Generic Clock Control */ 38 #define REG_GCLK_GENCTRL (0x40000C04) /**< \brief (GCLK) Generic Clock Generator Control */ 39 #define REG_GCLK_GENDIV (0x40000C08) /**< \brief (GCLK) Generic Clock Generator Division */ 40 #else 41 #define REG_GCLK_CTRL (*(RwReg8 *)0x40000C00UL) /**< \brief (GCLK) Control */ 42 #define REG_GCLK_STATUS (*(RoReg8 *)0x40000C01UL) /**< \brief (GCLK) Status */ 43 #define REG_GCLK_CLKCTRL (*(RwReg16*)0x40000C02UL) /**< \brief (GCLK) Generic Clock Control */ 44 #define REG_GCLK_GENCTRL (*(RwReg *)0x40000C04UL) /**< \brief (GCLK) Generic Clock Generator Control */ 45 #define REG_GCLK_GENDIV (*(RwReg *)0x40000C08UL) /**< \brief (GCLK) Generic Clock Generator Division */ 46 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 47 48 /* ========== Instance parameters for GCLK peripheral ========== */ 49 #define GCLK_GENDIV_BITS 16 50 #define GCLK_GEN_NUM 8 // Number of Generic Clock Generators 51 #define GCLK_GEN_NUM_MSB 7 // Number of Generic Clock Generators - 1 52 #define GCLK_GEN_SOURCE_NUM_MSB 7 // Number of Generic Clock Sources - 1 53 #define GCLK_NUM 28 // Number of Generic Clock Users 54 #define GCLK_SOURCE_DFLL48M 7 55 #define GCLK_SOURCE_GCLKGEN1 2 56 #define GCLK_SOURCE_GCLKIN 1 57 #define GCLK_SOURCE_NUM 8 // Number of Generic Clock Sources 58 #define GCLK_SOURCE_OSCULP32K 3 59 #define GCLK_SOURCE_OSC8M 6 60 #define GCLK_SOURCE_OSC32K 4 61 #define GCLK_SOURCE_XOSC 0 62 #define GCLK_SOURCE_XOSC32K 5 63 64 #endif /* _SAMD20_GCLK_INSTANCE_ */ 65
