1 /** 2 * \file 3 * 4 * \brief Component description for TC 5 * 6 * Copyright (c) 2017 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMD20_TC_COMPONENT_ 31 #define _SAMD20_TC_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR TC */ 35 /* ========================================================================== */ 36 /** \addtogroup SAMD20_TC Basic Timer Counter */ 37 /*@{*/ 38 39 #define TC_U2212 40 #define REV_TC 0x112 41 42 /* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 16) Control A -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint16_t SWRST:1; /*!< bit: 0 Software Reset */ 47 uint16_t ENABLE:1; /*!< bit: 1 Enable */ 48 uint16_t MODE:2; /*!< bit: 2.. 3 TC Mode */ 49 uint16_t :1; /*!< bit: 4 Reserved */ 50 uint16_t WAVEGEN:2; /*!< bit: 5.. 6 Waveform Generation Operation */ 51 uint16_t :1; /*!< bit: 7 Reserved */ 52 uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler */ 53 uint16_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */ 54 uint16_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization */ 55 uint16_t :2; /*!< bit: 14..15 Reserved */ 56 } bit; /*!< Structure used for bit access */ 57 uint16_t reg; /*!< Type used for register access */ 58 } TC_CTRLA_Type; 59 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 60 61 #define TC_CTRLA_OFFSET 0x00 /**< \brief (TC_CTRLA offset) Control A */ 62 #define TC_CTRLA_RESETVALUE _U_(0x0000) /**< \brief (TC_CTRLA reset_value) Control A */ 63 64 #define TC_CTRLA_SWRST_Pos 0 /**< \brief (TC_CTRLA) Software Reset */ 65 #define TC_CTRLA_SWRST (_U_(0x1) << TC_CTRLA_SWRST_Pos) 66 #define TC_CTRLA_ENABLE_Pos 1 /**< \brief (TC_CTRLA) Enable */ 67 #define TC_CTRLA_ENABLE (_U_(0x1) << TC_CTRLA_ENABLE_Pos) 68 #define TC_CTRLA_MODE_Pos 2 /**< \brief (TC_CTRLA) TC Mode */ 69 #define TC_CTRLA_MODE_Msk (_U_(0x3) << TC_CTRLA_MODE_Pos) 70 #define TC_CTRLA_MODE(value) (TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos)) 71 #define TC_CTRLA_MODE_COUNT16_Val _U_(0x0) /**< \brief (TC_CTRLA) Counter in 16-bit mode */ 72 #define TC_CTRLA_MODE_COUNT8_Val _U_(0x1) /**< \brief (TC_CTRLA) Counter in 8-bit mode */ 73 #define TC_CTRLA_MODE_COUNT32_Val _U_(0x2) /**< \brief (TC_CTRLA) Counter in 32-bit mode */ 74 #define TC_CTRLA_MODE_COUNT16 (TC_CTRLA_MODE_COUNT16_Val << TC_CTRLA_MODE_Pos) 75 #define TC_CTRLA_MODE_COUNT8 (TC_CTRLA_MODE_COUNT8_Val << TC_CTRLA_MODE_Pos) 76 #define TC_CTRLA_MODE_COUNT32 (TC_CTRLA_MODE_COUNT32_Val << TC_CTRLA_MODE_Pos) 77 #define TC_CTRLA_WAVEGEN_Pos 5 /**< \brief (TC_CTRLA) Waveform Generation Operation */ 78 #define TC_CTRLA_WAVEGEN_Msk (_U_(0x3) << TC_CTRLA_WAVEGEN_Pos) 79 #define TC_CTRLA_WAVEGEN(value) (TC_CTRLA_WAVEGEN_Msk & ((value) << TC_CTRLA_WAVEGEN_Pos)) 80 #define TC_CTRLA_WAVEGEN_NFRQ_Val _U_(0x0) /**< \brief (TC_CTRLA) */ 81 #define TC_CTRLA_WAVEGEN_MFRQ_Val _U_(0x1) /**< \brief (TC_CTRLA) */ 82 #define TC_CTRLA_WAVEGEN_NPWM_Val _U_(0x2) /**< \brief (TC_CTRLA) */ 83 #define TC_CTRLA_WAVEGEN_MPWM_Val _U_(0x3) /**< \brief (TC_CTRLA) */ 84 #define TC_CTRLA_WAVEGEN_NFRQ (TC_CTRLA_WAVEGEN_NFRQ_Val << TC_CTRLA_WAVEGEN_Pos) 85 #define TC_CTRLA_WAVEGEN_MFRQ (TC_CTRLA_WAVEGEN_MFRQ_Val << TC_CTRLA_WAVEGEN_Pos) 86 #define TC_CTRLA_WAVEGEN_NPWM (TC_CTRLA_WAVEGEN_NPWM_Val << TC_CTRLA_WAVEGEN_Pos) 87 #define TC_CTRLA_WAVEGEN_MPWM (TC_CTRLA_WAVEGEN_MPWM_Val << TC_CTRLA_WAVEGEN_Pos) 88 #define TC_CTRLA_PRESCALER_Pos 8 /**< \brief (TC_CTRLA) Prescaler */ 89 #define TC_CTRLA_PRESCALER_Msk (_U_(0x7) << TC_CTRLA_PRESCALER_Pos) 90 #define TC_CTRLA_PRESCALER(value) (TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos)) 91 #define TC_CTRLA_PRESCALER_DIV1_Val _U_(0x0) /**< \brief (TC_CTRLA) GCLK_TC */ 92 #define TC_CTRLA_PRESCALER_DIV2_Val _U_(0x1) /**< \brief (TC_CTRLA) GCLK_TC/2 */ 93 #define TC_CTRLA_PRESCALER_DIV4_Val _U_(0x2) /**< \brief (TC_CTRLA) GCLK_TC/4 */ 94 #define TC_CTRLA_PRESCALER_DIV8_Val _U_(0x3) /**< \brief (TC_CTRLA) GCLK_TC/8 */ 95 #define TC_CTRLA_PRESCALER_DIV16_Val _U_(0x4) /**< \brief (TC_CTRLA) GCLK_TC/16 */ 96 #define TC_CTRLA_PRESCALER_DIV64_Val _U_(0x5) /**< \brief (TC_CTRLA) GCLK_TC/64 */ 97 #define TC_CTRLA_PRESCALER_DIV256_Val _U_(0x6) /**< \brief (TC_CTRLA) GCLK_TC/256 */ 98 #define TC_CTRLA_PRESCALER_DIV1024_Val _U_(0x7) /**< \brief (TC_CTRLA) GCLK_TC/1024 */ 99 #define TC_CTRLA_PRESCALER_DIV1 (TC_CTRLA_PRESCALER_DIV1_Val << TC_CTRLA_PRESCALER_Pos) 100 #define TC_CTRLA_PRESCALER_DIV2 (TC_CTRLA_PRESCALER_DIV2_Val << TC_CTRLA_PRESCALER_Pos) 101 #define TC_CTRLA_PRESCALER_DIV4 (TC_CTRLA_PRESCALER_DIV4_Val << TC_CTRLA_PRESCALER_Pos) 102 #define TC_CTRLA_PRESCALER_DIV8 (TC_CTRLA_PRESCALER_DIV8_Val << TC_CTRLA_PRESCALER_Pos) 103 #define TC_CTRLA_PRESCALER_DIV16 (TC_CTRLA_PRESCALER_DIV16_Val << TC_CTRLA_PRESCALER_Pos) 104 #define TC_CTRLA_PRESCALER_DIV64 (TC_CTRLA_PRESCALER_DIV64_Val << TC_CTRLA_PRESCALER_Pos) 105 #define TC_CTRLA_PRESCALER_DIV256 (TC_CTRLA_PRESCALER_DIV256_Val << TC_CTRLA_PRESCALER_Pos) 106 #define TC_CTRLA_PRESCALER_DIV1024 (TC_CTRLA_PRESCALER_DIV1024_Val << TC_CTRLA_PRESCALER_Pos) 107 #define TC_CTRLA_RUNSTDBY_Pos 11 /**< \brief (TC_CTRLA) Run in Standby */ 108 #define TC_CTRLA_RUNSTDBY (_U_(0x1) << TC_CTRLA_RUNSTDBY_Pos) 109 #define TC_CTRLA_PRESCSYNC_Pos 12 /**< \brief (TC_CTRLA) Prescaler and Counter Synchronization */ 110 #define TC_CTRLA_PRESCSYNC_Msk (_U_(0x3) << TC_CTRLA_PRESCSYNC_Pos) 111 #define TC_CTRLA_PRESCSYNC(value) (TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos)) 112 #define TC_CTRLA_PRESCSYNC_GCLK_Val _U_(0x0) /**< \brief (TC_CTRLA) Reload or reset Counter on next GCLK */ 113 #define TC_CTRLA_PRESCSYNC_PRESC_Val _U_(0x1) /**< \brief (TC_CTRLA) Reload or reset Counter on next prescaler clock */ 114 #define TC_CTRLA_PRESCSYNC_RESYNC_Val _U_(0x2) /**< \brief (TC_CTRLA) Reload or reset Counter on next GCLK. Reset prescaler counter */ 115 #define TC_CTRLA_PRESCSYNC_GCLK (TC_CTRLA_PRESCSYNC_GCLK_Val << TC_CTRLA_PRESCSYNC_Pos) 116 #define TC_CTRLA_PRESCSYNC_PRESC (TC_CTRLA_PRESCSYNC_PRESC_Val << TC_CTRLA_PRESCSYNC_Pos) 117 #define TC_CTRLA_PRESCSYNC_RESYNC (TC_CTRLA_PRESCSYNC_RESYNC_Val << TC_CTRLA_PRESCSYNC_Pos) 118 #define TC_CTRLA_MASK _U_(0x3F6F) /**< \brief (TC_CTRLA) MASK Register */ 119 120 /* -------- TC_READREQ : (TC Offset: 0x02) (R/W 16) Read Request -------- */ 121 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 122 typedef union { 123 struct { 124 uint16_t ADDR:5; /*!< bit: 0.. 4 Address */ 125 uint16_t :9; /*!< bit: 5..13 Reserved */ 126 uint16_t RCONT:1; /*!< bit: 14 Read Continuously */ 127 uint16_t RREQ:1; /*!< bit: 15 Read Request */ 128 } bit; /*!< Structure used for bit access */ 129 uint16_t reg; /*!< Type used for register access */ 130 } TC_READREQ_Type; 131 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 132 133 #define TC_READREQ_OFFSET 0x02 /**< \brief (TC_READREQ offset) Read Request */ 134 #define TC_READREQ_RESETVALUE _U_(0x0000) /**< \brief (TC_READREQ reset_value) Read Request */ 135 136 #define TC_READREQ_ADDR_Pos 0 /**< \brief (TC_READREQ) Address */ 137 #define TC_READREQ_ADDR_Msk (_U_(0x1F) << TC_READREQ_ADDR_Pos) 138 #define TC_READREQ_ADDR(value) (TC_READREQ_ADDR_Msk & ((value) << TC_READREQ_ADDR_Pos)) 139 #define TC_READREQ_RCONT_Pos 14 /**< \brief (TC_READREQ) Read Continuously */ 140 #define TC_READREQ_RCONT (_U_(0x1) << TC_READREQ_RCONT_Pos) 141 #define TC_READREQ_RREQ_Pos 15 /**< \brief (TC_READREQ) Read Request */ 142 #define TC_READREQ_RREQ (_U_(0x1) << TC_READREQ_RREQ_Pos) 143 #define TC_READREQ_MASK _U_(0xC01F) /**< \brief (TC_READREQ) MASK Register */ 144 145 /* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W 8) Control B Clear -------- */ 146 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 147 typedef union { 148 struct { 149 uint8_t DIR:1; /*!< bit: 0 Counter Direction */ 150 uint8_t :1; /*!< bit: 1 Reserved */ 151 uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ 152 uint8_t :3; /*!< bit: 3.. 5 Reserved */ 153 uint8_t CMD:2; /*!< bit: 6.. 7 Command */ 154 } bit; /*!< Structure used for bit access */ 155 uint8_t reg; /*!< Type used for register access */ 156 } TC_CTRLBCLR_Type; 157 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 158 159 #define TC_CTRLBCLR_OFFSET 0x04 /**< \brief (TC_CTRLBCLR offset) Control B Clear */ 160 #define TC_CTRLBCLR_RESETVALUE _U_(0x02) /**< \brief (TC_CTRLBCLR reset_value) Control B Clear */ 161 162 #define TC_CTRLBCLR_DIR_Pos 0 /**< \brief (TC_CTRLBCLR) Counter Direction */ 163 #define TC_CTRLBCLR_DIR (_U_(0x1) << TC_CTRLBCLR_DIR_Pos) 164 #define TC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TC_CTRLBCLR) One-Shot */ 165 #define TC_CTRLBCLR_ONESHOT (_U_(0x1) << TC_CTRLBCLR_ONESHOT_Pos) 166 #define TC_CTRLBCLR_CMD_Pos 6 /**< \brief (TC_CTRLBCLR) Command */ 167 #define TC_CTRLBCLR_CMD_Msk (_U_(0x3) << TC_CTRLBCLR_CMD_Pos) 168 #define TC_CTRLBCLR_CMD(value) (TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos)) 169 #define TC_CTRLBCLR_CMD_NONE_Val _U_(0x0) /**< \brief (TC_CTRLBCLR) No action */ 170 #define TC_CTRLBCLR_CMD_RETRIGGER_Val _U_(0x1) /**< \brief (TC_CTRLBCLR) Force start, restart or retrigger */ 171 #define TC_CTRLBCLR_CMD_STOP_Val _U_(0x2) /**< \brief (TC_CTRLBCLR) Force stop */ 172 #define TC_CTRLBCLR_CMD_NONE (TC_CTRLBCLR_CMD_NONE_Val << TC_CTRLBCLR_CMD_Pos) 173 #define TC_CTRLBCLR_CMD_RETRIGGER (TC_CTRLBCLR_CMD_RETRIGGER_Val << TC_CTRLBCLR_CMD_Pos) 174 #define TC_CTRLBCLR_CMD_STOP (TC_CTRLBCLR_CMD_STOP_Val << TC_CTRLBCLR_CMD_Pos) 175 #define TC_CTRLBCLR_MASK _U_(0xC5) /**< \brief (TC_CTRLBCLR) MASK Register */ 176 177 /* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W 8) Control B Set -------- */ 178 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 179 typedef union { 180 struct { 181 uint8_t DIR:1; /*!< bit: 0 Counter Direction */ 182 uint8_t :1; /*!< bit: 1 Reserved */ 183 uint8_t ONESHOT:1; /*!< bit: 2 One-shot */ 184 uint8_t :3; /*!< bit: 3.. 5 Reserved */ 185 uint8_t CMD:2; /*!< bit: 6.. 7 Command */ 186 } bit; /*!< Structure used for bit access */ 187 uint8_t reg; /*!< Type used for register access */ 188 } TC_CTRLBSET_Type; 189 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 190 191 #define TC_CTRLBSET_OFFSET 0x05 /**< \brief (TC_CTRLBSET offset) Control B Set */ 192 #define TC_CTRLBSET_RESETVALUE _U_(0x00) /**< \brief (TC_CTRLBSET reset_value) Control B Set */ 193 194 #define TC_CTRLBSET_DIR_Pos 0 /**< \brief (TC_CTRLBSET) Counter Direction */ 195 #define TC_CTRLBSET_DIR (_U_(0x1) << TC_CTRLBSET_DIR_Pos) 196 #define TC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TC_CTRLBSET) One-shot */ 197 #define TC_CTRLBSET_ONESHOT (_U_(0x1) << TC_CTRLBSET_ONESHOT_Pos) 198 #define TC_CTRLBSET_CMD_Pos 6 /**< \brief (TC_CTRLBSET) Command */ 199 #define TC_CTRLBSET_CMD_Msk (_U_(0x3) << TC_CTRLBSET_CMD_Pos) 200 #define TC_CTRLBSET_CMD(value) (TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos)) 201 #define TC_CTRLBSET_CMD_NONE_Val _U_(0x0) /**< \brief (TC_CTRLBSET) No action */ 202 #define TC_CTRLBSET_CMD_RETRIGGER_Val _U_(0x1) /**< \brief (TC_CTRLBSET) Force start, restart or retrigger */ 203 #define TC_CTRLBSET_CMD_STOP_Val _U_(0x2) /**< \brief (TC_CTRLBSET) Force stop */ 204 #define TC_CTRLBSET_CMD_NONE (TC_CTRLBSET_CMD_NONE_Val << TC_CTRLBSET_CMD_Pos) 205 #define TC_CTRLBSET_CMD_RETRIGGER (TC_CTRLBSET_CMD_RETRIGGER_Val << TC_CTRLBSET_CMD_Pos) 206 #define TC_CTRLBSET_CMD_STOP (TC_CTRLBSET_CMD_STOP_Val << TC_CTRLBSET_CMD_Pos) 207 #define TC_CTRLBSET_MASK _U_(0xC5) /**< \brief (TC_CTRLBSET) MASK Register */ 208 209 /* -------- TC_CTRLC : (TC Offset: 0x06) (R/W 8) Control C -------- */ 210 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 211 typedef union { 212 struct { 213 uint8_t INVEN0:1; /*!< bit: 0 Output Waveform 0 Invert Enable */ 214 uint8_t INVEN1:1; /*!< bit: 1 Output Waveform 1 Invert Enable */ 215 uint8_t :2; /*!< bit: 2.. 3 Reserved */ 216 uint8_t CPTEN0:1; /*!< bit: 4 Capture Channel 0 Enable */ 217 uint8_t CPTEN1:1; /*!< bit: 5 Capture Channel 1 Enable */ 218 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 219 } bit; /*!< Structure used for bit access */ 220 struct { 221 uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform x Invert Enable */ 222 uint8_t :2; /*!< bit: 2.. 3 Reserved */ 223 uint8_t CPTEN:2; /*!< bit: 4.. 5 Capture Channel x Enable */ 224 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 225 } vec; /*!< Structure used for vec access */ 226 uint8_t reg; /*!< Type used for register access */ 227 } TC_CTRLC_Type; 228 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 229 230 #define TC_CTRLC_OFFSET 0x06 /**< \brief (TC_CTRLC offset) Control C */ 231 #define TC_CTRLC_RESETVALUE _U_(0x00) /**< \brief (TC_CTRLC reset_value) Control C */ 232 233 #define TC_CTRLC_INVEN0_Pos 0 /**< \brief (TC_CTRLC) Output Waveform 0 Invert Enable */ 234 #define TC_CTRLC_INVEN0 (_U_(1) << TC_CTRLC_INVEN0_Pos) 235 #define TC_CTRLC_INVEN1_Pos 1 /**< \brief (TC_CTRLC) Output Waveform 1 Invert Enable */ 236 #define TC_CTRLC_INVEN1 (_U_(1) << TC_CTRLC_INVEN1_Pos) 237 #define TC_CTRLC_INVEN_Pos 0 /**< \brief (TC_CTRLC) Output Waveform x Invert Enable */ 238 #define TC_CTRLC_INVEN_Msk (_U_(0x3) << TC_CTRLC_INVEN_Pos) 239 #define TC_CTRLC_INVEN(value) (TC_CTRLC_INVEN_Msk & ((value) << TC_CTRLC_INVEN_Pos)) 240 #define TC_CTRLC_CPTEN0_Pos 4 /**< \brief (TC_CTRLC) Capture Channel 0 Enable */ 241 #define TC_CTRLC_CPTEN0 (_U_(1) << TC_CTRLC_CPTEN0_Pos) 242 #define TC_CTRLC_CPTEN1_Pos 5 /**< \brief (TC_CTRLC) Capture Channel 1 Enable */ 243 #define TC_CTRLC_CPTEN1 (_U_(1) << TC_CTRLC_CPTEN1_Pos) 244 #define TC_CTRLC_CPTEN_Pos 4 /**< \brief (TC_CTRLC) Capture Channel x Enable */ 245 #define TC_CTRLC_CPTEN_Msk (_U_(0x3) << TC_CTRLC_CPTEN_Pos) 246 #define TC_CTRLC_CPTEN(value) (TC_CTRLC_CPTEN_Msk & ((value) << TC_CTRLC_CPTEN_Pos)) 247 #define TC_CTRLC_MASK _U_(0x33) /**< \brief (TC_CTRLC) MASK Register */ 248 249 /* -------- TC_DBGCTRL : (TC Offset: 0x08) (R/W 8) Debug Control -------- */ 250 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 251 typedef union { 252 struct { 253 uint8_t DBGRUN:1; /*!< bit: 0 Debug Run Mode */ 254 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 255 } bit; /*!< Structure used for bit access */ 256 uint8_t reg; /*!< Type used for register access */ 257 } TC_DBGCTRL_Type; 258 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 259 260 #define TC_DBGCTRL_OFFSET 0x08 /**< \brief (TC_DBGCTRL offset) Debug Control */ 261 #define TC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (TC_DBGCTRL reset_value) Debug Control */ 262 263 #define TC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TC_DBGCTRL) Debug Run Mode */ 264 #define TC_DBGCTRL_DBGRUN (_U_(0x1) << TC_DBGCTRL_DBGRUN_Pos) 265 #define TC_DBGCTRL_MASK _U_(0x01) /**< \brief (TC_DBGCTRL) MASK Register */ 266 267 /* -------- TC_EVCTRL : (TC Offset: 0x0A) (R/W 16) Event Control -------- */ 268 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 269 typedef union { 270 struct { 271 uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */ 272 uint16_t :1; /*!< bit: 3 Reserved */ 273 uint16_t TCINV:1; /*!< bit: 4 TC Inverted Event Input */ 274 uint16_t TCEI:1; /*!< bit: 5 TC Event Input */ 275 uint16_t :2; /*!< bit: 6.. 7 Reserved */ 276 uint16_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Event Output Enable */ 277 uint16_t :3; /*!< bit: 9..11 Reserved */ 278 uint16_t MCEO0:1; /*!< bit: 12 Match or Capture Channel 0 Event Output Enable */ 279 uint16_t MCEO1:1; /*!< bit: 13 Match or Capture Channel 1 Event Output Enable */ 280 uint16_t :2; /*!< bit: 14..15 Reserved */ 281 } bit; /*!< Structure used for bit access */ 282 struct { 283 uint16_t :12; /*!< bit: 0..11 Reserved */ 284 uint16_t MCEO:2; /*!< bit: 12..13 Match or Capture Channel x Event Output Enable */ 285 uint16_t :2; /*!< bit: 14..15 Reserved */ 286 } vec; /*!< Structure used for vec access */ 287 uint16_t reg; /*!< Type used for register access */ 288 } TC_EVCTRL_Type; 289 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 290 291 #define TC_EVCTRL_OFFSET 0x0A /**< \brief (TC_EVCTRL offset) Event Control */ 292 #define TC_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (TC_EVCTRL reset_value) Event Control */ 293 294 #define TC_EVCTRL_EVACT_Pos 0 /**< \brief (TC_EVCTRL) Event Action */ 295 #define TC_EVCTRL_EVACT_Msk (_U_(0x7) << TC_EVCTRL_EVACT_Pos) 296 #define TC_EVCTRL_EVACT(value) (TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos)) 297 #define TC_EVCTRL_EVACT_OFF_Val _U_(0x0) /**< \brief (TC_EVCTRL) Event action disabled */ 298 #define TC_EVCTRL_EVACT_RETRIGGER_Val _U_(0x1) /**< \brief (TC_EVCTRL) Start, restart or retrigger TC on event */ 299 #define TC_EVCTRL_EVACT_COUNT_Val _U_(0x2) /**< \brief (TC_EVCTRL) Count on event */ 300 #define TC_EVCTRL_EVACT_START_Val _U_(0x3) /**< \brief (TC_EVCTRL) Start TC on event */ 301 #define TC_EVCTRL_EVACT_PPW_Val _U_(0x5) /**< \brief (TC_EVCTRL) Period captured into CC0 Pulse Width in CC1 */ 302 #define TC_EVCTRL_EVACT_PWP_Val _U_(0x6) /**< \brief (TC_EVCTRL) Period captured into CC1 Pulse Width on CC0 */ 303 #define TC_EVCTRL_EVACT_OFF (TC_EVCTRL_EVACT_OFF_Val << TC_EVCTRL_EVACT_Pos) 304 #define TC_EVCTRL_EVACT_RETRIGGER (TC_EVCTRL_EVACT_RETRIGGER_Val << TC_EVCTRL_EVACT_Pos) 305 #define TC_EVCTRL_EVACT_COUNT (TC_EVCTRL_EVACT_COUNT_Val << TC_EVCTRL_EVACT_Pos) 306 #define TC_EVCTRL_EVACT_START (TC_EVCTRL_EVACT_START_Val << TC_EVCTRL_EVACT_Pos) 307 #define TC_EVCTRL_EVACT_PPW (TC_EVCTRL_EVACT_PPW_Val << TC_EVCTRL_EVACT_Pos) 308 #define TC_EVCTRL_EVACT_PWP (TC_EVCTRL_EVACT_PWP_Val << TC_EVCTRL_EVACT_Pos) 309 #define TC_EVCTRL_TCINV_Pos 4 /**< \brief (TC_EVCTRL) TC Inverted Event Input */ 310 #define TC_EVCTRL_TCINV (_U_(0x1) << TC_EVCTRL_TCINV_Pos) 311 #define TC_EVCTRL_TCEI_Pos 5 /**< \brief (TC_EVCTRL) TC Event Input */ 312 #define TC_EVCTRL_TCEI (_U_(0x1) << TC_EVCTRL_TCEI_Pos) 313 #define TC_EVCTRL_OVFEO_Pos 8 /**< \brief (TC_EVCTRL) Overflow/Underflow Event Output Enable */ 314 #define TC_EVCTRL_OVFEO (_U_(0x1) << TC_EVCTRL_OVFEO_Pos) 315 #define TC_EVCTRL_MCEO0_Pos 12 /**< \brief (TC_EVCTRL) Match or Capture Channel 0 Event Output Enable */ 316 #define TC_EVCTRL_MCEO0 (_U_(1) << TC_EVCTRL_MCEO0_Pos) 317 #define TC_EVCTRL_MCEO1_Pos 13 /**< \brief (TC_EVCTRL) Match or Capture Channel 1 Event Output Enable */ 318 #define TC_EVCTRL_MCEO1 (_U_(1) << TC_EVCTRL_MCEO1_Pos) 319 #define TC_EVCTRL_MCEO_Pos 12 /**< \brief (TC_EVCTRL) Match or Capture Channel x Event Output Enable */ 320 #define TC_EVCTRL_MCEO_Msk (_U_(0x3) << TC_EVCTRL_MCEO_Pos) 321 #define TC_EVCTRL_MCEO(value) (TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos)) 322 #define TC_EVCTRL_MASK _U_(0x3137) /**< \brief (TC_EVCTRL) MASK Register */ 323 324 /* -------- TC_INTENCLR : (TC Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */ 325 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 326 typedef union { 327 struct { 328 uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ 329 uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */ 330 uint8_t :1; /*!< bit: 2 Reserved */ 331 uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ 332 uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */ 333 uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */ 334 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 335 } bit; /*!< Structure used for bit access */ 336 struct { 337 uint8_t :4; /*!< bit: 0.. 3 Reserved */ 338 uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */ 339 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 340 } vec; /*!< Structure used for vec access */ 341 uint8_t reg; /*!< Type used for register access */ 342 } TC_INTENCLR_Type; 343 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 344 345 #define TC_INTENCLR_OFFSET 0x0C /**< \brief (TC_INTENCLR offset) Interrupt Enable Clear */ 346 #define TC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (TC_INTENCLR reset_value) Interrupt Enable Clear */ 347 348 #define TC_INTENCLR_OVF_Pos 0 /**< \brief (TC_INTENCLR) Overflow Interrupt Enable */ 349 #define TC_INTENCLR_OVF (_U_(0x1) << TC_INTENCLR_OVF_Pos) 350 #define TC_INTENCLR_ERR_Pos 1 /**< \brief (TC_INTENCLR) Error Interrupt Enable */ 351 #define TC_INTENCLR_ERR (_U_(0x1) << TC_INTENCLR_ERR_Pos) 352 #define TC_INTENCLR_SYNCRDY_Pos 3 /**< \brief (TC_INTENCLR) Synchronization Ready Interrupt Enable */ 353 #define TC_INTENCLR_SYNCRDY (_U_(0x1) << TC_INTENCLR_SYNCRDY_Pos) 354 #define TC_INTENCLR_MC0_Pos 4 /**< \brief (TC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */ 355 #define TC_INTENCLR_MC0 (_U_(1) << TC_INTENCLR_MC0_Pos) 356 #define TC_INTENCLR_MC1_Pos 5 /**< \brief (TC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */ 357 #define TC_INTENCLR_MC1 (_U_(1) << TC_INTENCLR_MC1_Pos) 358 #define TC_INTENCLR_MC_Pos 4 /**< \brief (TC_INTENCLR) Match or Capture Channel x Interrupt Enable */ 359 #define TC_INTENCLR_MC_Msk (_U_(0x3) << TC_INTENCLR_MC_Pos) 360 #define TC_INTENCLR_MC(value) (TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos)) 361 #define TC_INTENCLR_MASK _U_(0x3B) /**< \brief (TC_INTENCLR) MASK Register */ 362 363 /* -------- TC_INTENSET : (TC Offset: 0x0D) (R/W 8) Interrupt Enable Set -------- */ 364 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 365 typedef union { 366 struct { 367 uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ 368 uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */ 369 uint8_t :1; /*!< bit: 2 Reserved */ 370 uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ 371 uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */ 372 uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */ 373 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 374 } bit; /*!< Structure used for bit access */ 375 struct { 376 uint8_t :4; /*!< bit: 0.. 3 Reserved */ 377 uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */ 378 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 379 } vec; /*!< Structure used for vec access */ 380 uint8_t reg; /*!< Type used for register access */ 381 } TC_INTENSET_Type; 382 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 383 384 #define TC_INTENSET_OFFSET 0x0D /**< \brief (TC_INTENSET offset) Interrupt Enable Set */ 385 #define TC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (TC_INTENSET reset_value) Interrupt Enable Set */ 386 387 #define TC_INTENSET_OVF_Pos 0 /**< \brief (TC_INTENSET) Overflow Interrupt Enable */ 388 #define TC_INTENSET_OVF (_U_(0x1) << TC_INTENSET_OVF_Pos) 389 #define TC_INTENSET_ERR_Pos 1 /**< \brief (TC_INTENSET) Error Interrupt Enable */ 390 #define TC_INTENSET_ERR (_U_(0x1) << TC_INTENSET_ERR_Pos) 391 #define TC_INTENSET_SYNCRDY_Pos 3 /**< \brief (TC_INTENSET) Synchronization Ready Interrupt Enable */ 392 #define TC_INTENSET_SYNCRDY (_U_(0x1) << TC_INTENSET_SYNCRDY_Pos) 393 #define TC_INTENSET_MC0_Pos 4 /**< \brief (TC_INTENSET) Match or Capture Channel 0 Interrupt Enable */ 394 #define TC_INTENSET_MC0 (_U_(1) << TC_INTENSET_MC0_Pos) 395 #define TC_INTENSET_MC1_Pos 5 /**< \brief (TC_INTENSET) Match or Capture Channel 1 Interrupt Enable */ 396 #define TC_INTENSET_MC1 (_U_(1) << TC_INTENSET_MC1_Pos) 397 #define TC_INTENSET_MC_Pos 4 /**< \brief (TC_INTENSET) Match or Capture Channel x Interrupt Enable */ 398 #define TC_INTENSET_MC_Msk (_U_(0x3) << TC_INTENSET_MC_Pos) 399 #define TC_INTENSET_MC(value) (TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos)) 400 #define TC_INTENSET_MASK _U_(0x3B) /**< \brief (TC_INTENSET) MASK Register */ 401 402 /* -------- TC_INTFLAG : (TC Offset: 0x0E) (R/W 8) Interrupt Flag Status and Clear -------- */ 403 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 404 typedef union { // __I to avoid read-modify-write on write-to-clear register 405 struct { 406 __I uint8_t OVF:1; /*!< bit: 0 Overflow */ 407 __I uint8_t ERR:1; /*!< bit: 1 Error */ 408 __I uint8_t :1; /*!< bit: 2 Reserved */ 409 __I uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */ 410 __I uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 */ 411 __I uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 */ 412 __I uint8_t :2; /*!< bit: 6.. 7 Reserved */ 413 } bit; /*!< Structure used for bit access */ 414 struct { 415 __I uint8_t :4; /*!< bit: 0.. 3 Reserved */ 416 __I uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x */ 417 __I uint8_t :2; /*!< bit: 6.. 7 Reserved */ 418 } vec; /*!< Structure used for vec access */ 419 uint8_t reg; /*!< Type used for register access */ 420 } TC_INTFLAG_Type; 421 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 422 423 #define TC_INTFLAG_OFFSET 0x0E /**< \brief (TC_INTFLAG offset) Interrupt Flag Status and Clear */ 424 #define TC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (TC_INTFLAG reset_value) Interrupt Flag Status and Clear */ 425 426 #define TC_INTFLAG_OVF_Pos 0 /**< \brief (TC_INTFLAG) Overflow */ 427 #define TC_INTFLAG_OVF (_U_(0x1) << TC_INTFLAG_OVF_Pos) 428 #define TC_INTFLAG_ERR_Pos 1 /**< \brief (TC_INTFLAG) Error */ 429 #define TC_INTFLAG_ERR (_U_(0x1) << TC_INTFLAG_ERR_Pos) 430 #define TC_INTFLAG_SYNCRDY_Pos 3 /**< \brief (TC_INTFLAG) Synchronization Ready */ 431 #define TC_INTFLAG_SYNCRDY (_U_(0x1) << TC_INTFLAG_SYNCRDY_Pos) 432 #define TC_INTFLAG_MC0_Pos 4 /**< \brief (TC_INTFLAG) Match or Capture Channel 0 */ 433 #define TC_INTFLAG_MC0 (_U_(1) << TC_INTFLAG_MC0_Pos) 434 #define TC_INTFLAG_MC1_Pos 5 /**< \brief (TC_INTFLAG) Match or Capture Channel 1 */ 435 #define TC_INTFLAG_MC1 (_U_(1) << TC_INTFLAG_MC1_Pos) 436 #define TC_INTFLAG_MC_Pos 4 /**< \brief (TC_INTFLAG) Match or Capture Channel x */ 437 #define TC_INTFLAG_MC_Msk (_U_(0x3) << TC_INTFLAG_MC_Pos) 438 #define TC_INTFLAG_MC(value) (TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos)) 439 #define TC_INTFLAG_MASK _U_(0x3B) /**< \brief (TC_INTFLAG) MASK Register */ 440 441 /* -------- TC_STATUS : (TC Offset: 0x0F) (R/ 8) Status -------- */ 442 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 443 typedef union { 444 struct { 445 uint8_t :3; /*!< bit: 0.. 2 Reserved */ 446 uint8_t STOP:1; /*!< bit: 3 Stop */ 447 uint8_t SLAVE:1; /*!< bit: 4 Slave */ 448 uint8_t :2; /*!< bit: 5.. 6 Reserved */ 449 uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ 450 } bit; /*!< Structure used for bit access */ 451 uint8_t reg; /*!< Type used for register access */ 452 } TC_STATUS_Type; 453 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 454 455 #define TC_STATUS_OFFSET 0x0F /**< \brief (TC_STATUS offset) Status */ 456 #define TC_STATUS_RESETVALUE _U_(0x08) /**< \brief (TC_STATUS reset_value) Status */ 457 458 #define TC_STATUS_STOP_Pos 3 /**< \brief (TC_STATUS) Stop */ 459 #define TC_STATUS_STOP (_U_(0x1) << TC_STATUS_STOP_Pos) 460 #define TC_STATUS_SLAVE_Pos 4 /**< \brief (TC_STATUS) Slave */ 461 #define TC_STATUS_SLAVE (_U_(0x1) << TC_STATUS_SLAVE_Pos) 462 #define TC_STATUS_SYNCBUSY_Pos 7 /**< \brief (TC_STATUS) Synchronization Busy */ 463 #define TC_STATUS_SYNCBUSY (_U_(0x1) << TC_STATUS_SYNCBUSY_Pos) 464 #define TC_STATUS_MASK _U_(0x98) /**< \brief (TC_STATUS) MASK Register */ 465 466 /* -------- TC_COUNT16_COUNT : (TC Offset: 0x10) (R/W 16) COUNT16 COUNT16 Counter Value -------- */ 467 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 468 typedef union { 469 struct { 470 uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */ 471 } bit; /*!< Structure used for bit access */ 472 uint16_t reg; /*!< Type used for register access */ 473 } TC_COUNT16_COUNT_Type; 474 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 475 476 #define TC_COUNT16_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT16_COUNT offset) COUNT16 Counter Value */ 477 #define TC_COUNT16_COUNT_RESETVALUE _U_(0x0000) /**< \brief (TC_COUNT16_COUNT reset_value) COUNT16 Counter Value */ 478 479 #define TC_COUNT16_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT16_COUNT) Counter Value */ 480 #define TC_COUNT16_COUNT_COUNT_Msk (_U_(0xFFFF) << TC_COUNT16_COUNT_COUNT_Pos) 481 #define TC_COUNT16_COUNT_COUNT(value) (TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos)) 482 #define TC_COUNT16_COUNT_MASK _U_(0xFFFF) /**< \brief (TC_COUNT16_COUNT) MASK Register */ 483 484 /* -------- TC_COUNT32_COUNT : (TC Offset: 0x10) (R/W 32) COUNT32 COUNT32 Counter Value -------- */ 485 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 486 typedef union { 487 struct { 488 uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */ 489 } bit; /*!< Structure used for bit access */ 490 uint32_t reg; /*!< Type used for register access */ 491 } TC_COUNT32_COUNT_Type; 492 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 493 494 #define TC_COUNT32_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT32_COUNT offset) COUNT32 Counter Value */ 495 #define TC_COUNT32_COUNT_RESETVALUE _U_(0x00000000) /**< \brief (TC_COUNT32_COUNT reset_value) COUNT32 Counter Value */ 496 497 #define TC_COUNT32_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT32_COUNT) Counter Value */ 498 #define TC_COUNT32_COUNT_COUNT_Msk (_U_(0xFFFFFFFF) << TC_COUNT32_COUNT_COUNT_Pos) 499 #define TC_COUNT32_COUNT_COUNT(value) (TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos)) 500 #define TC_COUNT32_COUNT_MASK _U_(0xFFFFFFFF) /**< \brief (TC_COUNT32_COUNT) MASK Register */ 501 502 /* -------- TC_COUNT8_COUNT : (TC Offset: 0x10) (R/W 8) COUNT8 COUNT8 Counter Value -------- */ 503 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 504 typedef union { 505 struct { 506 uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */ 507 } bit; /*!< Structure used for bit access */ 508 uint8_t reg; /*!< Type used for register access */ 509 } TC_COUNT8_COUNT_Type; 510 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 511 512 #define TC_COUNT8_COUNT_OFFSET 0x10 /**< \brief (TC_COUNT8_COUNT offset) COUNT8 Counter Value */ 513 #define TC_COUNT8_COUNT_RESETVALUE _U_(0x00) /**< \brief (TC_COUNT8_COUNT reset_value) COUNT8 Counter Value */ 514 515 #define TC_COUNT8_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT8_COUNT) Counter Value */ 516 #define TC_COUNT8_COUNT_COUNT_Msk (_U_(0xFF) << TC_COUNT8_COUNT_COUNT_Pos) 517 #define TC_COUNT8_COUNT_COUNT(value) (TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos)) 518 #define TC_COUNT8_COUNT_MASK _U_(0xFF) /**< \brief (TC_COUNT8_COUNT) MASK Register */ 519 520 /* -------- TC_COUNT8_PER : (TC Offset: 0x14) (R/W 8) COUNT8 COUNT8 Period Value -------- */ 521 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 522 typedef union { 523 struct { 524 uint8_t PER:8; /*!< bit: 0.. 7 Period Value */ 525 } bit; /*!< Structure used for bit access */ 526 uint8_t reg; /*!< Type used for register access */ 527 } TC_COUNT8_PER_Type; 528 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 529 530 #define TC_COUNT8_PER_OFFSET 0x14 /**< \brief (TC_COUNT8_PER offset) COUNT8 Period Value */ 531 #define TC_COUNT8_PER_RESETVALUE _U_(0xFF) /**< \brief (TC_COUNT8_PER reset_value) COUNT8 Period Value */ 532 533 #define TC_COUNT8_PER_PER_Pos 0 /**< \brief (TC_COUNT8_PER) Period Value */ 534 #define TC_COUNT8_PER_PER_Msk (_U_(0xFF) << TC_COUNT8_PER_PER_Pos) 535 #define TC_COUNT8_PER_PER(value) (TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos)) 536 #define TC_COUNT8_PER_MASK _U_(0xFF) /**< \brief (TC_COUNT8_PER) MASK Register */ 537 538 /* -------- TC_COUNT16_CC : (TC Offset: 0x18) (R/W 16) COUNT16 COUNT16 Compare/Capture -------- */ 539 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 540 typedef union { 541 struct { 542 uint16_t CC:16; /*!< bit: 0..15 Compare/Capture Value */ 543 } bit; /*!< Structure used for bit access */ 544 uint16_t reg; /*!< Type used for register access */ 545 } TC_COUNT16_CC_Type; 546 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 547 548 #define TC_COUNT16_CC_OFFSET 0x18 /**< \brief (TC_COUNT16_CC offset) COUNT16 Compare/Capture */ 549 #define TC_COUNT16_CC_RESETVALUE _U_(0x0000) /**< \brief (TC_COUNT16_CC reset_value) COUNT16 Compare/Capture */ 550 551 #define TC_COUNT16_CC_CC_Pos 0 /**< \brief (TC_COUNT16_CC) Compare/Capture Value */ 552 #define TC_COUNT16_CC_CC_Msk (_U_(0xFFFF) << TC_COUNT16_CC_CC_Pos) 553 #define TC_COUNT16_CC_CC(value) (TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos)) 554 #define TC_COUNT16_CC_MASK _U_(0xFFFF) /**< \brief (TC_COUNT16_CC) MASK Register */ 555 556 /* -------- TC_COUNT32_CC : (TC Offset: 0x18) (R/W 32) COUNT32 COUNT32 Compare/Capture -------- */ 557 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 558 typedef union { 559 struct { 560 uint32_t CC:32; /*!< bit: 0..31 Compare/Capture Value */ 561 } bit; /*!< Structure used for bit access */ 562 uint32_t reg; /*!< Type used for register access */ 563 } TC_COUNT32_CC_Type; 564 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 565 566 #define TC_COUNT32_CC_OFFSET 0x18 /**< \brief (TC_COUNT32_CC offset) COUNT32 Compare/Capture */ 567 #define TC_COUNT32_CC_RESETVALUE _U_(0x00000000) /**< \brief (TC_COUNT32_CC reset_value) COUNT32 Compare/Capture */ 568 569 #define TC_COUNT32_CC_CC_Pos 0 /**< \brief (TC_COUNT32_CC) Compare/Capture Value */ 570 #define TC_COUNT32_CC_CC_Msk (_U_(0xFFFFFFFF) << TC_COUNT32_CC_CC_Pos) 571 #define TC_COUNT32_CC_CC(value) (TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos)) 572 #define TC_COUNT32_CC_MASK _U_(0xFFFFFFFF) /**< \brief (TC_COUNT32_CC) MASK Register */ 573 574 /* -------- TC_COUNT8_CC : (TC Offset: 0x18) (R/W 8) COUNT8 COUNT8 Compare/Capture -------- */ 575 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 576 typedef union { 577 struct { 578 uint8_t CC:8; /*!< bit: 0.. 7 Compare/Capture Value */ 579 } bit; /*!< Structure used for bit access */ 580 uint8_t reg; /*!< Type used for register access */ 581 } TC_COUNT8_CC_Type; 582 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 583 584 #define TC_COUNT8_CC_OFFSET 0x18 /**< \brief (TC_COUNT8_CC offset) COUNT8 Compare/Capture */ 585 #define TC_COUNT8_CC_RESETVALUE _U_(0x00) /**< \brief (TC_COUNT8_CC reset_value) COUNT8 Compare/Capture */ 586 587 #define TC_COUNT8_CC_CC_Pos 0 /**< \brief (TC_COUNT8_CC) Compare/Capture Value */ 588 #define TC_COUNT8_CC_CC_Msk (_U_(0xFF) << TC_COUNT8_CC_CC_Pos) 589 #define TC_COUNT8_CC_CC(value) (TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos)) 590 #define TC_COUNT8_CC_MASK _U_(0xFF) /**< \brief (TC_COUNT8_CC) MASK Register */ 591 592 /** \brief TC_COUNT8 hardware registers */ 593 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 594 typedef struct { /* 8-bit Counter Mode */ 595 __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ 596 __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ 597 __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ 598 __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ 599 __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ 600 RoReg8 Reserved1[0x1]; 601 __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */ 602 RoReg8 Reserved2[0x1]; 603 __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */ 604 __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ 605 __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */ 606 __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */ 607 __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */ 608 __IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 8) COUNT8 Counter Value */ 609 RoReg8 Reserved3[0x3]; 610 __IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Period Value */ 611 RoReg8 Reserved4[0x3]; 612 __IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 8) COUNT8 Compare/Capture */ 613 } TcCount8; 614 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 615 616 /** \brief TC_COUNT16 hardware registers */ 617 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 618 typedef struct { /* 16-bit Counter Mode */ 619 __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ 620 __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ 621 __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ 622 __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ 623 __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ 624 RoReg8 Reserved1[0x1]; 625 __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */ 626 RoReg8 Reserved2[0x1]; 627 __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */ 628 __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ 629 __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */ 630 __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */ 631 __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */ 632 __IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) COUNT16 Counter Value */ 633 RoReg8 Reserved3[0x6]; 634 __IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 16) COUNT16 Compare/Capture */ 635 } TcCount16; 636 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 637 638 /** \brief TC_COUNT32 hardware registers */ 639 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 640 typedef struct { /* 32-bit Counter Mode */ 641 __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ 642 __IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ 643 __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ 644 __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ 645 __IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */ 646 RoReg8 Reserved1[0x1]; 647 __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */ 648 RoReg8 Reserved2[0x1]; 649 __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */ 650 __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ 651 __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */ 652 __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */ 653 __I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */ 654 __IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) COUNT32 Counter Value */ 655 RoReg8 Reserved3[0x4]; 656 __IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 32) COUNT32 Compare/Capture */ 657 } TcCount32; 658 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 659 660 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 661 typedef union { 662 TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */ 663 TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */ 664 TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */ 665 } Tc; 666 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 667 668 /*@}*/ 669 670 #endif /* _SAMD20_TC_COMPONENT_ */ 671
