1 /** 2 * \file 3 * 4 * \brief Component description for SERCOM 5 * 6 * Copyright (c) 2017 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMD20_SERCOM_COMPONENT_ 31 #define _SAMD20_SERCOM_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR SERCOM */ 35 /* ========================================================================== */ 36 /** \addtogroup SAMD20_SERCOM Serial Communication Interface */ 37 /*@{*/ 38 39 #define SERCOM_U2201 40 #define REV_SERCOM 0x102 41 42 /* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM I2CM Control A -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint32_t SWRST:1; /*!< bit: 0 Software Reset */ 47 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 48 uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ 49 uint32_t :2; /*!< bit: 5.. 6 Reserved */ 50 uint32_t RUNSTDBY:1; /*!< bit: 7 Run in Standby */ 51 uint32_t :8; /*!< bit: 8..15 Reserved */ 52 uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */ 53 uint32_t :3; /*!< bit: 17..19 Reserved */ 54 uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */ 55 uint32_t :6; /*!< bit: 22..27 Reserved */ 56 uint32_t INACTOUT:2; /*!< bit: 28..29 Inactive Time-out */ 57 uint32_t LOWTOUT:1; /*!< bit: 30 SCL Low Time-out */ 58 uint32_t :1; /*!< bit: 31 Reserved */ 59 } bit; /*!< Structure used for bit access */ 60 uint32_t reg; /*!< Type used for register access */ 61 } SERCOM_I2CM_CTRLA_Type; 62 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 63 64 #define SERCOM_I2CM_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CM_CTRLA offset) I2CM Control A */ 65 #define SERCOM_I2CM_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_CTRLA reset_value) I2CM Control A */ 66 67 #define SERCOM_I2CM_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_CTRLA) Software Reset */ 68 #define SERCOM_I2CM_CTRLA_SWRST (_U_(0x1) << SERCOM_I2CM_CTRLA_SWRST_Pos) 69 #define SERCOM_I2CM_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_CTRLA) Enable */ 70 #define SERCOM_I2CM_CTRLA_ENABLE (_U_(0x1) << SERCOM_I2CM_CTRLA_ENABLE_Pos) 71 #define SERCOM_I2CM_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CM_CTRLA) Operating Mode */ 72 #define SERCOM_I2CM_CTRLA_MODE_Msk (_U_(0x7) << SERCOM_I2CM_CTRLA_MODE_Pos) 73 #define SERCOM_I2CM_CTRLA_MODE(value) (SERCOM_I2CM_CTRLA_MODE_Msk & ((value) << SERCOM_I2CM_CTRLA_MODE_Pos)) 74 #define SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val _U_(0x0) /**< \brief (SERCOM_I2CM_CTRLA) USART mode with external clock */ 75 #define SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val _U_(0x1) /**< \brief (SERCOM_I2CM_CTRLA) USART mode with internal clock */ 76 #define SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val _U_(0x2) /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with external clock */ 77 #define SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val _U_(0x3) /**< \brief (SERCOM_I2CM_CTRLA) SPI mode with internal clock */ 78 #define SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val _U_(0x4) /**< \brief (SERCOM_I2CM_CTRLA) I2C mode with external clock */ 79 #define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val _U_(0x5) /**< \brief (SERCOM_I2CM_CTRLA) I2C mode with internal clock */ 80 #define SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK (SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos) 81 #define SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK (SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos) 82 #define SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE (SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos) 83 #define SERCOM_I2CM_CTRLA_MODE_SPI_MASTER (SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos) 84 #define SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE (SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos) 85 #define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos) 86 #define SERCOM_I2CM_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CM_CTRLA) Run in Standby */ 87 #define SERCOM_I2CM_CTRLA_RUNSTDBY (_U_(0x1) << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos) 88 #define SERCOM_I2CM_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CM_CTRLA) Pin Usage */ 89 #define SERCOM_I2CM_CTRLA_PINOUT (_U_(0x1) << SERCOM_I2CM_CTRLA_PINOUT_Pos) 90 #define SERCOM_I2CM_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CM_CTRLA) SDA Hold Time */ 91 #define SERCOM_I2CM_CTRLA_SDAHOLD_Msk (_U_(0x3) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos) 92 #define SERCOM_I2CM_CTRLA_SDAHOLD(value) (SERCOM_I2CM_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)) 93 #define SERCOM_I2CM_CTRLA_INACTOUT_Pos 28 /**< \brief (SERCOM_I2CM_CTRLA) Inactive Time-out */ 94 #define SERCOM_I2CM_CTRLA_INACTOUT_Msk (_U_(0x3) << SERCOM_I2CM_CTRLA_INACTOUT_Pos) 95 #define SERCOM_I2CM_CTRLA_INACTOUT(value) (SERCOM_I2CM_CTRLA_INACTOUT_Msk & ((value) << SERCOM_I2CM_CTRLA_INACTOUT_Pos)) 96 #define SERCOM_I2CM_CTRLA_LOWTOUT_Pos 30 /**< \brief (SERCOM_I2CM_CTRLA) SCL Low Time-out */ 97 #define SERCOM_I2CM_CTRLA_LOWTOUT (_U_(0x1) << SERCOM_I2CM_CTRLA_LOWTOUT_Pos) 98 #define SERCOM_I2CM_CTRLA_MASK _U_(0x7031009F) /**< \brief (SERCOM_I2CM_CTRLA) MASK Register */ 99 100 /* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS I2CS Control A -------- */ 101 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 102 typedef union { 103 struct { 104 uint32_t SWRST:1; /*!< bit: 0 Software Reset */ 105 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 106 uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ 107 uint32_t :2; /*!< bit: 5.. 6 Reserved */ 108 uint32_t RUNSTDBY:1; /*!< bit: 7 Run in Standby */ 109 uint32_t :8; /*!< bit: 8..15 Reserved */ 110 uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */ 111 uint32_t :3; /*!< bit: 17..19 Reserved */ 112 uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */ 113 uint32_t :8; /*!< bit: 22..29 Reserved */ 114 uint32_t LOWTOUT:1; /*!< bit: 30 SCL Low Time-out */ 115 uint32_t :1; /*!< bit: 31 Reserved */ 116 } bit; /*!< Structure used for bit access */ 117 uint32_t reg; /*!< Type used for register access */ 118 } SERCOM_I2CS_CTRLA_Type; 119 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 120 121 #define SERCOM_I2CS_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CS_CTRLA offset) I2CS Control A */ 122 #define SERCOM_I2CS_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_CTRLA reset_value) I2CS Control A */ 123 124 #define SERCOM_I2CS_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_CTRLA) Software Reset */ 125 #define SERCOM_I2CS_CTRLA_SWRST (_U_(0x1) << SERCOM_I2CS_CTRLA_SWRST_Pos) 126 #define SERCOM_I2CS_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_CTRLA) Enable */ 127 #define SERCOM_I2CS_CTRLA_ENABLE (_U_(0x1) << SERCOM_I2CS_CTRLA_ENABLE_Pos) 128 #define SERCOM_I2CS_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CS_CTRLA) Operating Mode */ 129 #define SERCOM_I2CS_CTRLA_MODE_Msk (_U_(0x7) << SERCOM_I2CS_CTRLA_MODE_Pos) 130 #define SERCOM_I2CS_CTRLA_MODE(value) (SERCOM_I2CS_CTRLA_MODE_Msk & ((value) << SERCOM_I2CS_CTRLA_MODE_Pos)) 131 #define SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val _U_(0x0) /**< \brief (SERCOM_I2CS_CTRLA) USART mode with external clock */ 132 #define SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val _U_(0x1) /**< \brief (SERCOM_I2CS_CTRLA) USART mode with internal clock */ 133 #define SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val _U_(0x2) /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with external clock */ 134 #define SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val _U_(0x3) /**< \brief (SERCOM_I2CS_CTRLA) SPI mode with internal clock */ 135 #define SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val _U_(0x4) /**< \brief (SERCOM_I2CS_CTRLA) I2C mode with external clock */ 136 #define SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val _U_(0x5) /**< \brief (SERCOM_I2CS_CTRLA) I2C mode with internal clock */ 137 #define SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK (SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos) 138 #define SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK (SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos) 139 #define SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE (SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos) 140 #define SERCOM_I2CS_CTRLA_MODE_SPI_MASTER (SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos) 141 #define SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE (SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos) 142 #define SERCOM_I2CS_CTRLA_MODE_I2C_MASTER (SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos) 143 #define SERCOM_I2CS_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CS_CTRLA) Run in Standby */ 144 #define SERCOM_I2CS_CTRLA_RUNSTDBY (_U_(0x1) << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos) 145 #define SERCOM_I2CS_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CS_CTRLA) Pin Usage */ 146 #define SERCOM_I2CS_CTRLA_PINOUT (_U_(0x1) << SERCOM_I2CS_CTRLA_PINOUT_Pos) 147 #define SERCOM_I2CS_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CS_CTRLA) SDA Hold Time */ 148 #define SERCOM_I2CS_CTRLA_SDAHOLD_Msk (_U_(0x3) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos) 149 #define SERCOM_I2CS_CTRLA_SDAHOLD(value) (SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)) 150 #define SERCOM_I2CS_CTRLA_SDAHOLD_DIS_Val _U_(0x0) /**< \brief (SERCOM_I2CS_CTRLA) Disabled */ 151 #define SERCOM_I2CS_CTRLA_SDAHOLD_75_Val _U_(0x1) /**< \brief (SERCOM_I2CS_CTRLA) 50-100 ns hold time */ 152 #define SERCOM_I2CS_CTRLA_SDAHOLD_450_Val _U_(0x2) /**< \brief (SERCOM_I2CS_CTRLA) 300-600 ns hold time */ 153 #define SERCOM_I2CS_CTRLA_SDAHOLD_600_Val _U_(0x3) /**< \brief (SERCOM_I2CS_CTRLA) 400-800 ns hold time */ 154 #define SERCOM_I2CS_CTRLA_SDAHOLD_DIS (SERCOM_I2CS_CTRLA_SDAHOLD_DIS_Val << SERCOM_I2CS_CTRLA_SDAHOLD_Pos) 155 #define SERCOM_I2CS_CTRLA_SDAHOLD_75 (SERCOM_I2CS_CTRLA_SDAHOLD_75_Val << SERCOM_I2CS_CTRLA_SDAHOLD_Pos) 156 #define SERCOM_I2CS_CTRLA_SDAHOLD_450 (SERCOM_I2CS_CTRLA_SDAHOLD_450_Val << SERCOM_I2CS_CTRLA_SDAHOLD_Pos) 157 #define SERCOM_I2CS_CTRLA_SDAHOLD_600 (SERCOM_I2CS_CTRLA_SDAHOLD_600_Val << SERCOM_I2CS_CTRLA_SDAHOLD_Pos) 158 #define SERCOM_I2CS_CTRLA_LOWTOUT_Pos 30 /**< \brief (SERCOM_I2CS_CTRLA) SCL Low Time-out */ 159 #define SERCOM_I2CS_CTRLA_LOWTOUT (_U_(0x1) << SERCOM_I2CS_CTRLA_LOWTOUT_Pos) 160 #define SERCOM_I2CS_CTRLA_MASK _U_(0x4031009F) /**< \brief (SERCOM_I2CS_CTRLA) MASK Register */ 161 162 /* -------- SERCOM_SPI_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPI SPI Control A -------- */ 163 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 164 typedef union { 165 struct { 166 uint32_t SWRST:1; /*!< bit: 0 Software Reset */ 167 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 168 uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ 169 uint32_t :2; /*!< bit: 5.. 6 Reserved */ 170 uint32_t RUNSTDBY:1; /*!< bit: 7 Run In Standby */ 171 uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */ 172 uint32_t :7; /*!< bit: 9..15 Reserved */ 173 uint32_t DOPO:2; /*!< bit: 16..17 Data Out Pinout */ 174 uint32_t :2; /*!< bit: 18..19 Reserved */ 175 uint32_t DIPO:2; /*!< bit: 20..21 Data In Pinout */ 176 uint32_t :2; /*!< bit: 22..23 Reserved */ 177 uint32_t FORM:4; /*!< bit: 24..27 Frame Format */ 178 uint32_t CPHA:1; /*!< bit: 28 Clock Phase */ 179 uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */ 180 uint32_t DORD:1; /*!< bit: 30 Data Order */ 181 uint32_t :1; /*!< bit: 31 Reserved */ 182 } bit; /*!< Structure used for bit access */ 183 uint32_t reg; /*!< Type used for register access */ 184 } SERCOM_SPI_CTRLA_Type; 185 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 186 187 #define SERCOM_SPI_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_SPI_CTRLA offset) SPI Control A */ 188 #define SERCOM_SPI_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_CTRLA reset_value) SPI Control A */ 189 190 #define SERCOM_SPI_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_SPI_CTRLA) Software Reset */ 191 #define SERCOM_SPI_CTRLA_SWRST (_U_(0x1) << SERCOM_SPI_CTRLA_SWRST_Pos) 192 #define SERCOM_SPI_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_CTRLA) Enable */ 193 #define SERCOM_SPI_CTRLA_ENABLE (_U_(0x1) << SERCOM_SPI_CTRLA_ENABLE_Pos) 194 #define SERCOM_SPI_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_SPI_CTRLA) Operating Mode */ 195 #define SERCOM_SPI_CTRLA_MODE_Msk (_U_(0x7) << SERCOM_SPI_CTRLA_MODE_Pos) 196 #define SERCOM_SPI_CTRLA_MODE(value) (SERCOM_SPI_CTRLA_MODE_Msk & ((value) << SERCOM_SPI_CTRLA_MODE_Pos)) 197 #define SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK_Val _U_(0x0) /**< \brief (SERCOM_SPI_CTRLA) USART mode with external clock */ 198 #define SERCOM_SPI_CTRLA_MODE_USART_INT_CLK_Val _U_(0x1) /**< \brief (SERCOM_SPI_CTRLA) USART mode with internal clock */ 199 #define SERCOM_SPI_CTRLA_MODE_SPI_SLAVE_Val _U_(0x2) /**< \brief (SERCOM_SPI_CTRLA) SPI mode with external clock */ 200 #define SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val _U_(0x3) /**< \brief (SERCOM_SPI_CTRLA) SPI mode with internal clock */ 201 #define SERCOM_SPI_CTRLA_MODE_I2C_SLAVE_Val _U_(0x4) /**< \brief (SERCOM_SPI_CTRLA) I2C mode with external clock */ 202 #define SERCOM_SPI_CTRLA_MODE_I2C_MASTER_Val _U_(0x5) /**< \brief (SERCOM_SPI_CTRLA) I2C mode with internal clock */ 203 #define SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK (SERCOM_SPI_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_SPI_CTRLA_MODE_Pos) 204 #define SERCOM_SPI_CTRLA_MODE_USART_INT_CLK (SERCOM_SPI_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_SPI_CTRLA_MODE_Pos) 205 #define SERCOM_SPI_CTRLA_MODE_SPI_SLAVE (SERCOM_SPI_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_SPI_CTRLA_MODE_Pos) 206 #define SERCOM_SPI_CTRLA_MODE_SPI_MASTER (SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val << SERCOM_SPI_CTRLA_MODE_Pos) 207 #define SERCOM_SPI_CTRLA_MODE_I2C_SLAVE (SERCOM_SPI_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_SPI_CTRLA_MODE_Pos) 208 #define SERCOM_SPI_CTRLA_MODE_I2C_MASTER (SERCOM_SPI_CTRLA_MODE_I2C_MASTER_Val << SERCOM_SPI_CTRLA_MODE_Pos) 209 #define SERCOM_SPI_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_SPI_CTRLA) Run In Standby */ 210 #define SERCOM_SPI_CTRLA_RUNSTDBY (_U_(0x1) << SERCOM_SPI_CTRLA_RUNSTDBY_Pos) 211 #define SERCOM_SPI_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_SPI_CTRLA) Immediate Buffer Overflow Notification */ 212 #define SERCOM_SPI_CTRLA_IBON (_U_(0x1) << SERCOM_SPI_CTRLA_IBON_Pos) 213 #define SERCOM_SPI_CTRLA_DOPO_Pos 16 /**< \brief (SERCOM_SPI_CTRLA) Data Out Pinout */ 214 #define SERCOM_SPI_CTRLA_DOPO_Msk (_U_(0x3) << SERCOM_SPI_CTRLA_DOPO_Pos) 215 #define SERCOM_SPI_CTRLA_DOPO(value) (SERCOM_SPI_CTRLA_DOPO_Msk & ((value) << SERCOM_SPI_CTRLA_DOPO_Pos)) 216 #define SERCOM_SPI_CTRLA_DIPO_Pos 20 /**< \brief (SERCOM_SPI_CTRLA) Data In Pinout */ 217 #define SERCOM_SPI_CTRLA_DIPO_Msk (_U_(0x3) << SERCOM_SPI_CTRLA_DIPO_Pos) 218 #define SERCOM_SPI_CTRLA_DIPO(value) (SERCOM_SPI_CTRLA_DIPO_Msk & ((value) << SERCOM_SPI_CTRLA_DIPO_Pos)) 219 #define SERCOM_SPI_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_SPI_CTRLA) Frame Format */ 220 #define SERCOM_SPI_CTRLA_FORM_Msk (_U_(0xF) << SERCOM_SPI_CTRLA_FORM_Pos) 221 #define SERCOM_SPI_CTRLA_FORM(value) (SERCOM_SPI_CTRLA_FORM_Msk & ((value) << SERCOM_SPI_CTRLA_FORM_Pos)) 222 #define SERCOM_SPI_CTRLA_FORM_SPI_Val _U_(0x0) /**< \brief (SERCOM_SPI_CTRLA) SPI frame */ 223 #define SERCOM_SPI_CTRLA_FORM_SPI_ADDR_Val _U_(0x2) /**< \brief (SERCOM_SPI_CTRLA) SPI frame with address */ 224 #define SERCOM_SPI_CTRLA_FORM_SPI (SERCOM_SPI_CTRLA_FORM_SPI_Val << SERCOM_SPI_CTRLA_FORM_Pos) 225 #define SERCOM_SPI_CTRLA_FORM_SPI_ADDR (SERCOM_SPI_CTRLA_FORM_SPI_ADDR_Val << SERCOM_SPI_CTRLA_FORM_Pos) 226 #define SERCOM_SPI_CTRLA_CPHA_Pos 28 /**< \brief (SERCOM_SPI_CTRLA) Clock Phase */ 227 #define SERCOM_SPI_CTRLA_CPHA (_U_(0x1) << SERCOM_SPI_CTRLA_CPHA_Pos) 228 #define SERCOM_SPI_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_SPI_CTRLA) Clock Polarity */ 229 #define SERCOM_SPI_CTRLA_CPOL (_U_(0x1) << SERCOM_SPI_CTRLA_CPOL_Pos) 230 #define SERCOM_SPI_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_SPI_CTRLA) Data Order */ 231 #define SERCOM_SPI_CTRLA_DORD (_U_(0x1) << SERCOM_SPI_CTRLA_DORD_Pos) 232 #define SERCOM_SPI_CTRLA_MASK _U_(0x7F33019F) /**< \brief (SERCOM_SPI_CTRLA) MASK Register */ 233 234 /* -------- SERCOM_USART_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART USART Control A -------- */ 235 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 236 typedef union { 237 struct { 238 uint32_t SWRST:1; /*!< bit: 0 Software Reset */ 239 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 240 uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ 241 uint32_t :2; /*!< bit: 5.. 6 Reserved */ 242 uint32_t RUNSTDBY:1; /*!< bit: 7 Run In Standby */ 243 uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */ 244 uint32_t :7; /*!< bit: 9..15 Reserved */ 245 uint32_t TXPO:1; /*!< bit: 16 Transmit Data Pinout */ 246 uint32_t :3; /*!< bit: 17..19 Reserved */ 247 uint32_t RXPO:2; /*!< bit: 20..21 Receive Data Pinout */ 248 uint32_t :2; /*!< bit: 22..23 Reserved */ 249 uint32_t FORM:4; /*!< bit: 24..27 Frame Format */ 250 uint32_t CMODE:1; /*!< bit: 28 Communication Mode */ 251 uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */ 252 uint32_t DORD:1; /*!< bit: 30 Data Order */ 253 uint32_t :1; /*!< bit: 31 Reserved */ 254 } bit; /*!< Structure used for bit access */ 255 uint32_t reg; /*!< Type used for register access */ 256 } SERCOM_USART_CTRLA_Type; 257 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 258 259 #define SERCOM_USART_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_USART_CTRLA offset) USART Control A */ 260 #define SERCOM_USART_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_CTRLA reset_value) USART Control A */ 261 262 #define SERCOM_USART_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_USART_CTRLA) Software Reset */ 263 #define SERCOM_USART_CTRLA_SWRST (_U_(0x1) << SERCOM_USART_CTRLA_SWRST_Pos) 264 #define SERCOM_USART_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_USART_CTRLA) Enable */ 265 #define SERCOM_USART_CTRLA_ENABLE (_U_(0x1) << SERCOM_USART_CTRLA_ENABLE_Pos) 266 #define SERCOM_USART_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_USART_CTRLA) Operating Mode */ 267 #define SERCOM_USART_CTRLA_MODE_Msk (_U_(0x7) << SERCOM_USART_CTRLA_MODE_Pos) 268 #define SERCOM_USART_CTRLA_MODE(value) (SERCOM_USART_CTRLA_MODE_Msk & ((value) << SERCOM_USART_CTRLA_MODE_Pos)) 269 #define SERCOM_USART_CTRLA_MODE_USART_EXT_CLK_Val _U_(0x0) /**< \brief (SERCOM_USART_CTRLA) USART mode with external clock */ 270 #define SERCOM_USART_CTRLA_MODE_USART_INT_CLK_Val _U_(0x1) /**< \brief (SERCOM_USART_CTRLA) USART mode with internal clock */ 271 #define SERCOM_USART_CTRLA_MODE_SPI_SLAVE_Val _U_(0x2) /**< \brief (SERCOM_USART_CTRLA) SPI mode with external clock */ 272 #define SERCOM_USART_CTRLA_MODE_SPI_MASTER_Val _U_(0x3) /**< \brief (SERCOM_USART_CTRLA) SPI mode with internal clock */ 273 #define SERCOM_USART_CTRLA_MODE_I2C_SLAVE_Val _U_(0x4) /**< \brief (SERCOM_USART_CTRLA) I2C mode with external clock */ 274 #define SERCOM_USART_CTRLA_MODE_I2C_MASTER_Val _U_(0x5) /**< \brief (SERCOM_USART_CTRLA) I2C mode with internal clock */ 275 #define SERCOM_USART_CTRLA_MODE_USART_EXT_CLK (SERCOM_USART_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_USART_CTRLA_MODE_Pos) 276 #define SERCOM_USART_CTRLA_MODE_USART_INT_CLK (SERCOM_USART_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_USART_CTRLA_MODE_Pos) 277 #define SERCOM_USART_CTRLA_MODE_SPI_SLAVE (SERCOM_USART_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_USART_CTRLA_MODE_Pos) 278 #define SERCOM_USART_CTRLA_MODE_SPI_MASTER (SERCOM_USART_CTRLA_MODE_SPI_MASTER_Val << SERCOM_USART_CTRLA_MODE_Pos) 279 #define SERCOM_USART_CTRLA_MODE_I2C_SLAVE (SERCOM_USART_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_USART_CTRLA_MODE_Pos) 280 #define SERCOM_USART_CTRLA_MODE_I2C_MASTER (SERCOM_USART_CTRLA_MODE_I2C_MASTER_Val << SERCOM_USART_CTRLA_MODE_Pos) 281 #define SERCOM_USART_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_USART_CTRLA) Run In Standby */ 282 #define SERCOM_USART_CTRLA_RUNSTDBY (_U_(0x1) << SERCOM_USART_CTRLA_RUNSTDBY_Pos) 283 #define SERCOM_USART_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_USART_CTRLA) Immediate Buffer Overflow Notification */ 284 #define SERCOM_USART_CTRLA_IBON (_U_(0x1) << SERCOM_USART_CTRLA_IBON_Pos) 285 #define SERCOM_USART_CTRLA_TXPO_Pos 16 /**< \brief (SERCOM_USART_CTRLA) Transmit Data Pinout */ 286 #define SERCOM_USART_CTRLA_TXPO (_U_(0x1) << SERCOM_USART_CTRLA_TXPO_Pos) 287 #define SERCOM_USART_CTRLA_TXPO_PAD0_Val _U_(0x0) /**< \brief (SERCOM_USART_CTRLA) TXD at PAD0, XCK at PAD1 */ 288 #define SERCOM_USART_CTRLA_TXPO_PAD2_Val _U_(0x1) /**< \brief (SERCOM_USART_CTRLA) TXD at PAD2, XCK at PAD3 */ 289 #define SERCOM_USART_CTRLA_TXPO_PAD0 (SERCOM_USART_CTRLA_TXPO_PAD0_Val << SERCOM_USART_CTRLA_TXPO_Pos) 290 #define SERCOM_USART_CTRLA_TXPO_PAD2 (SERCOM_USART_CTRLA_TXPO_PAD2_Val << SERCOM_USART_CTRLA_TXPO_Pos) 291 #define SERCOM_USART_CTRLA_RXPO_Pos 20 /**< \brief (SERCOM_USART_CTRLA) Receive Data Pinout */ 292 #define SERCOM_USART_CTRLA_RXPO_Msk (_U_(0x3) << SERCOM_USART_CTRLA_RXPO_Pos) 293 #define SERCOM_USART_CTRLA_RXPO(value) (SERCOM_USART_CTRLA_RXPO_Msk & ((value) << SERCOM_USART_CTRLA_RXPO_Pos)) 294 #define SERCOM_USART_CTRLA_RXPO_PAD0_Val _U_(0x0) /**< \brief (SERCOM_USART_CTRLA) SERCOM_PAD0 */ 295 #define SERCOM_USART_CTRLA_RXPO_PAD1_Val _U_(0x1) /**< \brief (SERCOM_USART_CTRLA) SERCOM_PAD1 */ 296 #define SERCOM_USART_CTRLA_RXPO_PAD2_Val _U_(0x2) /**< \brief (SERCOM_USART_CTRLA) SERCOM_PAD2 */ 297 #define SERCOM_USART_CTRLA_RXPO_PAD3_Val _U_(0x3) /**< \brief (SERCOM_USART_CTRLA) SERCOM_PAD3 */ 298 #define SERCOM_USART_CTRLA_RXPO_PAD0 (SERCOM_USART_CTRLA_RXPO_PAD0_Val << SERCOM_USART_CTRLA_RXPO_Pos) 299 #define SERCOM_USART_CTRLA_RXPO_PAD1 (SERCOM_USART_CTRLA_RXPO_PAD1_Val << SERCOM_USART_CTRLA_RXPO_Pos) 300 #define SERCOM_USART_CTRLA_RXPO_PAD2 (SERCOM_USART_CTRLA_RXPO_PAD2_Val << SERCOM_USART_CTRLA_RXPO_Pos) 301 #define SERCOM_USART_CTRLA_RXPO_PAD3 (SERCOM_USART_CTRLA_RXPO_PAD3_Val << SERCOM_USART_CTRLA_RXPO_Pos) 302 #define SERCOM_USART_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_USART_CTRLA) Frame Format */ 303 #define SERCOM_USART_CTRLA_FORM_Msk (_U_(0xF) << SERCOM_USART_CTRLA_FORM_Pos) 304 #define SERCOM_USART_CTRLA_FORM(value) (SERCOM_USART_CTRLA_FORM_Msk & ((value) << SERCOM_USART_CTRLA_FORM_Pos)) 305 #define SERCOM_USART_CTRLA_FORM_0_Val _U_(0x0) /**< \brief (SERCOM_USART_CTRLA) USART frame */ 306 #define SERCOM_USART_CTRLA_FORM_1_Val _U_(0x1) /**< \brief (SERCOM_USART_CTRLA) USART frame with parity */ 307 #define SERCOM_USART_CTRLA_FORM_0 (SERCOM_USART_CTRLA_FORM_0_Val << SERCOM_USART_CTRLA_FORM_Pos) 308 #define SERCOM_USART_CTRLA_FORM_1 (SERCOM_USART_CTRLA_FORM_1_Val << SERCOM_USART_CTRLA_FORM_Pos) 309 #define SERCOM_USART_CTRLA_CMODE_Pos 28 /**< \brief (SERCOM_USART_CTRLA) Communication Mode */ 310 #define SERCOM_USART_CTRLA_CMODE (_U_(0x1) << SERCOM_USART_CTRLA_CMODE_Pos) 311 #define SERCOM_USART_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_USART_CTRLA) Clock Polarity */ 312 #define SERCOM_USART_CTRLA_CPOL (_U_(0x1) << SERCOM_USART_CTRLA_CPOL_Pos) 313 #define SERCOM_USART_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_USART_CTRLA) Data Order */ 314 #define SERCOM_USART_CTRLA_DORD (_U_(0x1) << SERCOM_USART_CTRLA_DORD_Pos) 315 #define SERCOM_USART_CTRLA_MASK _U_(0x7F31019F) /**< \brief (SERCOM_USART_CTRLA) MASK Register */ 316 317 /* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM I2CM Control B -------- */ 318 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 319 typedef union { 320 struct { 321 uint32_t :8; /*!< bit: 0.. 7 Reserved */ 322 uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */ 323 uint32_t QCEN:1; /*!< bit: 9 Quick Command Enable */ 324 uint32_t :6; /*!< bit: 10..15 Reserved */ 325 uint32_t CMD:2; /*!< bit: 16..17 Command */ 326 uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */ 327 uint32_t :13; /*!< bit: 19..31 Reserved */ 328 } bit; /*!< Structure used for bit access */ 329 uint32_t reg; /*!< Type used for register access */ 330 } SERCOM_I2CM_CTRLB_Type; 331 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 332 333 #define SERCOM_I2CM_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CM_CTRLB offset) I2CM Control B */ 334 #define SERCOM_I2CM_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_CTRLB reset_value) I2CM Control B */ 335 336 #define SERCOM_I2CM_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CM_CTRLB) Smart Mode Enable */ 337 #define SERCOM_I2CM_CTRLB_SMEN (_U_(0x1) << SERCOM_I2CM_CTRLB_SMEN_Pos) 338 #define SERCOM_I2CM_CTRLB_QCEN_Pos 9 /**< \brief (SERCOM_I2CM_CTRLB) Quick Command Enable */ 339 #define SERCOM_I2CM_CTRLB_QCEN (_U_(0x1) << SERCOM_I2CM_CTRLB_QCEN_Pos) 340 #define SERCOM_I2CM_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CM_CTRLB) Command */ 341 #define SERCOM_I2CM_CTRLB_CMD_Msk (_U_(0x3) << SERCOM_I2CM_CTRLB_CMD_Pos) 342 #define SERCOM_I2CM_CTRLB_CMD(value) (SERCOM_I2CM_CTRLB_CMD_Msk & ((value) << SERCOM_I2CM_CTRLB_CMD_Pos)) 343 #define SERCOM_I2CM_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CM_CTRLB) Acknowledge Action */ 344 #define SERCOM_I2CM_CTRLB_ACKACT (_U_(0x1) << SERCOM_I2CM_CTRLB_ACKACT_Pos) 345 #define SERCOM_I2CM_CTRLB_MASK _U_(0x00070300) /**< \brief (SERCOM_I2CM_CTRLB) MASK Register */ 346 347 /* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS I2CS Control B -------- */ 348 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 349 typedef union { 350 struct { 351 uint32_t :8; /*!< bit: 0.. 7 Reserved */ 352 uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */ 353 uint32_t :5; /*!< bit: 9..13 Reserved */ 354 uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */ 355 uint32_t CMD:2; /*!< bit: 16..17 Command */ 356 uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */ 357 uint32_t :13; /*!< bit: 19..31 Reserved */ 358 } bit; /*!< Structure used for bit access */ 359 uint32_t reg; /*!< Type used for register access */ 360 } SERCOM_I2CS_CTRLB_Type; 361 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 362 363 #define SERCOM_I2CS_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CS_CTRLB offset) I2CS Control B */ 364 #define SERCOM_I2CS_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_CTRLB reset_value) I2CS Control B */ 365 366 #define SERCOM_I2CS_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CS_CTRLB) Smart Mode Enable */ 367 #define SERCOM_I2CS_CTRLB_SMEN (_U_(0x1) << SERCOM_I2CS_CTRLB_SMEN_Pos) 368 #define SERCOM_I2CS_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_I2CS_CTRLB) Address Mode */ 369 #define SERCOM_I2CS_CTRLB_AMODE_Msk (_U_(0x3) << SERCOM_I2CS_CTRLB_AMODE_Pos) 370 #define SERCOM_I2CS_CTRLB_AMODE(value) (SERCOM_I2CS_CTRLB_AMODE_Msk & ((value) << SERCOM_I2CS_CTRLB_AMODE_Pos)) 371 #define SERCOM_I2CS_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CS_CTRLB) Command */ 372 #define SERCOM_I2CS_CTRLB_CMD_Msk (_U_(0x3) << SERCOM_I2CS_CTRLB_CMD_Pos) 373 #define SERCOM_I2CS_CTRLB_CMD(value) (SERCOM_I2CS_CTRLB_CMD_Msk & ((value) << SERCOM_I2CS_CTRLB_CMD_Pos)) 374 #define SERCOM_I2CS_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CS_CTRLB) Acknowledge Action */ 375 #define SERCOM_I2CS_CTRLB_ACKACT (_U_(0x1) << SERCOM_I2CS_CTRLB_ACKACT_Pos) 376 #define SERCOM_I2CS_CTRLB_MASK _U_(0x0007C100) /**< \brief (SERCOM_I2CS_CTRLB) MASK Register */ 377 378 /* -------- SERCOM_SPI_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPI SPI Control B -------- */ 379 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 380 typedef union { 381 struct { 382 uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */ 383 uint32_t :3; /*!< bit: 3.. 5 Reserved */ 384 uint32_t PLOADEN:1; /*!< bit: 6 Slave Data Preload Enable */ 385 uint32_t :7; /*!< bit: 7..13 Reserved */ 386 uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */ 387 uint32_t :1; /*!< bit: 16 Reserved */ 388 uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */ 389 uint32_t :14; /*!< bit: 18..31 Reserved */ 390 } bit; /*!< Structure used for bit access */ 391 uint32_t reg; /*!< Type used for register access */ 392 } SERCOM_SPI_CTRLB_Type; 393 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 394 395 #define SERCOM_SPI_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_SPI_CTRLB offset) SPI Control B */ 396 #define SERCOM_SPI_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_CTRLB reset_value) SPI Control B */ 397 398 #define SERCOM_SPI_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_SPI_CTRLB) Character Size */ 399 #define SERCOM_SPI_CTRLB_CHSIZE_Msk (_U_(0x7) << SERCOM_SPI_CTRLB_CHSIZE_Pos) 400 #define SERCOM_SPI_CTRLB_CHSIZE(value) (SERCOM_SPI_CTRLB_CHSIZE_Msk & ((value) << SERCOM_SPI_CTRLB_CHSIZE_Pos)) 401 #define SERCOM_SPI_CTRLB_PLOADEN_Pos 6 /**< \brief (SERCOM_SPI_CTRLB) Slave Data Preload Enable */ 402 #define SERCOM_SPI_CTRLB_PLOADEN (_U_(0x1) << SERCOM_SPI_CTRLB_PLOADEN_Pos) 403 #define SERCOM_SPI_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_SPI_CTRLB) Address Mode */ 404 #define SERCOM_SPI_CTRLB_AMODE_Msk (_U_(0x3) << SERCOM_SPI_CTRLB_AMODE_Pos) 405 #define SERCOM_SPI_CTRLB_AMODE(value) (SERCOM_SPI_CTRLB_AMODE_Msk & ((value) << SERCOM_SPI_CTRLB_AMODE_Pos)) 406 #define SERCOM_SPI_CTRLB_AMODE_MASK_Val _U_(0x0) /**< \brief (SERCOM_SPI_CTRLB) ADDRMASK is used as a mask to the ADDR register. */ 407 #define SERCOM_SPI_CTRLB_AMODE_2ADDR_Val _U_(0x1) /**< \brief (SERCOM_SPI_CTRLB) The slave responds to the 2 unique addresses in ADDR and ADDRMASK. */ 408 #define SERCOM_SPI_CTRLB_AMODE_RANGE_Val _U_(0x2) /**< \brief (SERCOM_SPI_CTRLB) The slave responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit. */ 409 #define SERCOM_SPI_CTRLB_AMODE_MASK (SERCOM_SPI_CTRLB_AMODE_MASK_Val << SERCOM_SPI_CTRLB_AMODE_Pos) 410 #define SERCOM_SPI_CTRLB_AMODE_2ADDR (SERCOM_SPI_CTRLB_AMODE_2ADDR_Val << SERCOM_SPI_CTRLB_AMODE_Pos) 411 #define SERCOM_SPI_CTRLB_AMODE_RANGE (SERCOM_SPI_CTRLB_AMODE_RANGE_Val << SERCOM_SPI_CTRLB_AMODE_Pos) 412 #define SERCOM_SPI_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_SPI_CTRLB) Receiver Enable */ 413 #define SERCOM_SPI_CTRLB_RXEN (_U_(0x1) << SERCOM_SPI_CTRLB_RXEN_Pos) 414 #define SERCOM_SPI_CTRLB_MASK _U_(0x0002C047) /**< \brief (SERCOM_SPI_CTRLB) MASK Register */ 415 416 /* -------- SERCOM_USART_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART USART Control B -------- */ 417 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 418 typedef union { 419 struct { 420 uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */ 421 uint32_t :3; /*!< bit: 3.. 5 Reserved */ 422 uint32_t SBMODE:1; /*!< bit: 6 Stop Bit Mode */ 423 uint32_t :2; /*!< bit: 7.. 8 Reserved */ 424 uint32_t SFDE:1; /*!< bit: 9 Start of Frame Detection Enable */ 425 uint32_t :3; /*!< bit: 10..12 Reserved */ 426 uint32_t PMODE:1; /*!< bit: 13 Parity Mode */ 427 uint32_t :2; /*!< bit: 14..15 Reserved */ 428 uint32_t TXEN:1; /*!< bit: 16 Transmitter Enable */ 429 uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */ 430 uint32_t :14; /*!< bit: 18..31 Reserved */ 431 } bit; /*!< Structure used for bit access */ 432 uint32_t reg; /*!< Type used for register access */ 433 } SERCOM_USART_CTRLB_Type; 434 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 435 436 #define SERCOM_USART_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_USART_CTRLB offset) USART Control B */ 437 #define SERCOM_USART_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_CTRLB reset_value) USART Control B */ 438 439 #define SERCOM_USART_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_USART_CTRLB) Character Size */ 440 #define SERCOM_USART_CTRLB_CHSIZE_Msk (_U_(0x7) << SERCOM_USART_CTRLB_CHSIZE_Pos) 441 #define SERCOM_USART_CTRLB_CHSIZE(value) (SERCOM_USART_CTRLB_CHSIZE_Msk & ((value) << SERCOM_USART_CTRLB_CHSIZE_Pos)) 442 #define SERCOM_USART_CTRLB_SBMODE_Pos 6 /**< \brief (SERCOM_USART_CTRLB) Stop Bit Mode */ 443 #define SERCOM_USART_CTRLB_SBMODE (_U_(0x1) << SERCOM_USART_CTRLB_SBMODE_Pos) 444 #define SERCOM_USART_CTRLB_SFDE_Pos 9 /**< \brief (SERCOM_USART_CTRLB) Start of Frame Detection Enable */ 445 #define SERCOM_USART_CTRLB_SFDE (_U_(0x1) << SERCOM_USART_CTRLB_SFDE_Pos) 446 #define SERCOM_USART_CTRLB_PMODE_Pos 13 /**< \brief (SERCOM_USART_CTRLB) Parity Mode */ 447 #define SERCOM_USART_CTRLB_PMODE (_U_(0x1) << SERCOM_USART_CTRLB_PMODE_Pos) 448 #define SERCOM_USART_CTRLB_TXEN_Pos 16 /**< \brief (SERCOM_USART_CTRLB) Transmitter Enable */ 449 #define SERCOM_USART_CTRLB_TXEN (_U_(0x1) << SERCOM_USART_CTRLB_TXEN_Pos) 450 #define SERCOM_USART_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_USART_CTRLB) Receiver Enable */ 451 #define SERCOM_USART_CTRLB_RXEN (_U_(0x1) << SERCOM_USART_CTRLB_RXEN_Pos) 452 #define SERCOM_USART_CTRLB_MASK _U_(0x00032247) /**< \brief (SERCOM_USART_CTRLB) MASK Register */ 453 454 /* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x08) (R/W 8) I2CM I2CM Debug Control -------- */ 455 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 456 typedef union { 457 struct { 458 uint8_t DBGSTOP:1; /*!< bit: 0 Debug Stop Mode */ 459 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 460 } bit; /*!< Structure used for bit access */ 461 uint8_t reg; /*!< Type used for register access */ 462 } SERCOM_I2CM_DBGCTRL_Type; 463 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 464 465 #define SERCOM_I2CM_DBGCTRL_OFFSET 0x08 /**< \brief (SERCOM_I2CM_DBGCTRL offset) I2CM Debug Control */ 466 #define SERCOM_I2CM_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CM_DBGCTRL reset_value) I2CM Debug Control */ 467 468 #define SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_I2CM_DBGCTRL) Debug Stop Mode */ 469 #define SERCOM_I2CM_DBGCTRL_DBGSTOP (_U_(0x1) << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos) 470 #define SERCOM_I2CM_DBGCTRL_MASK _U_(0x01) /**< \brief (SERCOM_I2CM_DBGCTRL) MASK Register */ 471 472 /* -------- SERCOM_SPI_DBGCTRL : (SERCOM Offset: 0x08) (R/W 8) SPI SPI Debug Control -------- */ 473 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 474 typedef union { 475 struct { 476 uint8_t DBGSTOP:1; /*!< bit: 0 Debug Stop Mode */ 477 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 478 } bit; /*!< Structure used for bit access */ 479 uint8_t reg; /*!< Type used for register access */ 480 } SERCOM_SPI_DBGCTRL_Type; 481 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 482 483 #define SERCOM_SPI_DBGCTRL_OFFSET 0x08 /**< \brief (SERCOM_SPI_DBGCTRL offset) SPI Debug Control */ 484 #define SERCOM_SPI_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (SERCOM_SPI_DBGCTRL reset_value) SPI Debug Control */ 485 486 #define SERCOM_SPI_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_SPI_DBGCTRL) Debug Stop Mode */ 487 #define SERCOM_SPI_DBGCTRL_DBGSTOP (_U_(0x1) << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos) 488 #define SERCOM_SPI_DBGCTRL_MASK _U_(0x01) /**< \brief (SERCOM_SPI_DBGCTRL) MASK Register */ 489 490 /* -------- SERCOM_USART_DBGCTRL : (SERCOM Offset: 0x08) (R/W 8) USART USART Debug Control -------- */ 491 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 492 typedef union { 493 struct { 494 uint8_t DBGSTOP:1; /*!< bit: 0 Debug Stop Mode */ 495 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 496 } bit; /*!< Structure used for bit access */ 497 uint8_t reg; /*!< Type used for register access */ 498 } SERCOM_USART_DBGCTRL_Type; 499 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 500 501 #define SERCOM_USART_DBGCTRL_OFFSET 0x08 /**< \brief (SERCOM_USART_DBGCTRL offset) USART Debug Control */ 502 #define SERCOM_USART_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (SERCOM_USART_DBGCTRL reset_value) USART Debug Control */ 503 504 #define SERCOM_USART_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_USART_DBGCTRL) Debug Stop Mode */ 505 #define SERCOM_USART_DBGCTRL_DBGSTOP (_U_(0x1) << SERCOM_USART_DBGCTRL_DBGSTOP_Pos) 506 #define SERCOM_USART_DBGCTRL_MASK _U_(0x01) /**< \brief (SERCOM_USART_DBGCTRL) MASK Register */ 507 508 /* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0A) (R/W 16) I2CM I2CM Baud Rate -------- */ 509 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 510 typedef union { 511 struct { 512 uint16_t BAUD:8; /*!< bit: 0.. 7 Master Baud Rate */ 513 uint16_t BAUDLOW:8; /*!< bit: 8..15 Master Baud Rate Low */ 514 } bit; /*!< Structure used for bit access */ 515 uint16_t reg; /*!< Type used for register access */ 516 } SERCOM_I2CM_BAUD_Type; 517 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 518 519 #define SERCOM_I2CM_BAUD_OFFSET 0x0A /**< \brief (SERCOM_I2CM_BAUD offset) I2CM Baud Rate */ 520 #define SERCOM_I2CM_BAUD_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_I2CM_BAUD reset_value) I2CM Baud Rate */ 521 522 #define SERCOM_I2CM_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_I2CM_BAUD) Master Baud Rate */ 523 #define SERCOM_I2CM_BAUD_BAUD_Msk (_U_(0xFF) << SERCOM_I2CM_BAUD_BAUD_Pos) 524 #define SERCOM_I2CM_BAUD_BAUD(value) (SERCOM_I2CM_BAUD_BAUD_Msk & ((value) << SERCOM_I2CM_BAUD_BAUD_Pos)) 525 #define SERCOM_I2CM_BAUD_BAUDLOW_Pos 8 /**< \brief (SERCOM_I2CM_BAUD) Master Baud Rate Low */ 526 #define SERCOM_I2CM_BAUD_BAUDLOW_Msk (_U_(0xFF) << SERCOM_I2CM_BAUD_BAUDLOW_Pos) 527 #define SERCOM_I2CM_BAUD_BAUDLOW(value) (SERCOM_I2CM_BAUD_BAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_BAUDLOW_Pos)) 528 #define SERCOM_I2CM_BAUD_MASK _U_(0xFFFF) /**< \brief (SERCOM_I2CM_BAUD) MASK Register */ 529 530 /* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0A) (R/W 8) SPI SPI Baud Rate -------- */ 531 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 532 typedef union { 533 struct { 534 uint8_t BAUD:8; /*!< bit: 0.. 7 Baud Register */ 535 } bit; /*!< Structure used for bit access */ 536 uint8_t reg; /*!< Type used for register access */ 537 } SERCOM_SPI_BAUD_Type; 538 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 539 540 #define SERCOM_SPI_BAUD_OFFSET 0x0A /**< \brief (SERCOM_SPI_BAUD offset) SPI Baud Rate */ 541 #define SERCOM_SPI_BAUD_RESETVALUE _U_(0x00) /**< \brief (SERCOM_SPI_BAUD reset_value) SPI Baud Rate */ 542 543 #define SERCOM_SPI_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_SPI_BAUD) Baud Register */ 544 #define SERCOM_SPI_BAUD_BAUD_Msk (_U_(0xFF) << SERCOM_SPI_BAUD_BAUD_Pos) 545 #define SERCOM_SPI_BAUD_BAUD(value) (SERCOM_SPI_BAUD_BAUD_Msk & ((value) << SERCOM_SPI_BAUD_BAUD_Pos)) 546 #define SERCOM_SPI_BAUD_MASK _U_(0xFF) /**< \brief (SERCOM_SPI_BAUD) MASK Register */ 547 548 /* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0A) (R/W 16) USART USART Baud -------- */ 549 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 550 typedef union { 551 struct { 552 uint16_t BAUD:16; /*!< bit: 0..15 Baud Value */ 553 } bit; /*!< Structure used for bit access */ 554 uint16_t reg; /*!< Type used for register access */ 555 } SERCOM_USART_BAUD_Type; 556 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 557 558 #define SERCOM_USART_BAUD_OFFSET 0x0A /**< \brief (SERCOM_USART_BAUD offset) USART Baud */ 559 #define SERCOM_USART_BAUD_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_USART_BAUD reset_value) USART Baud */ 560 561 #define SERCOM_USART_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD) Baud Value */ 562 #define SERCOM_USART_BAUD_BAUD_Msk (_U_(0xFFFF) << SERCOM_USART_BAUD_BAUD_Pos) 563 #define SERCOM_USART_BAUD_BAUD(value) (SERCOM_USART_BAUD_BAUD_Msk & ((value) << SERCOM_USART_BAUD_BAUD_Pos)) 564 #define SERCOM_USART_BAUD_MASK _U_(0xFFFF) /**< \brief (SERCOM_USART_BAUD) MASK Register */ 565 566 /* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x0C) (R/W 8) I2CM I2CM Interrupt Enable Clear -------- */ 567 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 568 typedef union { 569 struct { 570 uint8_t MB:1; /*!< bit: 0 Master on Bus Interrupt Enable */ 571 uint8_t SB:1; /*!< bit: 1 Slave on Bus Interrupt Enable */ 572 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 573 } bit; /*!< Structure used for bit access */ 574 uint8_t reg; /*!< Type used for register access */ 575 } SERCOM_I2CM_INTENCLR_Type; 576 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 577 578 #define SERCOM_I2CM_INTENCLR_OFFSET 0x0C /**< \brief (SERCOM_I2CM_INTENCLR offset) I2CM Interrupt Enable Clear */ 579 #define SERCOM_I2CM_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CM_INTENCLR reset_value) I2CM Interrupt Enable Clear */ 580 581 #define SERCOM_I2CM_INTENCLR_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENCLR) Master on Bus Interrupt Enable */ 582 #define SERCOM_I2CM_INTENCLR_MB (_U_(0x1) << SERCOM_I2CM_INTENCLR_MB_Pos) 583 #define SERCOM_I2CM_INTENCLR_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENCLR) Slave on Bus Interrupt Enable */ 584 #define SERCOM_I2CM_INTENCLR_SB (_U_(0x1) << SERCOM_I2CM_INTENCLR_SB_Pos) 585 #define SERCOM_I2CM_INTENCLR_MASK _U_(0x03) /**< \brief (SERCOM_I2CM_INTENCLR) MASK Register */ 586 587 /* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x0C) (R/W 8) I2CS I2CS Interrupt Enable Clear -------- */ 588 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 589 typedef union { 590 struct { 591 uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Enable */ 592 uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Enable */ 593 uint8_t DRDY:1; /*!< bit: 2 Data Ready Interrupt Enable */ 594 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 595 } bit; /*!< Structure used for bit access */ 596 uint8_t reg; /*!< Type used for register access */ 597 } SERCOM_I2CS_INTENCLR_Type; 598 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 599 600 #define SERCOM_I2CS_INTENCLR_OFFSET 0x0C /**< \brief (SERCOM_I2CS_INTENCLR offset) I2CS Interrupt Enable Clear */ 601 #define SERCOM_I2CS_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CS_INTENCLR reset_value) I2CS Interrupt Enable Clear */ 602 603 #define SERCOM_I2CS_INTENCLR_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENCLR) Stop Received Interrupt Enable */ 604 #define SERCOM_I2CS_INTENCLR_PREC (_U_(0x1) << SERCOM_I2CS_INTENCLR_PREC_Pos) 605 #define SERCOM_I2CS_INTENCLR_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENCLR) Address Match Interrupt Enable */ 606 #define SERCOM_I2CS_INTENCLR_AMATCH (_U_(0x1) << SERCOM_I2CS_INTENCLR_AMATCH_Pos) 607 #define SERCOM_I2CS_INTENCLR_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENCLR) Data Ready Interrupt Enable */ 608 #define SERCOM_I2CS_INTENCLR_DRDY (_U_(0x1) << SERCOM_I2CS_INTENCLR_DRDY_Pos) 609 #define SERCOM_I2CS_INTENCLR_MASK _U_(0x07) /**< \brief (SERCOM_I2CS_INTENCLR) MASK Register */ 610 611 /* -------- SERCOM_SPI_INTENCLR : (SERCOM Offset: 0x0C) (R/W 8) SPI SPI Interrupt Enable Clear -------- */ 612 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 613 typedef union { 614 struct { 615 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */ 616 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */ 617 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */ 618 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 619 } bit; /*!< Structure used for bit access */ 620 uint8_t reg; /*!< Type used for register access */ 621 } SERCOM_SPI_INTENCLR_Type; 622 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 623 624 #define SERCOM_SPI_INTENCLR_OFFSET 0x0C /**< \brief (SERCOM_SPI_INTENCLR offset) SPI Interrupt Enable Clear */ 625 #define SERCOM_SPI_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (SERCOM_SPI_INTENCLR reset_value) SPI Interrupt Enable Clear */ 626 627 #define SERCOM_SPI_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENCLR) Data Register Empty Interrupt Enable */ 628 #define SERCOM_SPI_INTENCLR_DRE (_U_(0x1) << SERCOM_SPI_INTENCLR_DRE_Pos) 629 #define SERCOM_SPI_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENCLR) Transmit Complete Interrupt Enable */ 630 #define SERCOM_SPI_INTENCLR_TXC (_U_(0x1) << SERCOM_SPI_INTENCLR_TXC_Pos) 631 #define SERCOM_SPI_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENCLR) Receive Complete Interrupt Enable */ 632 #define SERCOM_SPI_INTENCLR_RXC (_U_(0x1) << SERCOM_SPI_INTENCLR_RXC_Pos) 633 #define SERCOM_SPI_INTENCLR_MASK _U_(0x07) /**< \brief (SERCOM_SPI_INTENCLR) MASK Register */ 634 635 /* -------- SERCOM_USART_INTENCLR : (SERCOM Offset: 0x0C) (R/W 8) USART USART Interrupt Enable Clear -------- */ 636 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 637 typedef union { 638 struct { 639 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */ 640 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */ 641 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */ 642 uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Disable */ 643 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 644 } bit; /*!< Structure used for bit access */ 645 uint8_t reg; /*!< Type used for register access */ 646 } SERCOM_USART_INTENCLR_Type; 647 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 648 649 #define SERCOM_USART_INTENCLR_OFFSET 0x0C /**< \brief (SERCOM_USART_INTENCLR offset) USART Interrupt Enable Clear */ 650 #define SERCOM_USART_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (SERCOM_USART_INTENCLR reset_value) USART Interrupt Enable Clear */ 651 652 #define SERCOM_USART_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENCLR) Data Register Empty Interrupt Enable */ 653 #define SERCOM_USART_INTENCLR_DRE (_U_(0x1) << SERCOM_USART_INTENCLR_DRE_Pos) 654 #define SERCOM_USART_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENCLR) Transmit Complete Interrupt Enable */ 655 #define SERCOM_USART_INTENCLR_TXC (_U_(0x1) << SERCOM_USART_INTENCLR_TXC_Pos) 656 #define SERCOM_USART_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENCLR) Receive Complete Interrupt Enable */ 657 #define SERCOM_USART_INTENCLR_RXC (_U_(0x1) << SERCOM_USART_INTENCLR_RXC_Pos) 658 #define SERCOM_USART_INTENCLR_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENCLR) Receive Start Interrupt Disable */ 659 #define SERCOM_USART_INTENCLR_RXS (_U_(0x1) << SERCOM_USART_INTENCLR_RXS_Pos) 660 #define SERCOM_USART_INTENCLR_MASK _U_(0x0F) /**< \brief (SERCOM_USART_INTENCLR) MASK Register */ 661 662 /* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x0D) (R/W 8) I2CM I2CM Interrupt Enable Set -------- */ 663 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 664 typedef union { 665 struct { 666 uint8_t MB:1; /*!< bit: 0 Master on Bus Interrupt Enable */ 667 uint8_t SB:1; /*!< bit: 1 Slave on Bus Interrupt Enable */ 668 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 669 } bit; /*!< Structure used for bit access */ 670 uint8_t reg; /*!< Type used for register access */ 671 } SERCOM_I2CM_INTENSET_Type; 672 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 673 674 #define SERCOM_I2CM_INTENSET_OFFSET 0x0D /**< \brief (SERCOM_I2CM_INTENSET offset) I2CM Interrupt Enable Set */ 675 #define SERCOM_I2CM_INTENSET_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CM_INTENSET reset_value) I2CM Interrupt Enable Set */ 676 677 #define SERCOM_I2CM_INTENSET_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENSET) Master on Bus Interrupt Enable */ 678 #define SERCOM_I2CM_INTENSET_MB (_U_(0x1) << SERCOM_I2CM_INTENSET_MB_Pos) 679 #define SERCOM_I2CM_INTENSET_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENSET) Slave on Bus Interrupt Enable */ 680 #define SERCOM_I2CM_INTENSET_SB (_U_(0x1) << SERCOM_I2CM_INTENSET_SB_Pos) 681 #define SERCOM_I2CM_INTENSET_MASK _U_(0x03) /**< \brief (SERCOM_I2CM_INTENSET) MASK Register */ 682 683 /* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x0D) (R/W 8) I2CS I2CS Interrupt Enable Set -------- */ 684 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 685 typedef union { 686 struct { 687 uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Enable */ 688 uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Enable */ 689 uint8_t DRDY:1; /*!< bit: 2 Data Ready Interrupt Enable */ 690 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 691 } bit; /*!< Structure used for bit access */ 692 uint8_t reg; /*!< Type used for register access */ 693 } SERCOM_I2CS_INTENSET_Type; 694 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 695 696 #define SERCOM_I2CS_INTENSET_OFFSET 0x0D /**< \brief (SERCOM_I2CS_INTENSET offset) I2CS Interrupt Enable Set */ 697 #define SERCOM_I2CS_INTENSET_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CS_INTENSET reset_value) I2CS Interrupt Enable Set */ 698 699 #define SERCOM_I2CS_INTENSET_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENSET) Stop Received Interrupt Enable */ 700 #define SERCOM_I2CS_INTENSET_PREC (_U_(0x1) << SERCOM_I2CS_INTENSET_PREC_Pos) 701 #define SERCOM_I2CS_INTENSET_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENSET) Address Match Interrupt Enable */ 702 #define SERCOM_I2CS_INTENSET_AMATCH (_U_(0x1) << SERCOM_I2CS_INTENSET_AMATCH_Pos) 703 #define SERCOM_I2CS_INTENSET_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENSET) Data Ready Interrupt Enable */ 704 #define SERCOM_I2CS_INTENSET_DRDY (_U_(0x1) << SERCOM_I2CS_INTENSET_DRDY_Pos) 705 #define SERCOM_I2CS_INTENSET_MASK _U_(0x07) /**< \brief (SERCOM_I2CS_INTENSET) MASK Register */ 706 707 /* -------- SERCOM_SPI_INTENSET : (SERCOM Offset: 0x0D) (R/W 8) SPI SPI Interrupt Enable Set -------- */ 708 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 709 typedef union { 710 struct { 711 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */ 712 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */ 713 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */ 714 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 715 } bit; /*!< Structure used for bit access */ 716 uint8_t reg; /*!< Type used for register access */ 717 } SERCOM_SPI_INTENSET_Type; 718 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 719 720 #define SERCOM_SPI_INTENSET_OFFSET 0x0D /**< \brief (SERCOM_SPI_INTENSET offset) SPI Interrupt Enable Set */ 721 #define SERCOM_SPI_INTENSET_RESETVALUE _U_(0x00) /**< \brief (SERCOM_SPI_INTENSET reset_value) SPI Interrupt Enable Set */ 722 723 #define SERCOM_SPI_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENSET) Data Register Empty Interrupt Enable */ 724 #define SERCOM_SPI_INTENSET_DRE (_U_(0x1) << SERCOM_SPI_INTENSET_DRE_Pos) 725 #define SERCOM_SPI_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENSET) Transmit Complete Interrupt Enable */ 726 #define SERCOM_SPI_INTENSET_TXC (_U_(0x1) << SERCOM_SPI_INTENSET_TXC_Pos) 727 #define SERCOM_SPI_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENSET) Receive Complete Interrupt Enable */ 728 #define SERCOM_SPI_INTENSET_RXC (_U_(0x1) << SERCOM_SPI_INTENSET_RXC_Pos) 729 #define SERCOM_SPI_INTENSET_MASK _U_(0x07) /**< \brief (SERCOM_SPI_INTENSET) MASK Register */ 730 731 /* -------- SERCOM_USART_INTENSET : (SERCOM Offset: 0x0D) (R/W 8) USART USART Interrupt Enable Set -------- */ 732 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 733 typedef union { 734 struct { 735 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */ 736 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */ 737 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */ 738 uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Enable */ 739 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 740 } bit; /*!< Structure used for bit access */ 741 uint8_t reg; /*!< Type used for register access */ 742 } SERCOM_USART_INTENSET_Type; 743 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 744 745 #define SERCOM_USART_INTENSET_OFFSET 0x0D /**< \brief (SERCOM_USART_INTENSET offset) USART Interrupt Enable Set */ 746 #define SERCOM_USART_INTENSET_RESETVALUE _U_(0x00) /**< \brief (SERCOM_USART_INTENSET reset_value) USART Interrupt Enable Set */ 747 748 #define SERCOM_USART_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENSET) Data Register Empty Interrupt Enable */ 749 #define SERCOM_USART_INTENSET_DRE (_U_(0x1) << SERCOM_USART_INTENSET_DRE_Pos) 750 #define SERCOM_USART_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENSET) Transmit Complete Interrupt Enable */ 751 #define SERCOM_USART_INTENSET_TXC (_U_(0x1) << SERCOM_USART_INTENSET_TXC_Pos) 752 #define SERCOM_USART_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENSET) Receive Complete Interrupt Enable */ 753 #define SERCOM_USART_INTENSET_RXC (_U_(0x1) << SERCOM_USART_INTENSET_RXC_Pos) 754 #define SERCOM_USART_INTENSET_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENSET) Receive Start Interrupt Enable */ 755 #define SERCOM_USART_INTENSET_RXS (_U_(0x1) << SERCOM_USART_INTENSET_RXS_Pos) 756 #define SERCOM_USART_INTENSET_MASK _U_(0x0F) /**< \brief (SERCOM_USART_INTENSET) MASK Register */ 757 758 /* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x0E) (R/W 8) I2CM I2CM Interrupt Flag Status and Clear -------- */ 759 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 760 typedef union { // __I to avoid read-modify-write on write-to-clear register 761 struct { 762 __I uint8_t MB:1; /*!< bit: 0 Master on Bus */ 763 __I uint8_t SB:1; /*!< bit: 1 Slave on Bus */ 764 __I uint8_t :6; /*!< bit: 2.. 7 Reserved */ 765 } bit; /*!< Structure used for bit access */ 766 uint8_t reg; /*!< Type used for register access */ 767 } SERCOM_I2CM_INTFLAG_Type; 768 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 769 770 #define SERCOM_I2CM_INTFLAG_OFFSET 0x0E /**< \brief (SERCOM_I2CM_INTFLAG offset) I2CM Interrupt Flag Status and Clear */ 771 #define SERCOM_I2CM_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CM_INTFLAG reset_value) I2CM Interrupt Flag Status and Clear */ 772 773 #define SERCOM_I2CM_INTFLAG_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTFLAG) Master on Bus */ 774 #define SERCOM_I2CM_INTFLAG_MB (_U_(0x1) << SERCOM_I2CM_INTFLAG_MB_Pos) 775 #define SERCOM_I2CM_INTFLAG_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTFLAG) Slave on Bus */ 776 #define SERCOM_I2CM_INTFLAG_SB (_U_(0x1) << SERCOM_I2CM_INTFLAG_SB_Pos) 777 #define SERCOM_I2CM_INTFLAG_MASK _U_(0x03) /**< \brief (SERCOM_I2CM_INTFLAG) MASK Register */ 778 779 /* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x0E) (R/W 8) I2CS I2CS Interrupt Flag Status and Clear -------- */ 780 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 781 typedef union { // __I to avoid read-modify-write on write-to-clear register 782 struct { 783 __I uint8_t PREC:1; /*!< bit: 0 Stop Received */ 784 __I uint8_t AMATCH:1; /*!< bit: 1 Address Match */ 785 __I uint8_t DRDY:1; /*!< bit: 2 Data Ready */ 786 __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ 787 } bit; /*!< Structure used for bit access */ 788 uint8_t reg; /*!< Type used for register access */ 789 } SERCOM_I2CS_INTFLAG_Type; 790 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 791 792 #define SERCOM_I2CS_INTFLAG_OFFSET 0x0E /**< \brief (SERCOM_I2CS_INTFLAG offset) I2CS Interrupt Flag Status and Clear */ 793 #define SERCOM_I2CS_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CS_INTFLAG reset_value) I2CS Interrupt Flag Status and Clear */ 794 795 #define SERCOM_I2CS_INTFLAG_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTFLAG) Stop Received */ 796 #define SERCOM_I2CS_INTFLAG_PREC (_U_(0x1) << SERCOM_I2CS_INTFLAG_PREC_Pos) 797 #define SERCOM_I2CS_INTFLAG_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTFLAG) Address Match */ 798 #define SERCOM_I2CS_INTFLAG_AMATCH (_U_(0x1) << SERCOM_I2CS_INTFLAG_AMATCH_Pos) 799 #define SERCOM_I2CS_INTFLAG_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTFLAG) Data Ready */ 800 #define SERCOM_I2CS_INTFLAG_DRDY (_U_(0x1) << SERCOM_I2CS_INTFLAG_DRDY_Pos) 801 #define SERCOM_I2CS_INTFLAG_MASK _U_(0x07) /**< \brief (SERCOM_I2CS_INTFLAG) MASK Register */ 802 803 /* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x0E) (R/W 8) SPI SPI Interrupt Flag Status and Clear -------- */ 804 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 805 typedef union { // __I to avoid read-modify-write on write-to-clear register 806 struct { 807 __I uint8_t DRE:1; /*!< bit: 0 Data Register Empty */ 808 __I uint8_t TXC:1; /*!< bit: 1 Transmit Complete */ 809 __I uint8_t RXC:1; /*!< bit: 2 Receive Complete */ 810 __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ 811 } bit; /*!< Structure used for bit access */ 812 uint8_t reg; /*!< Type used for register access */ 813 } SERCOM_SPI_INTFLAG_Type; 814 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 815 816 #define SERCOM_SPI_INTFLAG_OFFSET 0x0E /**< \brief (SERCOM_SPI_INTFLAG offset) SPI Interrupt Flag Status and Clear */ 817 #define SERCOM_SPI_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (SERCOM_SPI_INTFLAG reset_value) SPI Interrupt Flag Status and Clear */ 818 819 #define SERCOM_SPI_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTFLAG) Data Register Empty */ 820 #define SERCOM_SPI_INTFLAG_DRE (_U_(0x1) << SERCOM_SPI_INTFLAG_DRE_Pos) 821 #define SERCOM_SPI_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTFLAG) Transmit Complete */ 822 #define SERCOM_SPI_INTFLAG_TXC (_U_(0x1) << SERCOM_SPI_INTFLAG_TXC_Pos) 823 #define SERCOM_SPI_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTFLAG) Receive Complete */ 824 #define SERCOM_SPI_INTFLAG_RXC (_U_(0x1) << SERCOM_SPI_INTFLAG_RXC_Pos) 825 #define SERCOM_SPI_INTFLAG_MASK _U_(0x07) /**< \brief (SERCOM_SPI_INTFLAG) MASK Register */ 826 827 /* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x0E) (R/W 8) USART USART Interrupt Flag Status and Clear -------- */ 828 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 829 typedef union { // __I to avoid read-modify-write on write-to-clear register 830 struct { 831 __I uint8_t DRE:1; /*!< bit: 0 Data Register Empty */ 832 __I uint8_t TXC:1; /*!< bit: 1 Transmit Complete */ 833 __I uint8_t RXC:1; /*!< bit: 2 Receive Complete */ 834 __I uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */ 835 __I uint8_t :4; /*!< bit: 4.. 7 Reserved */ 836 } bit; /*!< Structure used for bit access */ 837 uint8_t reg; /*!< Type used for register access */ 838 } SERCOM_USART_INTFLAG_Type; 839 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 840 841 #define SERCOM_USART_INTFLAG_OFFSET 0x0E /**< \brief (SERCOM_USART_INTFLAG offset) USART Interrupt Flag Status and Clear */ 842 #define SERCOM_USART_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (SERCOM_USART_INTFLAG reset_value) USART Interrupt Flag Status and Clear */ 843 844 #define SERCOM_USART_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_USART_INTFLAG) Data Register Empty */ 845 #define SERCOM_USART_INTFLAG_DRE (_U_(0x1) << SERCOM_USART_INTFLAG_DRE_Pos) 846 #define SERCOM_USART_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_USART_INTFLAG) Transmit Complete */ 847 #define SERCOM_USART_INTFLAG_TXC (_U_(0x1) << SERCOM_USART_INTFLAG_TXC_Pos) 848 #define SERCOM_USART_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_USART_INTFLAG) Receive Complete */ 849 #define SERCOM_USART_INTFLAG_RXC (_U_(0x1) << SERCOM_USART_INTFLAG_RXC_Pos) 850 #define SERCOM_USART_INTFLAG_RXS_Pos 3 /**< \brief (SERCOM_USART_INTFLAG) Receive Start Interrupt */ 851 #define SERCOM_USART_INTFLAG_RXS (_U_(0x1) << SERCOM_USART_INTFLAG_RXS_Pos) 852 #define SERCOM_USART_INTFLAG_MASK _U_(0x0F) /**< \brief (SERCOM_USART_INTFLAG) MASK Register */ 853 854 /* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x10) (R/W 16) I2CM I2CM Status -------- */ 855 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 856 typedef union { 857 struct { 858 uint16_t BUSERR:1; /*!< bit: 0 Bus Error */ 859 uint16_t ARBLOST:1; /*!< bit: 1 Arbitration Lost */ 860 uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */ 861 uint16_t :1; /*!< bit: 3 Reserved */ 862 uint16_t BUSSTATE:2; /*!< bit: 4.. 5 Bus State */ 863 uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Time-out */ 864 uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */ 865 uint16_t :7; /*!< bit: 8..14 Reserved */ 866 uint16_t SYNCBUSY:1; /*!< bit: 15 Synchronization Busy */ 867 } bit; /*!< Structure used for bit access */ 868 uint16_t reg; /*!< Type used for register access */ 869 } SERCOM_I2CM_STATUS_Type; 870 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 871 872 #define SERCOM_I2CM_STATUS_OFFSET 0x10 /**< \brief (SERCOM_I2CM_STATUS offset) I2CM Status */ 873 #define SERCOM_I2CM_STATUS_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_I2CM_STATUS reset_value) I2CM Status */ 874 875 #define SERCOM_I2CM_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CM_STATUS) Bus Error */ 876 #define SERCOM_I2CM_STATUS_BUSERR (_U_(0x1) << SERCOM_I2CM_STATUS_BUSERR_Pos) 877 #define SERCOM_I2CM_STATUS_ARBLOST_Pos 1 /**< \brief (SERCOM_I2CM_STATUS) Arbitration Lost */ 878 #define SERCOM_I2CM_STATUS_ARBLOST (_U_(0x1) << SERCOM_I2CM_STATUS_ARBLOST_Pos) 879 #define SERCOM_I2CM_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CM_STATUS) Received Not Acknowledge */ 880 #define SERCOM_I2CM_STATUS_RXNACK (_U_(0x1) << SERCOM_I2CM_STATUS_RXNACK_Pos) 881 #define SERCOM_I2CM_STATUS_BUSSTATE_Pos 4 /**< \brief (SERCOM_I2CM_STATUS) Bus State */ 882 #define SERCOM_I2CM_STATUS_BUSSTATE_Msk (_U_(0x3) << SERCOM_I2CM_STATUS_BUSSTATE_Pos) 883 #define SERCOM_I2CM_STATUS_BUSSTATE(value) (SERCOM_I2CM_STATUS_BUSSTATE_Msk & ((value) << SERCOM_I2CM_STATUS_BUSSTATE_Pos)) 884 #define SERCOM_I2CM_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CM_STATUS) SCL Low Time-out */ 885 #define SERCOM_I2CM_STATUS_LOWTOUT (_U_(0x1) << SERCOM_I2CM_STATUS_LOWTOUT_Pos) 886 #define SERCOM_I2CM_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CM_STATUS) Clock Hold */ 887 #define SERCOM_I2CM_STATUS_CLKHOLD (_U_(0x1) << SERCOM_I2CM_STATUS_CLKHOLD_Pos) 888 #define SERCOM_I2CM_STATUS_SYNCBUSY_Pos 15 /**< \brief (SERCOM_I2CM_STATUS) Synchronization Busy */ 889 #define SERCOM_I2CM_STATUS_SYNCBUSY (_U_(0x1) << SERCOM_I2CM_STATUS_SYNCBUSY_Pos) 890 #define SERCOM_I2CM_STATUS_MASK _U_(0x80F7) /**< \brief (SERCOM_I2CM_STATUS) MASK Register */ 891 892 /* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x10) (R/W 16) I2CS I2CS Status -------- */ 893 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 894 typedef union { 895 struct { 896 uint16_t BUSERR:1; /*!< bit: 0 Bus Error */ 897 uint16_t COLL:1; /*!< bit: 1 Transmit Collision */ 898 uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */ 899 uint16_t DIR:1; /*!< bit: 3 Read / Write Direction */ 900 uint16_t SR:1; /*!< bit: 4 Repeated Start */ 901 uint16_t :1; /*!< bit: 5 Reserved */ 902 uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Time-out */ 903 uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */ 904 uint16_t :7; /*!< bit: 8..14 Reserved */ 905 uint16_t SYNCBUSY:1; /*!< bit: 15 Synchronization Busy */ 906 } bit; /*!< Structure used for bit access */ 907 uint16_t reg; /*!< Type used for register access */ 908 } SERCOM_I2CS_STATUS_Type; 909 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 910 911 #define SERCOM_I2CS_STATUS_OFFSET 0x10 /**< \brief (SERCOM_I2CS_STATUS offset) I2CS Status */ 912 #define SERCOM_I2CS_STATUS_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_I2CS_STATUS reset_value) I2CS Status */ 913 914 #define SERCOM_I2CS_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CS_STATUS) Bus Error */ 915 #define SERCOM_I2CS_STATUS_BUSERR (_U_(0x1) << SERCOM_I2CS_STATUS_BUSERR_Pos) 916 #define SERCOM_I2CS_STATUS_COLL_Pos 1 /**< \brief (SERCOM_I2CS_STATUS) Transmit Collision */ 917 #define SERCOM_I2CS_STATUS_COLL (_U_(0x1) << SERCOM_I2CS_STATUS_COLL_Pos) 918 #define SERCOM_I2CS_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CS_STATUS) Received Not Acknowledge */ 919 #define SERCOM_I2CS_STATUS_RXNACK (_U_(0x1) << SERCOM_I2CS_STATUS_RXNACK_Pos) 920 #define SERCOM_I2CS_STATUS_DIR_Pos 3 /**< \brief (SERCOM_I2CS_STATUS) Read / Write Direction */ 921 #define SERCOM_I2CS_STATUS_DIR (_U_(0x1) << SERCOM_I2CS_STATUS_DIR_Pos) 922 #define SERCOM_I2CS_STATUS_SR_Pos 4 /**< \brief (SERCOM_I2CS_STATUS) Repeated Start */ 923 #define SERCOM_I2CS_STATUS_SR (_U_(0x1) << SERCOM_I2CS_STATUS_SR_Pos) 924 #define SERCOM_I2CS_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CS_STATUS) SCL Low Time-out */ 925 #define SERCOM_I2CS_STATUS_LOWTOUT (_U_(0x1) << SERCOM_I2CS_STATUS_LOWTOUT_Pos) 926 #define SERCOM_I2CS_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CS_STATUS) Clock Hold */ 927 #define SERCOM_I2CS_STATUS_CLKHOLD (_U_(0x1) << SERCOM_I2CS_STATUS_CLKHOLD_Pos) 928 #define SERCOM_I2CS_STATUS_SYNCBUSY_Pos 15 /**< \brief (SERCOM_I2CS_STATUS) Synchronization Busy */ 929 #define SERCOM_I2CS_STATUS_SYNCBUSY (_U_(0x1) << SERCOM_I2CS_STATUS_SYNCBUSY_Pos) 930 #define SERCOM_I2CS_STATUS_MASK _U_(0x80DF) /**< \brief (SERCOM_I2CS_STATUS) MASK Register */ 931 932 /* -------- SERCOM_SPI_STATUS : (SERCOM Offset: 0x10) (R/W 16) SPI SPI Status -------- */ 933 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 934 typedef union { 935 struct { 936 uint16_t :2; /*!< bit: 0.. 1 Reserved */ 937 uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */ 938 uint16_t :12; /*!< bit: 3..14 Reserved */ 939 uint16_t SYNCBUSY:1; /*!< bit: 15 Synchronization Busy */ 940 } bit; /*!< Structure used for bit access */ 941 uint16_t reg; /*!< Type used for register access */ 942 } SERCOM_SPI_STATUS_Type; 943 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 944 945 #define SERCOM_SPI_STATUS_OFFSET 0x10 /**< \brief (SERCOM_SPI_STATUS offset) SPI Status */ 946 #define SERCOM_SPI_STATUS_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_SPI_STATUS reset_value) SPI Status */ 947 948 #define SERCOM_SPI_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_SPI_STATUS) Buffer Overflow */ 949 #define SERCOM_SPI_STATUS_BUFOVF (_U_(0x1) << SERCOM_SPI_STATUS_BUFOVF_Pos) 950 #define SERCOM_SPI_STATUS_SYNCBUSY_Pos 15 /**< \brief (SERCOM_SPI_STATUS) Synchronization Busy */ 951 #define SERCOM_SPI_STATUS_SYNCBUSY (_U_(0x1) << SERCOM_SPI_STATUS_SYNCBUSY_Pos) 952 #define SERCOM_SPI_STATUS_MASK _U_(0x8004) /**< \brief (SERCOM_SPI_STATUS) MASK Register */ 953 954 /* -------- SERCOM_USART_STATUS : (SERCOM Offset: 0x10) (R/W 16) USART USART Status -------- */ 955 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 956 typedef union { 957 struct { 958 uint16_t PERR:1; /*!< bit: 0 Parity Error */ 959 uint16_t FERR:1; /*!< bit: 1 Frame Error */ 960 uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */ 961 uint16_t :12; /*!< bit: 3..14 Reserved */ 962 uint16_t SYNCBUSY:1; /*!< bit: 15 Synchronization Busy */ 963 } bit; /*!< Structure used for bit access */ 964 uint16_t reg; /*!< Type used for register access */ 965 } SERCOM_USART_STATUS_Type; 966 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 967 968 #define SERCOM_USART_STATUS_OFFSET 0x10 /**< \brief (SERCOM_USART_STATUS offset) USART Status */ 969 #define SERCOM_USART_STATUS_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_USART_STATUS reset_value) USART Status */ 970 971 #define SERCOM_USART_STATUS_PERR_Pos 0 /**< \brief (SERCOM_USART_STATUS) Parity Error */ 972 #define SERCOM_USART_STATUS_PERR (_U_(0x1) << SERCOM_USART_STATUS_PERR_Pos) 973 #define SERCOM_USART_STATUS_FERR_Pos 1 /**< \brief (SERCOM_USART_STATUS) Frame Error */ 974 #define SERCOM_USART_STATUS_FERR (_U_(0x1) << SERCOM_USART_STATUS_FERR_Pos) 975 #define SERCOM_USART_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_USART_STATUS) Buffer Overflow */ 976 #define SERCOM_USART_STATUS_BUFOVF (_U_(0x1) << SERCOM_USART_STATUS_BUFOVF_Pos) 977 #define SERCOM_USART_STATUS_SYNCBUSY_Pos 15 /**< \brief (SERCOM_USART_STATUS) Synchronization Busy */ 978 #define SERCOM_USART_STATUS_SYNCBUSY (_U_(0x1) << SERCOM_USART_STATUS_SYNCBUSY_Pos) 979 #define SERCOM_USART_STATUS_MASK _U_(0x8007) /**< \brief (SERCOM_USART_STATUS) MASK Register */ 980 981 /* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x14) (R/W 8) I2CM I2CM Address -------- */ 982 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 983 typedef union { 984 struct { 985 uint8_t ADDR:8; /*!< bit: 0.. 7 Address */ 986 } bit; /*!< Structure used for bit access */ 987 uint8_t reg; /*!< Type used for register access */ 988 } SERCOM_I2CM_ADDR_Type; 989 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 990 991 #define SERCOM_I2CM_ADDR_OFFSET 0x14 /**< \brief (SERCOM_I2CM_ADDR offset) I2CM Address */ 992 #define SERCOM_I2CM_ADDR_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CM_ADDR reset_value) I2CM Address */ 993 994 #define SERCOM_I2CM_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_I2CM_ADDR) Address */ 995 #define SERCOM_I2CM_ADDR_ADDR_Msk (_U_(0xFF) << SERCOM_I2CM_ADDR_ADDR_Pos) 996 #define SERCOM_I2CM_ADDR_ADDR(value) (SERCOM_I2CM_ADDR_ADDR_Msk & ((value) << SERCOM_I2CM_ADDR_ADDR_Pos)) 997 #define SERCOM_I2CM_ADDR_MASK _U_(0xFF) /**< \brief (SERCOM_I2CM_ADDR) MASK Register */ 998 999 /* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x14) (R/W 32) I2CS I2CS Address -------- */ 1000 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1001 typedef union { 1002 struct { 1003 uint32_t GENCEN:1; /*!< bit: 0 General Call Address Enable */ 1004 uint32_t ADDR:7; /*!< bit: 1.. 7 Address */ 1005 uint32_t :9; /*!< bit: 8..16 Reserved */ 1006 uint32_t ADDRMASK:7; /*!< bit: 17..23 Address Mask */ 1007 uint32_t :8; /*!< bit: 24..31 Reserved */ 1008 } bit; /*!< Structure used for bit access */ 1009 uint32_t reg; /*!< Type used for register access */ 1010 } SERCOM_I2CS_ADDR_Type; 1011 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1012 1013 #define SERCOM_I2CS_ADDR_OFFSET 0x14 /**< \brief (SERCOM_I2CS_ADDR offset) I2CS Address */ 1014 #define SERCOM_I2CS_ADDR_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_ADDR reset_value) I2CS Address */ 1015 1016 #define SERCOM_I2CS_ADDR_GENCEN_Pos 0 /**< \brief (SERCOM_I2CS_ADDR) General Call Address Enable */ 1017 #define SERCOM_I2CS_ADDR_GENCEN (_U_(0x1) << SERCOM_I2CS_ADDR_GENCEN_Pos) 1018 #define SERCOM_I2CS_ADDR_ADDR_Pos 1 /**< \brief (SERCOM_I2CS_ADDR) Address */ 1019 #define SERCOM_I2CS_ADDR_ADDR_Msk (_U_(0x7F) << SERCOM_I2CS_ADDR_ADDR_Pos) 1020 #define SERCOM_I2CS_ADDR_ADDR(value) (SERCOM_I2CS_ADDR_ADDR_Msk & ((value) << SERCOM_I2CS_ADDR_ADDR_Pos)) 1021 #define SERCOM_I2CS_ADDR_ADDRMASK_Pos 17 /**< \brief (SERCOM_I2CS_ADDR) Address Mask */ 1022 #define SERCOM_I2CS_ADDR_ADDRMASK_Msk (_U_(0x7F) << SERCOM_I2CS_ADDR_ADDRMASK_Pos) 1023 #define SERCOM_I2CS_ADDR_ADDRMASK(value) (SERCOM_I2CS_ADDR_ADDRMASK_Msk & ((value) << SERCOM_I2CS_ADDR_ADDRMASK_Pos)) 1024 #define SERCOM_I2CS_ADDR_MASK _U_(0x00FE00FF) /**< \brief (SERCOM_I2CS_ADDR) MASK Register */ 1025 1026 /* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x14) (R/W 32) SPI SPI Address -------- */ 1027 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1028 typedef union { 1029 struct { 1030 uint32_t ADDR:8; /*!< bit: 0.. 7 Address */ 1031 uint32_t :8; /*!< bit: 8..15 Reserved */ 1032 uint32_t ADDRMASK:8; /*!< bit: 16..23 Address Mask */ 1033 uint32_t :8; /*!< bit: 24..31 Reserved */ 1034 } bit; /*!< Structure used for bit access */ 1035 uint32_t reg; /*!< Type used for register access */ 1036 } SERCOM_SPI_ADDR_Type; 1037 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1038 1039 #define SERCOM_SPI_ADDR_OFFSET 0x14 /**< \brief (SERCOM_SPI_ADDR offset) SPI Address */ 1040 #define SERCOM_SPI_ADDR_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_ADDR reset_value) SPI Address */ 1041 1042 #define SERCOM_SPI_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_SPI_ADDR) Address */ 1043 #define SERCOM_SPI_ADDR_ADDR_Msk (_U_(0xFF) << SERCOM_SPI_ADDR_ADDR_Pos) 1044 #define SERCOM_SPI_ADDR_ADDR(value) (SERCOM_SPI_ADDR_ADDR_Msk & ((value) << SERCOM_SPI_ADDR_ADDR_Pos)) 1045 #define SERCOM_SPI_ADDR_ADDRMASK_Pos 16 /**< \brief (SERCOM_SPI_ADDR) Address Mask */ 1046 #define SERCOM_SPI_ADDR_ADDRMASK_Msk (_U_(0xFF) << SERCOM_SPI_ADDR_ADDRMASK_Pos) 1047 #define SERCOM_SPI_ADDR_ADDRMASK(value) (SERCOM_SPI_ADDR_ADDRMASK_Msk & ((value) << SERCOM_SPI_ADDR_ADDRMASK_Pos)) 1048 #define SERCOM_SPI_ADDR_MASK _U_(0x00FF00FF) /**< \brief (SERCOM_SPI_ADDR) MASK Register */ 1049 1050 /* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x18) (R/W 8) I2CM I2CM Data -------- */ 1051 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1052 typedef union { 1053 struct { 1054 uint8_t DATA:8; /*!< bit: 0.. 7 Data */ 1055 } bit; /*!< Structure used for bit access */ 1056 uint8_t reg; /*!< Type used for register access */ 1057 } SERCOM_I2CM_DATA_Type; 1058 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1059 1060 #define SERCOM_I2CM_DATA_OFFSET 0x18 /**< \brief (SERCOM_I2CM_DATA offset) I2CM Data */ 1061 #define SERCOM_I2CM_DATA_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CM_DATA reset_value) I2CM Data */ 1062 1063 #define SERCOM_I2CM_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CM_DATA) Data */ 1064 #define SERCOM_I2CM_DATA_DATA_Msk (_U_(0xFF) << SERCOM_I2CM_DATA_DATA_Pos) 1065 #define SERCOM_I2CM_DATA_DATA(value) (SERCOM_I2CM_DATA_DATA_Msk & ((value) << SERCOM_I2CM_DATA_DATA_Pos)) 1066 #define SERCOM_I2CM_DATA_MASK _U_(0xFF) /**< \brief (SERCOM_I2CM_DATA) MASK Register */ 1067 1068 /* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x18) (R/W 8) I2CS I2CS Data -------- */ 1069 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1070 typedef union { 1071 struct { 1072 uint8_t DATA:8; /*!< bit: 0.. 7 Data */ 1073 } bit; /*!< Structure used for bit access */ 1074 uint8_t reg; /*!< Type used for register access */ 1075 } SERCOM_I2CS_DATA_Type; 1076 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1077 1078 #define SERCOM_I2CS_DATA_OFFSET 0x18 /**< \brief (SERCOM_I2CS_DATA offset) I2CS Data */ 1079 #define SERCOM_I2CS_DATA_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CS_DATA reset_value) I2CS Data */ 1080 1081 #define SERCOM_I2CS_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CS_DATA) Data */ 1082 #define SERCOM_I2CS_DATA_DATA_Msk (_U_(0xFF) << SERCOM_I2CS_DATA_DATA_Pos) 1083 #define SERCOM_I2CS_DATA_DATA(value) (SERCOM_I2CS_DATA_DATA_Msk & ((value) << SERCOM_I2CS_DATA_DATA_Pos)) 1084 #define SERCOM_I2CS_DATA_MASK _U_(0xFF) /**< \brief (SERCOM_I2CS_DATA) MASK Register */ 1085 1086 /* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x18) (R/W 16) SPI SPI Data -------- */ 1087 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1088 typedef union { 1089 struct { 1090 uint16_t DATA:9; /*!< bit: 0.. 8 Data */ 1091 uint16_t :7; /*!< bit: 9..15 Reserved */ 1092 } bit; /*!< Structure used for bit access */ 1093 uint16_t reg; /*!< Type used for register access */ 1094 } SERCOM_SPI_DATA_Type; 1095 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1096 1097 #define SERCOM_SPI_DATA_OFFSET 0x18 /**< \brief (SERCOM_SPI_DATA offset) SPI Data */ 1098 #define SERCOM_SPI_DATA_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_SPI_DATA reset_value) SPI Data */ 1099 1100 #define SERCOM_SPI_DATA_DATA_Pos 0 /**< \brief (SERCOM_SPI_DATA) Data */ 1101 #define SERCOM_SPI_DATA_DATA_Msk (_U_(0x1FF) << SERCOM_SPI_DATA_DATA_Pos) 1102 #define SERCOM_SPI_DATA_DATA(value) (SERCOM_SPI_DATA_DATA_Msk & ((value) << SERCOM_SPI_DATA_DATA_Pos)) 1103 #define SERCOM_SPI_DATA_MASK _U_(0x01FF) /**< \brief (SERCOM_SPI_DATA) MASK Register */ 1104 1105 /* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x18) (R/W 16) USART USART Data -------- */ 1106 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1107 typedef union { 1108 struct { 1109 uint16_t DATA:9; /*!< bit: 0.. 8 Data */ 1110 uint16_t :7; /*!< bit: 9..15 Reserved */ 1111 } bit; /*!< Structure used for bit access */ 1112 uint16_t reg; /*!< Type used for register access */ 1113 } SERCOM_USART_DATA_Type; 1114 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1115 1116 #define SERCOM_USART_DATA_OFFSET 0x18 /**< \brief (SERCOM_USART_DATA offset) USART Data */ 1117 #define SERCOM_USART_DATA_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_USART_DATA reset_value) USART Data */ 1118 1119 #define SERCOM_USART_DATA_DATA_Pos 0 /**< \brief (SERCOM_USART_DATA) Data */ 1120 #define SERCOM_USART_DATA_DATA_Msk (_U_(0x1FF) << SERCOM_USART_DATA_DATA_Pos) 1121 #define SERCOM_USART_DATA_DATA(value) (SERCOM_USART_DATA_DATA_Msk & ((value) << SERCOM_USART_DATA_DATA_Pos)) 1122 #define SERCOM_USART_DATA_MASK _U_(0x01FF) /**< \brief (SERCOM_USART_DATA) MASK Register */ 1123 1124 /** \brief SERCOM_I2CM hardware registers */ 1125 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1126 typedef struct { /* I2C Master Mode */ 1127 __IO SERCOM_I2CM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */ 1128 __IO SERCOM_I2CM_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */ 1129 __IO SERCOM_I2CM_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) I2CM Debug Control */ 1130 RoReg8 Reserved1[0x1]; 1131 __IO SERCOM_I2CM_BAUD_Type BAUD; /**< \brief Offset: 0x0A (R/W 16) I2CM Baud Rate */ 1132 __IO SERCOM_I2CM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) I2CM Interrupt Enable Clear */ 1133 __IO SERCOM_I2CM_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) I2CM Interrupt Enable Set */ 1134 __IO SERCOM_I2CM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) I2CM Interrupt Flag Status and Clear */ 1135 RoReg8 Reserved2[0x1]; 1136 __IO SERCOM_I2CM_STATUS_Type STATUS; /**< \brief Offset: 0x10 (R/W 16) I2CM Status */ 1137 RoReg8 Reserved3[0x2]; 1138 __IO SERCOM_I2CM_ADDR_Type ADDR; /**< \brief Offset: 0x14 (R/W 8) I2CM Address */ 1139 RoReg8 Reserved4[0x3]; 1140 __IO SERCOM_I2CM_DATA_Type DATA; /**< \brief Offset: 0x18 (R/W 8) I2CM Data */ 1141 } SercomI2cm; 1142 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1143 1144 /** \brief SERCOM_I2CS hardware registers */ 1145 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1146 typedef struct { /* I2C Slave Mode */ 1147 __IO SERCOM_I2CS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */ 1148 __IO SERCOM_I2CS_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */ 1149 RoReg8 Reserved1[0x4]; 1150 __IO SERCOM_I2CS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) I2CS Interrupt Enable Clear */ 1151 __IO SERCOM_I2CS_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) I2CS Interrupt Enable Set */ 1152 __IO SERCOM_I2CS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) I2CS Interrupt Flag Status and Clear */ 1153 RoReg8 Reserved2[0x1]; 1154 __IO SERCOM_I2CS_STATUS_Type STATUS; /**< \brief Offset: 0x10 (R/W 16) I2CS Status */ 1155 RoReg8 Reserved3[0x2]; 1156 __IO SERCOM_I2CS_ADDR_Type ADDR; /**< \brief Offset: 0x14 (R/W 32) I2CS Address */ 1157 __IO SERCOM_I2CS_DATA_Type DATA; /**< \brief Offset: 0x18 (R/W 8) I2CS Data */ 1158 } SercomI2cs; 1159 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1160 1161 /** \brief SERCOM_SPI hardware registers */ 1162 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1163 typedef struct { /* SPI Mode */ 1164 __IO SERCOM_SPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) SPI Control A */ 1165 __IO SERCOM_SPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) SPI Control B */ 1166 __IO SERCOM_SPI_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) SPI Debug Control */ 1167 RoReg8 Reserved1[0x1]; 1168 __IO SERCOM_SPI_BAUD_Type BAUD; /**< \brief Offset: 0x0A (R/W 8) SPI Baud Rate */ 1169 RoReg8 Reserved2[0x1]; 1170 __IO SERCOM_SPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) SPI Interrupt Enable Clear */ 1171 __IO SERCOM_SPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) SPI Interrupt Enable Set */ 1172 __IO SERCOM_SPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) SPI Interrupt Flag Status and Clear */ 1173 RoReg8 Reserved3[0x1]; 1174 __IO SERCOM_SPI_STATUS_Type STATUS; /**< \brief Offset: 0x10 (R/W 16) SPI Status */ 1175 RoReg8 Reserved4[0x2]; 1176 __IO SERCOM_SPI_ADDR_Type ADDR; /**< \brief Offset: 0x14 (R/W 32) SPI Address */ 1177 __IO SERCOM_SPI_DATA_Type DATA; /**< \brief Offset: 0x18 (R/W 16) SPI Data */ 1178 } SercomSpi; 1179 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1180 1181 /** \brief SERCOM_USART hardware registers */ 1182 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1183 typedef struct { /* USART Mode */ 1184 __IO SERCOM_USART_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) USART Control A */ 1185 __IO SERCOM_USART_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) USART Control B */ 1186 __IO SERCOM_USART_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) USART Debug Control */ 1187 RoReg8 Reserved1[0x1]; 1188 __IO SERCOM_USART_BAUD_Type BAUD; /**< \brief Offset: 0x0A (R/W 16) USART Baud */ 1189 __IO SERCOM_USART_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) USART Interrupt Enable Clear */ 1190 __IO SERCOM_USART_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) USART Interrupt Enable Set */ 1191 __IO SERCOM_USART_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) USART Interrupt Flag Status and Clear */ 1192 RoReg8 Reserved2[0x1]; 1193 __IO SERCOM_USART_STATUS_Type STATUS; /**< \brief Offset: 0x10 (R/W 16) USART Status */ 1194 RoReg8 Reserved3[0x6]; 1195 __IO SERCOM_USART_DATA_Type DATA; /**< \brief Offset: 0x18 (R/W 16) USART Data */ 1196 } SercomUsart; 1197 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1198 1199 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1200 typedef union { 1201 SercomI2cm I2CM; /**< \brief Offset: 0x00 I2C Master Mode */ 1202 SercomI2cs I2CS; /**< \brief Offset: 0x00 I2C Slave Mode */ 1203 SercomSpi SPI; /**< \brief Offset: 0x00 SPI Mode */ 1204 SercomUsart USART; /**< \brief Offset: 0x00 USART Mode */ 1205 } Sercom; 1206 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1207 1208 /*@}*/ 1209 1210 #endif /* _SAMD20_SERCOM_COMPONENT_ */ 1211
