1 /** 2 * \file 3 * 4 * \brief Component description for PAC 5 * 6 * Copyright (c) 2017 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMD20_PAC_COMPONENT_ 31 #define _SAMD20_PAC_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR PAC */ 35 /* ========================================================================== */ 36 /** \addtogroup SAMD20_PAC Peripheral Access Controller */ 37 /*@{*/ 38 39 #define PAC_U2211 40 #define REV_PAC 0x101 41 42 /* -------- PAC_WPCLR : (PAC Offset: 0x0) (R/W 32) Write Protection Clear -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint32_t :1; /*!< bit: 0 Reserved */ 47 uint32_t WP:31; /*!< bit: 1..31 Write Protection Clear */ 48 } bit; /*!< Structure used for bit access */ 49 uint32_t reg; /*!< Type used for register access */ 50 } PAC_WPCLR_Type; 51 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 52 53 #define PAC_WPCLR_OFFSET 0x0 /**< \brief (PAC_WPCLR offset) Write Protection Clear */ 54 #define PAC_WPCLR_RESETVALUE _U_(0x00000000) /**< \brief (PAC_WPCLR reset_value) Write Protection Clear */ 55 56 #define PAC_WPCLR_WP_Pos 1 /**< \brief (PAC_WPCLR) Write Protection Clear */ 57 #define PAC_WPCLR_WP_Msk (_U_(0x7FFFFFFF) << PAC_WPCLR_WP_Pos) 58 #define PAC_WPCLR_WP(value) (PAC_WPCLR_WP_Msk & ((value) << PAC_WPCLR_WP_Pos)) 59 #define PAC_WPCLR_MASK _U_(0xFFFFFFFE) /**< \brief (PAC_WPCLR) MASK Register */ 60 61 /* -------- PAC_WPSET : (PAC Offset: 0x4) (R/W 32) Write Protection Set -------- */ 62 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 63 typedef union { 64 struct { 65 uint32_t :1; /*!< bit: 0 Reserved */ 66 uint32_t WP:31; /*!< bit: 1..31 Write Protection Set */ 67 } bit; /*!< Structure used for bit access */ 68 uint32_t reg; /*!< Type used for register access */ 69 } PAC_WPSET_Type; 70 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 71 72 #define PAC_WPSET_OFFSET 0x4 /**< \brief (PAC_WPSET offset) Write Protection Set */ 73 #define PAC_WPSET_RESETVALUE _U_(0x00000000) /**< \brief (PAC_WPSET reset_value) Write Protection Set */ 74 75 #define PAC_WPSET_WP_Pos 1 /**< \brief (PAC_WPSET) Write Protection Set */ 76 #define PAC_WPSET_WP_Msk (_U_(0x7FFFFFFF) << PAC_WPSET_WP_Pos) 77 #define PAC_WPSET_WP(value) (PAC_WPSET_WP_Msk & ((value) << PAC_WPSET_WP_Pos)) 78 #define PAC_WPSET_MASK _U_(0xFFFFFFFE) /**< \brief (PAC_WPSET) MASK Register */ 79 80 /** \brief PAC hardware registers */ 81 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 82 typedef struct { 83 __IO PAC_WPCLR_Type WPCLR; /**< \brief Offset: 0x0 (R/W 32) Write Protection Clear */ 84 __IO PAC_WPSET_Type WPSET; /**< \brief Offset: 0x4 (R/W 32) Write Protection Set */ 85 } Pac; 86 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 87 88 /*@}*/ 89 90 #endif /* _SAMD20_PAC_COMPONENT_ */ 91
