1 /** 2 * \file 3 * 4 * \brief Component description for NVMCTRL 5 * 6 * Copyright (c) 2017 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMD20_NVMCTRL_COMPONENT_ 31 #define _SAMD20_NVMCTRL_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR NVMCTRL */ 35 /* ========================================================================== */ 36 /** \addtogroup SAMD20_NVMCTRL Non-Volatile Memory Controller */ 37 /*@{*/ 38 39 #define NVMCTRL_U2207 40 #define REV_NVMCTRL 0x106 41 42 /* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint16_t CMD:7; /*!< bit: 0.. 6 Command */ 47 uint16_t :1; /*!< bit: 7 Reserved */ 48 uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */ 49 } bit; /*!< Structure used for bit access */ 50 uint16_t reg; /*!< Type used for register access */ 51 } NVMCTRL_CTRLA_Type; 52 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 53 54 #define NVMCTRL_CTRLA_OFFSET 0x00 /**< \brief (NVMCTRL_CTRLA offset) Control A */ 55 #define NVMCTRL_CTRLA_RESETVALUE _U_(0x0000) /**< \brief (NVMCTRL_CTRLA reset_value) Control A */ 56 57 #define NVMCTRL_CTRLA_CMD_Pos 0 /**< \brief (NVMCTRL_CTRLA) Command */ 58 #define NVMCTRL_CTRLA_CMD_Msk (_U_(0x7F) << NVMCTRL_CTRLA_CMD_Pos) 59 #define NVMCTRL_CTRLA_CMD(value) (NVMCTRL_CTRLA_CMD_Msk & ((value) << NVMCTRL_CTRLA_CMD_Pos)) 60 #define NVMCTRL_CTRLA_CMD_ER_Val _U_(0x2) /**< \brief (NVMCTRL_CTRLA) Erase Row - Erases the row addressed by the ADDR register. */ 61 #define NVMCTRL_CTRLA_CMD_WP_Val _U_(0x4) /**< \brief (NVMCTRL_CTRLA) Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */ 62 #define NVMCTRL_CTRLA_CMD_EAR_Val _U_(0x5) /**< \brief (NVMCTRL_CTRLA) Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */ 63 #define NVMCTRL_CTRLA_CMD_WAP_Val _U_(0x6) /**< \brief (NVMCTRL_CTRLA) Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */ 64 #define NVMCTRL_CTRLA_CMD_SF_Val _U_(0xA) /**< \brief (NVMCTRL_CTRLA) Security Flow Command */ 65 #define NVMCTRL_CTRLA_CMD_WL_Val _U_(0xF) /**< \brief (NVMCTRL_CTRLA) Write lockbits */ 66 #define NVMCTRL_CTRLA_CMD_LR_Val _U_(0x40) /**< \brief (NVMCTRL_CTRLA) Lock Region - Locks the region containing the address location in the ADDR register. */ 67 #define NVMCTRL_CTRLA_CMD_UR_Val _U_(0x41) /**< \brief (NVMCTRL_CTRLA) Unlock Region - Unlocks the region containing the address location in the ADDR register. */ 68 #define NVMCTRL_CTRLA_CMD_SPRM_Val _U_(0x42) /**< \brief (NVMCTRL_CTRLA) Sets the power reduction mode. */ 69 #define NVMCTRL_CTRLA_CMD_CPRM_Val _U_(0x43) /**< \brief (NVMCTRL_CTRLA) Clears the power reduction mode. */ 70 #define NVMCTRL_CTRLA_CMD_PBC_Val _U_(0x44) /**< \brief (NVMCTRL_CTRLA) Page Buffer Clear - Clears the page buffer. */ 71 #define NVMCTRL_CTRLA_CMD_SSB_Val _U_(0x45) /**< \brief (NVMCTRL_CTRLA) Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. */ 72 #define NVMCTRL_CTRLA_CMD_INVALL_Val _U_(0x46) /**< \brief (NVMCTRL_CTRLA) Invalidate all cache lines. */ 73 #define NVMCTRL_CTRLA_CMD_ER (NVMCTRL_CTRLA_CMD_ER_Val << NVMCTRL_CTRLA_CMD_Pos) 74 #define NVMCTRL_CTRLA_CMD_WP (NVMCTRL_CTRLA_CMD_WP_Val << NVMCTRL_CTRLA_CMD_Pos) 75 #define NVMCTRL_CTRLA_CMD_EAR (NVMCTRL_CTRLA_CMD_EAR_Val << NVMCTRL_CTRLA_CMD_Pos) 76 #define NVMCTRL_CTRLA_CMD_WAP (NVMCTRL_CTRLA_CMD_WAP_Val << NVMCTRL_CTRLA_CMD_Pos) 77 #define NVMCTRL_CTRLA_CMD_SF (NVMCTRL_CTRLA_CMD_SF_Val << NVMCTRL_CTRLA_CMD_Pos) 78 #define NVMCTRL_CTRLA_CMD_WL (NVMCTRL_CTRLA_CMD_WL_Val << NVMCTRL_CTRLA_CMD_Pos) 79 #define NVMCTRL_CTRLA_CMD_LR (NVMCTRL_CTRLA_CMD_LR_Val << NVMCTRL_CTRLA_CMD_Pos) 80 #define NVMCTRL_CTRLA_CMD_UR (NVMCTRL_CTRLA_CMD_UR_Val << NVMCTRL_CTRLA_CMD_Pos) 81 #define NVMCTRL_CTRLA_CMD_SPRM (NVMCTRL_CTRLA_CMD_SPRM_Val << NVMCTRL_CTRLA_CMD_Pos) 82 #define NVMCTRL_CTRLA_CMD_CPRM (NVMCTRL_CTRLA_CMD_CPRM_Val << NVMCTRL_CTRLA_CMD_Pos) 83 #define NVMCTRL_CTRLA_CMD_PBC (NVMCTRL_CTRLA_CMD_PBC_Val << NVMCTRL_CTRLA_CMD_Pos) 84 #define NVMCTRL_CTRLA_CMD_SSB (NVMCTRL_CTRLA_CMD_SSB_Val << NVMCTRL_CTRLA_CMD_Pos) 85 #define NVMCTRL_CTRLA_CMD_INVALL (NVMCTRL_CTRLA_CMD_INVALL_Val << NVMCTRL_CTRLA_CMD_Pos) 86 #define NVMCTRL_CTRLA_CMDEX_Pos 8 /**< \brief (NVMCTRL_CTRLA) Command Execution */ 87 #define NVMCTRL_CTRLA_CMDEX_Msk (_U_(0xFF) << NVMCTRL_CTRLA_CMDEX_Pos) 88 #define NVMCTRL_CTRLA_CMDEX(value) (NVMCTRL_CTRLA_CMDEX_Msk & ((value) << NVMCTRL_CTRLA_CMDEX_Pos)) 89 #define NVMCTRL_CTRLA_CMDEX_KEY_Val _U_(0xA5) /**< \brief (NVMCTRL_CTRLA) Execution Key */ 90 #define NVMCTRL_CTRLA_CMDEX_KEY (NVMCTRL_CTRLA_CMDEX_KEY_Val << NVMCTRL_CTRLA_CMDEX_Pos) 91 #define NVMCTRL_CTRLA_MASK _U_(0xFF7F) /**< \brief (NVMCTRL_CTRLA) MASK Register */ 92 93 /* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) (R/W 32) Control B -------- */ 94 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 95 typedef union { 96 struct { 97 uint32_t :1; /*!< bit: 0 Reserved */ 98 uint32_t RWS:4; /*!< bit: 1.. 4 NVM Read Wait States */ 99 uint32_t :2; /*!< bit: 5.. 6 Reserved */ 100 uint32_t MANW:1; /*!< bit: 7 Manual Write */ 101 uint32_t SLEEPPRM:2; /*!< bit: 8.. 9 Power Reduction Mode during Sleep */ 102 uint32_t :6; /*!< bit: 10..15 Reserved */ 103 uint32_t READMODE:2; /*!< bit: 16..17 NVMCTRL Read Mode */ 104 uint32_t CACHEDIS:1; /*!< bit: 18 Cache Disable */ 105 uint32_t :13; /*!< bit: 19..31 Reserved */ 106 } bit; /*!< Structure used for bit access */ 107 uint32_t reg; /*!< Type used for register access */ 108 } NVMCTRL_CTRLB_Type; 109 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 110 111 #define NVMCTRL_CTRLB_OFFSET 0x04 /**< \brief (NVMCTRL_CTRLB offset) Control B */ 112 #define NVMCTRL_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (NVMCTRL_CTRLB reset_value) Control B */ 113 114 #define NVMCTRL_CTRLB_RWS_Pos 1 /**< \brief (NVMCTRL_CTRLB) NVM Read Wait States */ 115 #define NVMCTRL_CTRLB_RWS_Msk (_U_(0xF) << NVMCTRL_CTRLB_RWS_Pos) 116 #define NVMCTRL_CTRLB_RWS(value) (NVMCTRL_CTRLB_RWS_Msk & ((value) << NVMCTRL_CTRLB_RWS_Pos)) 117 #define NVMCTRL_CTRLB_RWS_SINGLE_Val _U_(0x0) /**< \brief (NVMCTRL_CTRLB) Single Auto Wait State */ 118 #define NVMCTRL_CTRLB_RWS_HALF_Val _U_(0x1) /**< \brief (NVMCTRL_CTRLB) Half Auto Wait State */ 119 #define NVMCTRL_CTRLB_RWS_DUAL_Val _U_(0x2) /**< \brief (NVMCTRL_CTRLB) Dual Auto Wait State */ 120 #define NVMCTRL_CTRLB_RWS_SINGLE (NVMCTRL_CTRLB_RWS_SINGLE_Val << NVMCTRL_CTRLB_RWS_Pos) 121 #define NVMCTRL_CTRLB_RWS_HALF (NVMCTRL_CTRLB_RWS_HALF_Val << NVMCTRL_CTRLB_RWS_Pos) 122 #define NVMCTRL_CTRLB_RWS_DUAL (NVMCTRL_CTRLB_RWS_DUAL_Val << NVMCTRL_CTRLB_RWS_Pos) 123 #define NVMCTRL_CTRLB_MANW_Pos 7 /**< \brief (NVMCTRL_CTRLB) Manual Write */ 124 #define NVMCTRL_CTRLB_MANW (_U_(0x1) << NVMCTRL_CTRLB_MANW_Pos) 125 #define NVMCTRL_CTRLB_SLEEPPRM_Pos 8 /**< \brief (NVMCTRL_CTRLB) Power Reduction Mode during Sleep */ 126 #define NVMCTRL_CTRLB_SLEEPPRM_Msk (_U_(0x3) << NVMCTRL_CTRLB_SLEEPPRM_Pos) 127 #define NVMCTRL_CTRLB_SLEEPPRM(value) (NVMCTRL_CTRLB_SLEEPPRM_Msk & ((value) << NVMCTRL_CTRLB_SLEEPPRM_Pos)) 128 #define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val _U_(0x0) /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. */ 129 #define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val _U_(0x1) /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. */ 130 #define NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val _U_(0x3) /**< \brief (NVMCTRL_CTRLB) Auto power reduction disabled. */ 131 #define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS (NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos) 132 #define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT (NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos) 133 #define NVMCTRL_CTRLB_SLEEPPRM_DISABLED (NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos) 134 #define NVMCTRL_CTRLB_READMODE_Pos 16 /**< \brief (NVMCTRL_CTRLB) NVMCTRL Read Mode */ 135 #define NVMCTRL_CTRLB_READMODE_Msk (_U_(0x3) << NVMCTRL_CTRLB_READMODE_Pos) 136 #define NVMCTRL_CTRLB_READMODE(value) (NVMCTRL_CTRLB_READMODE_Msk & ((value) << NVMCTRL_CTRLB_READMODE_Pos)) 137 #define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val _U_(0x0) /**< \brief (NVMCTRL_CTRLB) The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. */ 138 #define NVMCTRL_CTRLB_READMODE_LOW_POWER_Val _U_(0x1) /**< \brief (NVMCTRL_CTRLB) Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. */ 139 #define NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val _U_(0x2) /**< \brief (NVMCTRL_CTRLB) The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. */ 140 #define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY (NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val << NVMCTRL_CTRLB_READMODE_Pos) 141 #define NVMCTRL_CTRLB_READMODE_LOW_POWER (NVMCTRL_CTRLB_READMODE_LOW_POWER_Val << NVMCTRL_CTRLB_READMODE_Pos) 142 #define NVMCTRL_CTRLB_READMODE_DETERMINISTIC (NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val << NVMCTRL_CTRLB_READMODE_Pos) 143 #define NVMCTRL_CTRLB_CACHEDIS_Pos 18 /**< \brief (NVMCTRL_CTRLB) Cache Disable */ 144 #define NVMCTRL_CTRLB_CACHEDIS (_U_(0x1) << NVMCTRL_CTRLB_CACHEDIS_Pos) 145 #define NVMCTRL_CTRLB_MASK _U_(0x0007039E) /**< \brief (NVMCTRL_CTRLB) MASK Register */ 146 147 /* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/W 32) NVM Parameter -------- */ 148 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 149 typedef union { 150 struct { 151 uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */ 152 uint32_t PSZ:3; /*!< bit: 16..18 Page Size */ 153 uint32_t :13; /*!< bit: 19..31 Reserved */ 154 } bit; /*!< Structure used for bit access */ 155 uint32_t reg; /*!< Type used for register access */ 156 } NVMCTRL_PARAM_Type; 157 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 158 159 #define NVMCTRL_PARAM_OFFSET 0x08 /**< \brief (NVMCTRL_PARAM offset) NVM Parameter */ 160 #define NVMCTRL_PARAM_RESETVALUE _U_(0x00000000) /**< \brief (NVMCTRL_PARAM reset_value) NVM Parameter */ 161 162 #define NVMCTRL_PARAM_NVMP_Pos 0 /**< \brief (NVMCTRL_PARAM) NVM Pages */ 163 #define NVMCTRL_PARAM_NVMP_Msk (_U_(0xFFFF) << NVMCTRL_PARAM_NVMP_Pos) 164 #define NVMCTRL_PARAM_NVMP(value) (NVMCTRL_PARAM_NVMP_Msk & ((value) << NVMCTRL_PARAM_NVMP_Pos)) 165 #define NVMCTRL_PARAM_PSZ_Pos 16 /**< \brief (NVMCTRL_PARAM) Page Size */ 166 #define NVMCTRL_PARAM_PSZ_Msk (_U_(0x7) << NVMCTRL_PARAM_PSZ_Pos) 167 #define NVMCTRL_PARAM_PSZ(value) (NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos)) 168 #define NVMCTRL_PARAM_PSZ_8_Val _U_(0x0) /**< \brief (NVMCTRL_PARAM) 8 bytes */ 169 #define NVMCTRL_PARAM_PSZ_16_Val _U_(0x1) /**< \brief (NVMCTRL_PARAM) 16 bytes */ 170 #define NVMCTRL_PARAM_PSZ_32_Val _U_(0x2) /**< \brief (NVMCTRL_PARAM) 32 bytes */ 171 #define NVMCTRL_PARAM_PSZ_64_Val _U_(0x3) /**< \brief (NVMCTRL_PARAM) 64 bytes */ 172 #define NVMCTRL_PARAM_PSZ_128_Val _U_(0x4) /**< \brief (NVMCTRL_PARAM) 128 bytes */ 173 #define NVMCTRL_PARAM_PSZ_256_Val _U_(0x5) /**< \brief (NVMCTRL_PARAM) 256 bytes */ 174 #define NVMCTRL_PARAM_PSZ_512_Val _U_(0x6) /**< \brief (NVMCTRL_PARAM) 512 bytes */ 175 #define NVMCTRL_PARAM_PSZ_1024_Val _U_(0x7) /**< \brief (NVMCTRL_PARAM) 1024 bytes */ 176 #define NVMCTRL_PARAM_PSZ_8 (NVMCTRL_PARAM_PSZ_8_Val << NVMCTRL_PARAM_PSZ_Pos) 177 #define NVMCTRL_PARAM_PSZ_16 (NVMCTRL_PARAM_PSZ_16_Val << NVMCTRL_PARAM_PSZ_Pos) 178 #define NVMCTRL_PARAM_PSZ_32 (NVMCTRL_PARAM_PSZ_32_Val << NVMCTRL_PARAM_PSZ_Pos) 179 #define NVMCTRL_PARAM_PSZ_64 (NVMCTRL_PARAM_PSZ_64_Val << NVMCTRL_PARAM_PSZ_Pos) 180 #define NVMCTRL_PARAM_PSZ_128 (NVMCTRL_PARAM_PSZ_128_Val << NVMCTRL_PARAM_PSZ_Pos) 181 #define NVMCTRL_PARAM_PSZ_256 (NVMCTRL_PARAM_PSZ_256_Val << NVMCTRL_PARAM_PSZ_Pos) 182 #define NVMCTRL_PARAM_PSZ_512 (NVMCTRL_PARAM_PSZ_512_Val << NVMCTRL_PARAM_PSZ_Pos) 183 #define NVMCTRL_PARAM_PSZ_1024 (NVMCTRL_PARAM_PSZ_1024_Val << NVMCTRL_PARAM_PSZ_Pos) 184 #define NVMCTRL_PARAM_MASK _U_(0x0007FFFF) /**< \brief (NVMCTRL_PARAM) MASK Register */ 185 186 /* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */ 187 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 188 typedef union { 189 struct { 190 uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */ 191 uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */ 192 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 193 } bit; /*!< Structure used for bit access */ 194 uint8_t reg; /*!< Type used for register access */ 195 } NVMCTRL_INTENCLR_Type; 196 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 197 198 #define NVMCTRL_INTENCLR_OFFSET 0x0C /**< \brief (NVMCTRL_INTENCLR offset) Interrupt Enable Clear */ 199 #define NVMCTRL_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (NVMCTRL_INTENCLR reset_value) Interrupt Enable Clear */ 200 201 #define NVMCTRL_INTENCLR_READY_Pos 0 /**< \brief (NVMCTRL_INTENCLR) NVM Ready Interrupt Enable */ 202 #define NVMCTRL_INTENCLR_READY (_U_(0x1) << NVMCTRL_INTENCLR_READY_Pos) 203 #define NVMCTRL_INTENCLR_ERROR_Pos 1 /**< \brief (NVMCTRL_INTENCLR) Error Interrupt Enable */ 204 #define NVMCTRL_INTENCLR_ERROR (_U_(0x1) << NVMCTRL_INTENCLR_ERROR_Pos) 205 #define NVMCTRL_INTENCLR_MASK _U_(0x03) /**< \brief (NVMCTRL_INTENCLR) MASK Register */ 206 207 /* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x10) (R/W 8) Interrupt Enable Set -------- */ 208 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 209 typedef union { 210 struct { 211 uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */ 212 uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */ 213 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 214 } bit; /*!< Structure used for bit access */ 215 uint8_t reg; /*!< Type used for register access */ 216 } NVMCTRL_INTENSET_Type; 217 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 218 219 #define NVMCTRL_INTENSET_OFFSET 0x10 /**< \brief (NVMCTRL_INTENSET offset) Interrupt Enable Set */ 220 #define NVMCTRL_INTENSET_RESETVALUE _U_(0x00) /**< \brief (NVMCTRL_INTENSET reset_value) Interrupt Enable Set */ 221 222 #define NVMCTRL_INTENSET_READY_Pos 0 /**< \brief (NVMCTRL_INTENSET) NVM Ready Interrupt Enable */ 223 #define NVMCTRL_INTENSET_READY (_U_(0x1) << NVMCTRL_INTENSET_READY_Pos) 224 #define NVMCTRL_INTENSET_ERROR_Pos 1 /**< \brief (NVMCTRL_INTENSET) Error Interrupt Enable */ 225 #define NVMCTRL_INTENSET_ERROR (_U_(0x1) << NVMCTRL_INTENSET_ERROR_Pos) 226 #define NVMCTRL_INTENSET_MASK _U_(0x03) /**< \brief (NVMCTRL_INTENSET) MASK Register */ 227 228 /* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x14) (R/W 8) Interrupt Flag Status and Clear -------- */ 229 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 230 typedef union { // __I to avoid read-modify-write on write-to-clear register 231 struct { 232 __I uint8_t READY:1; /*!< bit: 0 NVM Ready */ 233 __I uint8_t ERROR:1; /*!< bit: 1 Error */ 234 __I uint8_t Reserved1:6; /*!< bit: 2.. 7 Reserved */ 235 } bit; /*!< Structure used for bit access */ 236 uint8_t reg; /*!< Type used for register access */ 237 } NVMCTRL_INTFLAG_Type; 238 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 239 240 #define NVMCTRL_INTFLAG_OFFSET 0x14 /**< \brief (NVMCTRL_INTFLAG offset) Interrupt Flag Status and Clear */ 241 #define NVMCTRL_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (NVMCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */ 242 243 #define NVMCTRL_INTFLAG_READY_Pos 0 /**< \brief (NVMCTRL_INTFLAG) NVM Ready */ 244 #define NVMCTRL_INTFLAG_READY (_U_(0x1) << NVMCTRL_INTFLAG_READY_Pos) 245 #define NVMCTRL_INTFLAG_ERROR_Pos 1 /**< \brief (NVMCTRL_INTFLAG) Error */ 246 #define NVMCTRL_INTFLAG_ERROR (_U_(0x1) << NVMCTRL_INTFLAG_ERROR_Pos) 247 #define NVMCTRL_INTFLAG_MASK _U_(0x03) /**< \brief (NVMCTRL_INTFLAG) MASK Register */ 248 249 /* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x18) (R/W 16) Status -------- */ 250 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 251 typedef union { 252 struct { 253 uint16_t PRM:1; /*!< bit: 0 Power Reduction Mode */ 254 uint16_t LOAD:1; /*!< bit: 1 NVM Page Buffer Active Loading */ 255 uint16_t PROGE:1; /*!< bit: 2 Programming Error Status */ 256 uint16_t LOCKE:1; /*!< bit: 3 Lock Error Status */ 257 uint16_t NVME:1; /*!< bit: 4 NVM Error */ 258 uint16_t :3; /*!< bit: 5.. 7 Reserved */ 259 uint16_t SB:1; /*!< bit: 8 Security Bit Status */ 260 uint16_t :7; /*!< bit: 9..15 Reserved */ 261 } bit; /*!< Structure used for bit access */ 262 uint16_t reg; /*!< Type used for register access */ 263 } NVMCTRL_STATUS_Type; 264 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 265 266 #define NVMCTRL_STATUS_OFFSET 0x18 /**< \brief (NVMCTRL_STATUS offset) Status */ 267 #define NVMCTRL_STATUS_RESETVALUE _U_(0x0000) /**< \brief (NVMCTRL_STATUS reset_value) Status */ 268 269 #define NVMCTRL_STATUS_PRM_Pos 0 /**< \brief (NVMCTRL_STATUS) Power Reduction Mode */ 270 #define NVMCTRL_STATUS_PRM (_U_(0x1) << NVMCTRL_STATUS_PRM_Pos) 271 #define NVMCTRL_STATUS_LOAD_Pos 1 /**< \brief (NVMCTRL_STATUS) NVM Page Buffer Active Loading */ 272 #define NVMCTRL_STATUS_LOAD (_U_(0x1) << NVMCTRL_STATUS_LOAD_Pos) 273 #define NVMCTRL_STATUS_PROGE_Pos 2 /**< \brief (NVMCTRL_STATUS) Programming Error Status */ 274 #define NVMCTRL_STATUS_PROGE (_U_(0x1) << NVMCTRL_STATUS_PROGE_Pos) 275 #define NVMCTRL_STATUS_LOCKE_Pos 3 /**< \brief (NVMCTRL_STATUS) Lock Error Status */ 276 #define NVMCTRL_STATUS_LOCKE (_U_(0x1) << NVMCTRL_STATUS_LOCKE_Pos) 277 #define NVMCTRL_STATUS_NVME_Pos 4 /**< \brief (NVMCTRL_STATUS) NVM Error */ 278 #define NVMCTRL_STATUS_NVME (_U_(0x1) << NVMCTRL_STATUS_NVME_Pos) 279 #define NVMCTRL_STATUS_SB_Pos 8 /**< \brief (NVMCTRL_STATUS) Security Bit Status */ 280 #define NVMCTRL_STATUS_SB (_U_(0x1) << NVMCTRL_STATUS_SB_Pos) 281 #define NVMCTRL_STATUS_MASK _U_(0x011F) /**< \brief (NVMCTRL_STATUS) MASK Register */ 282 283 /* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x1C) (R/W 32) Address -------- */ 284 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 285 typedef union { 286 struct { 287 uint32_t ADDR:22; /*!< bit: 0..21 NVM Address */ 288 uint32_t :10; /*!< bit: 22..31 Reserved */ 289 } bit; /*!< Structure used for bit access */ 290 uint32_t reg; /*!< Type used for register access */ 291 } NVMCTRL_ADDR_Type; 292 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 293 294 #define NVMCTRL_ADDR_OFFSET 0x1C /**< \brief (NVMCTRL_ADDR offset) Address */ 295 #define NVMCTRL_ADDR_RESETVALUE _U_(0x00000000) /**< \brief (NVMCTRL_ADDR reset_value) Address */ 296 297 #define NVMCTRL_ADDR_ADDR_Pos 0 /**< \brief (NVMCTRL_ADDR) NVM Address */ 298 #define NVMCTRL_ADDR_ADDR_Msk (_U_(0x3FFFFF) << NVMCTRL_ADDR_ADDR_Pos) 299 #define NVMCTRL_ADDR_ADDR(value) (NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos)) 300 #define NVMCTRL_ADDR_MASK _U_(0x003FFFFF) /**< \brief (NVMCTRL_ADDR) MASK Register */ 301 302 /* -------- NVMCTRL_LOCK : (NVMCTRL Offset: 0x20) (R/W 16) Lock Section -------- */ 303 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 304 typedef union { 305 struct { 306 uint16_t LOCK:16; /*!< bit: 0..15 Region Lock Bits */ 307 } bit; /*!< Structure used for bit access */ 308 uint16_t reg; /*!< Type used for register access */ 309 } NVMCTRL_LOCK_Type; 310 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 311 312 #define NVMCTRL_LOCK_OFFSET 0x20 /**< \brief (NVMCTRL_LOCK offset) Lock Section */ 313 #define NVMCTRL_LOCK_RESETVALUE _U_(0x0000) /**< \brief (NVMCTRL_LOCK reset_value) Lock Section */ 314 315 #define NVMCTRL_LOCK_LOCK_Pos 0 /**< \brief (NVMCTRL_LOCK) Region Lock Bits */ 316 #define NVMCTRL_LOCK_LOCK_Msk (_U_(0xFFFF) << NVMCTRL_LOCK_LOCK_Pos) 317 #define NVMCTRL_LOCK_LOCK(value) (NVMCTRL_LOCK_LOCK_Msk & ((value) << NVMCTRL_LOCK_LOCK_Pos)) 318 #define NVMCTRL_LOCK_MASK _U_(0xFFFF) /**< \brief (NVMCTRL_LOCK) MASK Register */ 319 320 /** \brief NVMCTRL APB hardware registers */ 321 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 322 typedef struct { 323 __IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ 324 RoReg8 Reserved1[0x2]; 325 __IO NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */ 326 __IO NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */ 327 __IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ 328 RoReg8 Reserved2[0x3]; 329 __IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 8) Interrupt Enable Set */ 330 RoReg8 Reserved3[0x3]; 331 __IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 8) Interrupt Flag Status and Clear */ 332 RoReg8 Reserved4[0x3]; 333 __IO NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x18 (R/W 16) Status */ 334 RoReg8 Reserved5[0x2]; 335 __IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x1C (R/W 32) Address */ 336 __IO NVMCTRL_LOCK_Type LOCK; /**< \brief Offset: 0x20 (R/W 16) Lock Section */ 337 } Nvmctrl; 338 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 339 340 #define SECTION_NVMCTRL_CAL 341 342 #define SECTION_NVMCTRL_LOCKBIT 343 344 #define SECTION_NVMCTRL_OTP1 345 346 #define SECTION_NVMCTRL_OTP2 347 348 #define SECTION_NVMCTRL_OTP4 349 350 #define SECTION_NVMCTRL_TEMP_LOG 351 352 #define SECTION_NVMCTRL_USER 353 354 /*@}*/ 355 356 /* ************************************************************************** */ 357 /** SOFTWARE PERIPHERAL API DEFINITION FOR NON-VOLATILE FUSES */ 358 /* ************************************************************************** */ 359 /** \addtogroup fuses_api Peripheral Software API */ 360 /*@{*/ 361 362 363 #define ADC_FUSES_BIASCAL_ADDR (NVMCTRL_OTP4 + 4) 364 #define ADC_FUSES_BIASCAL_Pos 3 /**< \brief (NVMCTRL_OTP4) ADC Bias Calibration */ 365 #define ADC_FUSES_BIASCAL_Msk (_U_(0x7) << ADC_FUSES_BIASCAL_Pos) 366 #define ADC_FUSES_BIASCAL(value) (ADC_FUSES_BIASCAL_Msk & ((value) << ADC_FUSES_BIASCAL_Pos)) 367 368 #define ADC_FUSES_LINEARITY_0_ADDR NVMCTRL_OTP4 369 #define ADC_FUSES_LINEARITY_0_Pos 27 /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 4:0 */ 370 #define ADC_FUSES_LINEARITY_0_Msk (_U_(0x1F) << ADC_FUSES_LINEARITY_0_Pos) 371 #define ADC_FUSES_LINEARITY_0(value) (ADC_FUSES_LINEARITY_0_Msk & ((value) << ADC_FUSES_LINEARITY_0_Pos)) 372 373 #define ADC_FUSES_LINEARITY_1_ADDR (NVMCTRL_OTP4 + 4) 374 #define ADC_FUSES_LINEARITY_1_Pos 0 /**< \brief (NVMCTRL_OTP4) ADC Linearity bits 7:5 */ 375 #define ADC_FUSES_LINEARITY_1_Msk (_U_(0x7) << ADC_FUSES_LINEARITY_1_Pos) 376 #define ADC_FUSES_LINEARITY_1(value) (ADC_FUSES_LINEARITY_1_Msk & ((value) << ADC_FUSES_LINEARITY_1_Pos)) 377 378 #define FUSES_BOD33USERLEVEL_ADDR NVMCTRL_USER 379 #define FUSES_BOD33USERLEVEL_Pos 8 /**< \brief (NVMCTRL_USER) BOD33 User Level */ 380 #define FUSES_BOD33USERLEVEL_Msk (_U_(0x3F) << FUSES_BOD33USERLEVEL_Pos) 381 #define FUSES_BOD33USERLEVEL(value) (FUSES_BOD33USERLEVEL_Msk & ((value) << FUSES_BOD33USERLEVEL_Pos)) 382 383 #define FUSES_BOD33_ACTION_ADDR NVMCTRL_USER 384 #define FUSES_BOD33_ACTION_Pos 15 /**< \brief (NVMCTRL_USER) BOD33 Action */ 385 #define FUSES_BOD33_ACTION_Msk (_U_(0x3) << FUSES_BOD33_ACTION_Pos) 386 #define FUSES_BOD33_ACTION(value) (FUSES_BOD33_ACTION_Msk & ((value) << FUSES_BOD33_ACTION_Pos)) 387 388 #define FUSES_BOD33_EN_ADDR NVMCTRL_USER 389 #define FUSES_BOD33_EN_Pos 14 /**< \brief (NVMCTRL_USER) BOD33 Enable */ 390 #define FUSES_BOD33_EN_Msk (_U_(0x1) << FUSES_BOD33_EN_Pos) 391 392 #define FUSES_BOD33_HYST_ADDR (NVMCTRL_USER + 4) 393 #define FUSES_BOD33_HYST_Pos 8 /**< \brief (NVMCTRL_USER) BOD33 Hysteresis */ 394 #define FUSES_BOD33_HYST_Msk (_U_(0x1) << FUSES_BOD33_HYST_Pos) 395 396 #define FUSES_DFLL48M_COARSE_CAL_ADDR (NVMCTRL_OTP4 + 4) 397 #define FUSES_DFLL48M_COARSE_CAL_Pos 26 /**< \brief (NVMCTRL_OTP4) DFLL48M Coarse Calibration */ 398 #define FUSES_DFLL48M_COARSE_CAL_Msk (_U_(0x3F) << FUSES_DFLL48M_COARSE_CAL_Pos) 399 #define FUSES_DFLL48M_COARSE_CAL(value) (FUSES_DFLL48M_COARSE_CAL_Msk & ((value) << FUSES_DFLL48M_COARSE_CAL_Pos)) 400 401 #define FUSES_DFLL48M_FINE_CAL_ADDR (NVMCTRL_OTP4 + 8) 402 #define FUSES_DFLL48M_FINE_CAL_Pos 0 /**< \brief (NVMCTRL_OTP4) DFLL48M Fine Calibration */ 403 #define FUSES_DFLL48M_FINE_CAL_Msk (_U_(0x3FF) << FUSES_DFLL48M_FINE_CAL_Pos) 404 #define FUSES_DFLL48M_FINE_CAL(value) (FUSES_DFLL48M_FINE_CAL_Msk & ((value) << FUSES_DFLL48M_FINE_CAL_Pos)) 405 406 #define FUSES_OSC32KCAL_ADDR (NVMCTRL_OTP4 + 4) 407 #define FUSES_OSC32KCAL_Pos 6 /**< \brief (NVMCTRL_OTP4) OSC32K Calibration */ 408 #define FUSES_OSC32KCAL_Msk (_U_(0x7F) << FUSES_OSC32KCAL_Pos) 409 #define FUSES_OSC32KCAL(value) (FUSES_OSC32KCAL_Msk & ((value) << FUSES_OSC32KCAL_Pos)) 410 411 #define NVMCTRL_FUSES_BOOTPROT_ADDR NVMCTRL_USER 412 #define NVMCTRL_FUSES_BOOTPROT_Pos 0 /**< \brief (NVMCTRL_USER) Bootloader Size */ 413 #define NVMCTRL_FUSES_BOOTPROT_Msk (_U_(0x7) << NVMCTRL_FUSES_BOOTPROT_Pos) 414 #define NVMCTRL_FUSES_BOOTPROT(value) (NVMCTRL_FUSES_BOOTPROT_Msk & ((value) << NVMCTRL_FUSES_BOOTPROT_Pos)) 415 416 #define NVMCTRL_FUSES_EEPROM_SIZE_ADDR NVMCTRL_USER 417 #define NVMCTRL_FUSES_EEPROM_SIZE_Pos 4 /**< \brief (NVMCTRL_USER) EEPROM Size */ 418 #define NVMCTRL_FUSES_EEPROM_SIZE_Msk (_U_(0x7) << NVMCTRL_FUSES_EEPROM_SIZE_Pos) 419 #define NVMCTRL_FUSES_EEPROM_SIZE(value) (NVMCTRL_FUSES_EEPROM_SIZE_Msk & ((value) << NVMCTRL_FUSES_EEPROM_SIZE_Pos)) 420 421 #define NVMCTRL_FUSES_HOT_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4) 422 #define NVMCTRL_FUSES_HOT_ADC_VAL_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at hot temperature */ 423 #define NVMCTRL_FUSES_HOT_ADC_VAL_Msk (_U_(0xFFF) << NVMCTRL_FUSES_HOT_ADC_VAL_Pos) 424 #define NVMCTRL_FUSES_HOT_ADC_VAL(value) (NVMCTRL_FUSES_HOT_ADC_VAL_Msk & ((value) << NVMCTRL_FUSES_HOT_ADC_VAL_Pos)) 425 426 #define NVMCTRL_FUSES_HOT_INT1V_VAL_ADDR (NVMCTRL_TEMP_LOG + 4) 427 #define NVMCTRL_FUSES_HOT_INT1V_VAL_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value) */ 428 #define NVMCTRL_FUSES_HOT_INT1V_VAL_Msk (_U_(0xFF) << NVMCTRL_FUSES_HOT_INT1V_VAL_Pos) 429 #define NVMCTRL_FUSES_HOT_INT1V_VAL(value) (NVMCTRL_FUSES_HOT_INT1V_VAL_Msk & ((value) << NVMCTRL_FUSES_HOT_INT1V_VAL_Pos)) 430 431 #define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG 432 #define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos 20 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of hot temperature */ 433 #define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Msk (_U_(0xF) << NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos) 434 #define NVMCTRL_FUSES_HOT_TEMP_VAL_DEC(value) (NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Msk & ((value) << NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos)) 435 436 #define NVMCTRL_FUSES_HOT_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG 437 #define NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos 12 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of hot temperature in oC */ 438 #define NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Msk (_U_(0xFF) << NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos) 439 #define NVMCTRL_FUSES_HOT_TEMP_VAL_INT(value) (NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Msk & ((value) << NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos)) 440 441 #define NVMCTRL_FUSES_REGION_LOCKS_ADDR (NVMCTRL_USER + 4) 442 #define NVMCTRL_FUSES_REGION_LOCKS_Pos 16 /**< \brief (NVMCTRL_USER) NVM Region Locks */ 443 #define NVMCTRL_FUSES_REGION_LOCKS_Msk (_U_(0xFFFF) << NVMCTRL_FUSES_REGION_LOCKS_Pos) 444 #define NVMCTRL_FUSES_REGION_LOCKS(value) (NVMCTRL_FUSES_REGION_LOCKS_Msk & ((value) << NVMCTRL_FUSES_REGION_LOCKS_Pos)) 445 446 #define NVMCTRL_FUSES_ROOM_ADC_VAL_ADDR (NVMCTRL_TEMP_LOG + 4) 447 #define NVMCTRL_FUSES_ROOM_ADC_VAL_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) 12-bit ADC conversion at room temperature */ 448 #define NVMCTRL_FUSES_ROOM_ADC_VAL_Msk (_U_(0xFFF) << NVMCTRL_FUSES_ROOM_ADC_VAL_Pos) 449 #define NVMCTRL_FUSES_ROOM_ADC_VAL(value) (NVMCTRL_FUSES_ROOM_ADC_VAL_Msk & ((value) << NVMCTRL_FUSES_ROOM_ADC_VAL_Pos)) 450 451 #define NVMCTRL_FUSES_ROOM_INT1V_VAL_ADDR NVMCTRL_TEMP_LOG 452 #define NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos 24 /**< \brief (NVMCTRL_TEMP_LOG) 2's complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value) */ 453 #define NVMCTRL_FUSES_ROOM_INT1V_VAL_Msk (_U_(0xFF) << NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos) 454 #define NVMCTRL_FUSES_ROOM_INT1V_VAL(value) (NVMCTRL_FUSES_ROOM_INT1V_VAL_Msk & ((value) << NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos)) 455 456 #define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_ADDR NVMCTRL_TEMP_LOG 457 #define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos 8 /**< \brief (NVMCTRL_TEMP_LOG) Decimal part of room temperature */ 458 #define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Msk (_U_(0xF) << NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos) 459 #define NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC(value) (NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Msk & ((value) << NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos)) 460 461 #define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_ADDR NVMCTRL_TEMP_LOG 462 #define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) Integer part of room temperature in oC */ 463 #define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Msk (_U_(0xFF) << NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos) 464 #define NVMCTRL_FUSES_ROOM_TEMP_VAL_INT(value) (NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Msk & ((value) << NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos)) 465 466 #define WDT_FUSES_ALWAYSON_ADDR NVMCTRL_USER 467 #define WDT_FUSES_ALWAYSON_Pos 26 /**< \brief (NVMCTRL_USER) WDT Always On */ 468 #define WDT_FUSES_ALWAYSON_Msk (_U_(0x1) << WDT_FUSES_ALWAYSON_Pos) 469 470 #define WDT_FUSES_ENABLE_ADDR NVMCTRL_USER 471 #define WDT_FUSES_ENABLE_Pos 25 /**< \brief (NVMCTRL_USER) WDT Enable */ 472 #define WDT_FUSES_ENABLE_Msk (_U_(0x1) << WDT_FUSES_ENABLE_Pos) 473 474 #define WDT_FUSES_EWOFFSET_ADDR (NVMCTRL_USER + 4) 475 #define WDT_FUSES_EWOFFSET_Pos 3 /**< \brief (NVMCTRL_USER) WDT Early Warning Offset */ 476 #define WDT_FUSES_EWOFFSET_Msk (_U_(0xF) << WDT_FUSES_EWOFFSET_Pos) 477 #define WDT_FUSES_EWOFFSET(value) (WDT_FUSES_EWOFFSET_Msk & ((value) << WDT_FUSES_EWOFFSET_Pos)) 478 479 #define WDT_FUSES_PER_ADDR NVMCTRL_USER 480 #define WDT_FUSES_PER_Pos 27 /**< \brief (NVMCTRL_USER) WDT Period */ 481 #define WDT_FUSES_PER_Msk (_U_(0xF) << WDT_FUSES_PER_Pos) 482 #define WDT_FUSES_PER(value) (WDT_FUSES_PER_Msk & ((value) << WDT_FUSES_PER_Pos)) 483 484 #define WDT_FUSES_WEN_ADDR (NVMCTRL_USER + 4) 485 #define WDT_FUSES_WEN_Pos 7 /**< \brief (NVMCTRL_USER) WDT Window Mode Enable */ 486 #define WDT_FUSES_WEN_Msk (_U_(0x1) << WDT_FUSES_WEN_Pos) 487 488 #define WDT_FUSES_WINDOW_0_ADDR NVMCTRL_USER 489 #define WDT_FUSES_WINDOW_0_Pos 31 /**< \brief (NVMCTRL_USER) WDT Window bit 0 */ 490 #define WDT_FUSES_WINDOW_0_Msk (_U_(0x1) << WDT_FUSES_WINDOW_0_Pos) 491 492 #define WDT_FUSES_WINDOW_1_ADDR (NVMCTRL_USER + 4) 493 #define WDT_FUSES_WINDOW_1_Pos 0 /**< \brief (NVMCTRL_USER) WDT Window bits 3:1 */ 494 #define WDT_FUSES_WINDOW_1_Msk (_U_(0x7) << WDT_FUSES_WINDOW_1_Pos) 495 #define WDT_FUSES_WINDOW_1(value) (WDT_FUSES_WINDOW_1_Msk & ((value) << WDT_FUSES_WINDOW_1_Pos)) 496 497 /*@}*/ 498 499 #endif /* _SAMD20_NVMCTRL_COMPONENT_ */ 500
