1 /** 2 * \file 3 * 4 * \brief Component description for EVSYS 5 * 6 * Copyright (c) 2017 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMD20_EVSYS_COMPONENT_ 31 #define _SAMD20_EVSYS_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR EVSYS */ 35 /* ========================================================================== */ 36 /** \addtogroup SAMD20_EVSYS Event System Interface */ 37 /*@{*/ 38 39 #define EVSYS_U2208 40 #define REV_EVSYS 0x101 41 42 /* -------- EVSYS_CTRL : (EVSYS Offset: 0x00) ( /W 8) Control -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint8_t SWRST:1; /*!< bit: 0 Software Reset */ 47 uint8_t :3; /*!< bit: 1.. 3 Reserved */ 48 uint8_t GCLKREQ:1; /*!< bit: 4 Generic Clock Requests */ 49 uint8_t :3; /*!< bit: 5.. 7 Reserved */ 50 } bit; /*!< Structure used for bit access */ 51 uint8_t reg; /*!< Type used for register access */ 52 } EVSYS_CTRL_Type; 53 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 54 55 #define EVSYS_CTRL_OFFSET 0x00 /**< \brief (EVSYS_CTRL offset) Control */ 56 #define EVSYS_CTRL_RESETVALUE _U_(0x00) /**< \brief (EVSYS_CTRL reset_value) Control */ 57 58 #define EVSYS_CTRL_SWRST_Pos 0 /**< \brief (EVSYS_CTRL) Software Reset */ 59 #define EVSYS_CTRL_SWRST (_U_(0x1) << EVSYS_CTRL_SWRST_Pos) 60 #define EVSYS_CTRL_GCLKREQ_Pos 4 /**< \brief (EVSYS_CTRL) Generic Clock Requests */ 61 #define EVSYS_CTRL_GCLKREQ (_U_(0x1) << EVSYS_CTRL_GCLKREQ_Pos) 62 #define EVSYS_CTRL_MASK _U_(0x11) /**< \brief (EVSYS_CTRL) MASK Register */ 63 64 /* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x04) (R/W 32) Channel -------- */ 65 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 66 typedef union { 67 struct { 68 uint32_t CHANNEL:3; /*!< bit: 0.. 2 Channel Selection */ 69 uint32_t :5; /*!< bit: 3.. 7 Reserved */ 70 uint32_t SWEVT:1; /*!< bit: 8 Software Event */ 71 uint32_t :7; /*!< bit: 9..15 Reserved */ 72 uint32_t EVGEN:6; /*!< bit: 16..21 Event Generator Selection */ 73 uint32_t :2; /*!< bit: 22..23 Reserved */ 74 uint32_t PATH:2; /*!< bit: 24..25 Path Selection */ 75 uint32_t EDGSEL:2; /*!< bit: 26..27 Edge Detection Selection */ 76 uint32_t :4; /*!< bit: 28..31 Reserved */ 77 } bit; /*!< Structure used for bit access */ 78 uint32_t reg; /*!< Type used for register access */ 79 } EVSYS_CHANNEL_Type; 80 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 81 82 #define EVSYS_CHANNEL_OFFSET 0x04 /**< \brief (EVSYS_CHANNEL offset) Channel */ 83 #define EVSYS_CHANNEL_RESETVALUE _U_(0x00000000) /**< \brief (EVSYS_CHANNEL reset_value) Channel */ 84 85 #define EVSYS_CHANNEL_CHANNEL_Pos 0 /**< \brief (EVSYS_CHANNEL) Channel Selection */ 86 #define EVSYS_CHANNEL_CHANNEL_Msk (_U_(0x7) << EVSYS_CHANNEL_CHANNEL_Pos) 87 #define EVSYS_CHANNEL_CHANNEL(value) (EVSYS_CHANNEL_CHANNEL_Msk & ((value) << EVSYS_CHANNEL_CHANNEL_Pos)) 88 #define EVSYS_CHANNEL_SWEVT_Pos 8 /**< \brief (EVSYS_CHANNEL) Software Event */ 89 #define EVSYS_CHANNEL_SWEVT (_U_(0x1) << EVSYS_CHANNEL_SWEVT_Pos) 90 #define EVSYS_CHANNEL_EVGEN_Pos 16 /**< \brief (EVSYS_CHANNEL) Event Generator Selection */ 91 #define EVSYS_CHANNEL_EVGEN_Msk (_U_(0x3F) << EVSYS_CHANNEL_EVGEN_Pos) 92 #define EVSYS_CHANNEL_EVGEN(value) (EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos)) 93 #define EVSYS_CHANNEL_PATH_Pos 24 /**< \brief (EVSYS_CHANNEL) Path Selection */ 94 #define EVSYS_CHANNEL_PATH_Msk (_U_(0x3) << EVSYS_CHANNEL_PATH_Pos) 95 #define EVSYS_CHANNEL_PATH(value) (EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos)) 96 #define EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val _U_(0x0) /**< \brief (EVSYS_CHANNEL) Synchronous path */ 97 #define EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val _U_(0x1) /**< \brief (EVSYS_CHANNEL) Resynchronized path */ 98 #define EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val _U_(0x2) /**< \brief (EVSYS_CHANNEL) Asynchronous path */ 99 #define EVSYS_CHANNEL_PATH_SYNCHRONOUS (EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos) 100 #define EVSYS_CHANNEL_PATH_RESYNCHRONIZED (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos) 101 #define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos) 102 #define EVSYS_CHANNEL_EDGSEL_Pos 26 /**< \brief (EVSYS_CHANNEL) Edge Detection Selection */ 103 #define EVSYS_CHANNEL_EDGSEL_Msk (_U_(0x3) << EVSYS_CHANNEL_EDGSEL_Pos) 104 #define EVSYS_CHANNEL_EDGSEL(value) (EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos)) 105 #define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val _U_(0x0) /**< \brief (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path */ 106 #define EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val _U_(0x1) /**< \brief (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path */ 107 #define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val _U_(0x2) /**< \brief (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path */ 108 #define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val _U_(0x3) /**< \brief (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path */ 109 #define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos) 110 #define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos) 111 #define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos) 112 #define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos) 113 #define EVSYS_CHANNEL_MASK _U_(0x0F3F0107) /**< \brief (EVSYS_CHANNEL) MASK Register */ 114 115 /* -------- EVSYS_USER : (EVSYS Offset: 0x08) (R/W 16) User Multiplexer -------- */ 116 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 117 typedef union { 118 struct { 119 uint16_t USER:4; /*!< bit: 0.. 3 User Multiplexer Selection */ 120 uint16_t :4; /*!< bit: 4.. 7 Reserved */ 121 uint16_t CHANNEL:4; /*!< bit: 8..11 Channel Event Selection */ 122 uint16_t :4; /*!< bit: 12..15 Reserved */ 123 } bit; /*!< Structure used for bit access */ 124 uint16_t reg; /*!< Type used for register access */ 125 } EVSYS_USER_Type; 126 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 127 128 #define EVSYS_USER_OFFSET 0x08 /**< \brief (EVSYS_USER offset) User Multiplexer */ 129 #define EVSYS_USER_RESETVALUE _U_(0x0000) /**< \brief (EVSYS_USER reset_value) User Multiplexer */ 130 131 #define EVSYS_USER_USER_Pos 0 /**< \brief (EVSYS_USER) User Multiplexer Selection */ 132 #define EVSYS_USER_USER_Msk (_U_(0xF) << EVSYS_USER_USER_Pos) 133 #define EVSYS_USER_USER(value) (EVSYS_USER_USER_Msk & ((value) << EVSYS_USER_USER_Pos)) 134 #define EVSYS_USER_CHANNEL_Pos 8 /**< \brief (EVSYS_USER) Channel Event Selection */ 135 #define EVSYS_USER_CHANNEL_Msk (_U_(0xF) << EVSYS_USER_CHANNEL_Pos) 136 #define EVSYS_USER_CHANNEL(value) (EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos)) 137 #define EVSYS_USER_MASK _U_(0x0F0F) /**< \brief (EVSYS_USER) MASK Register */ 138 139 /* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) (R/ 32) Channel Status -------- */ 140 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 141 typedef union { 142 struct { 143 uint32_t USRRDY0:1; /*!< bit: 0 Channel 0 User Ready */ 144 uint32_t USRRDY1:1; /*!< bit: 1 Channel 1 User Ready */ 145 uint32_t USRRDY2:1; /*!< bit: 2 Channel 2 User Ready */ 146 uint32_t USRRDY3:1; /*!< bit: 3 Channel 3 User Ready */ 147 uint32_t USRRDY4:1; /*!< bit: 4 Channel 4 User Ready */ 148 uint32_t USRRDY5:1; /*!< bit: 5 Channel 5 User Ready */ 149 uint32_t USRRDY6:1; /*!< bit: 6 Channel 6 User Ready */ 150 uint32_t USRRDY7:1; /*!< bit: 7 Channel 7 User Ready */ 151 uint32_t CHBUSY0:1; /*!< bit: 8 Channel 0 Busy */ 152 uint32_t CHBUSY1:1; /*!< bit: 9 Channel 1 Busy */ 153 uint32_t CHBUSY2:1; /*!< bit: 10 Channel 2 Busy */ 154 uint32_t CHBUSY3:1; /*!< bit: 11 Channel 3 Busy */ 155 uint32_t CHBUSY4:1; /*!< bit: 12 Channel 4 Busy */ 156 uint32_t CHBUSY5:1; /*!< bit: 13 Channel 5 Busy */ 157 uint32_t CHBUSY6:1; /*!< bit: 14 Channel 6 Busy */ 158 uint32_t CHBUSY7:1; /*!< bit: 15 Channel 7 Busy */ 159 uint32_t :16; /*!< bit: 16..31 Reserved */ 160 } bit; /*!< Structure used for bit access */ 161 struct { 162 uint32_t USRRDY:8; /*!< bit: 0.. 7 Channel x User Ready */ 163 uint32_t CHBUSY:8; /*!< bit: 8..15 Channel x Busy */ 164 uint32_t :16; /*!< bit: 16..31 Reserved */ 165 } vec; /*!< Structure used for vec access */ 166 uint32_t reg; /*!< Type used for register access */ 167 } EVSYS_CHSTATUS_Type; 168 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 169 170 #define EVSYS_CHSTATUS_OFFSET 0x0C /**< \brief (EVSYS_CHSTATUS offset) Channel Status */ 171 #define EVSYS_CHSTATUS_RESETVALUE _U_(0x00000000) /**< \brief (EVSYS_CHSTATUS reset_value) Channel Status */ 172 173 #define EVSYS_CHSTATUS_USRRDY0_Pos 0 /**< \brief (EVSYS_CHSTATUS) Channel 0 User Ready */ 174 #define EVSYS_CHSTATUS_USRRDY0 (_U_(1) << EVSYS_CHSTATUS_USRRDY0_Pos) 175 #define EVSYS_CHSTATUS_USRRDY1_Pos 1 /**< \brief (EVSYS_CHSTATUS) Channel 1 User Ready */ 176 #define EVSYS_CHSTATUS_USRRDY1 (_U_(1) << EVSYS_CHSTATUS_USRRDY1_Pos) 177 #define EVSYS_CHSTATUS_USRRDY2_Pos 2 /**< \brief (EVSYS_CHSTATUS) Channel 2 User Ready */ 178 #define EVSYS_CHSTATUS_USRRDY2 (_U_(1) << EVSYS_CHSTATUS_USRRDY2_Pos) 179 #define EVSYS_CHSTATUS_USRRDY3_Pos 3 /**< \brief (EVSYS_CHSTATUS) Channel 3 User Ready */ 180 #define EVSYS_CHSTATUS_USRRDY3 (_U_(1) << EVSYS_CHSTATUS_USRRDY3_Pos) 181 #define EVSYS_CHSTATUS_USRRDY4_Pos 4 /**< \brief (EVSYS_CHSTATUS) Channel 4 User Ready */ 182 #define EVSYS_CHSTATUS_USRRDY4 (_U_(1) << EVSYS_CHSTATUS_USRRDY4_Pos) 183 #define EVSYS_CHSTATUS_USRRDY5_Pos 5 /**< \brief (EVSYS_CHSTATUS) Channel 5 User Ready */ 184 #define EVSYS_CHSTATUS_USRRDY5 (_U_(1) << EVSYS_CHSTATUS_USRRDY5_Pos) 185 #define EVSYS_CHSTATUS_USRRDY6_Pos 6 /**< \brief (EVSYS_CHSTATUS) Channel 6 User Ready */ 186 #define EVSYS_CHSTATUS_USRRDY6 (_U_(1) << EVSYS_CHSTATUS_USRRDY6_Pos) 187 #define EVSYS_CHSTATUS_USRRDY7_Pos 7 /**< \brief (EVSYS_CHSTATUS) Channel 7 User Ready */ 188 #define EVSYS_CHSTATUS_USRRDY7 (_U_(1) << EVSYS_CHSTATUS_USRRDY7_Pos) 189 #define EVSYS_CHSTATUS_USRRDY_Pos 0 /**< \brief (EVSYS_CHSTATUS) Channel x User Ready */ 190 #define EVSYS_CHSTATUS_USRRDY_Msk (_U_(0xFF) << EVSYS_CHSTATUS_USRRDY_Pos) 191 #define EVSYS_CHSTATUS_USRRDY(value) (EVSYS_CHSTATUS_USRRDY_Msk & ((value) << EVSYS_CHSTATUS_USRRDY_Pos)) 192 #define EVSYS_CHSTATUS_CHBUSY0_Pos 8 /**< \brief (EVSYS_CHSTATUS) Channel 0 Busy */ 193 #define EVSYS_CHSTATUS_CHBUSY0 (_U_(1) << EVSYS_CHSTATUS_CHBUSY0_Pos) 194 #define EVSYS_CHSTATUS_CHBUSY1_Pos 9 /**< \brief (EVSYS_CHSTATUS) Channel 1 Busy */ 195 #define EVSYS_CHSTATUS_CHBUSY1 (_U_(1) << EVSYS_CHSTATUS_CHBUSY1_Pos) 196 #define EVSYS_CHSTATUS_CHBUSY2_Pos 10 /**< \brief (EVSYS_CHSTATUS) Channel 2 Busy */ 197 #define EVSYS_CHSTATUS_CHBUSY2 (_U_(1) << EVSYS_CHSTATUS_CHBUSY2_Pos) 198 #define EVSYS_CHSTATUS_CHBUSY3_Pos 11 /**< \brief (EVSYS_CHSTATUS) Channel 3 Busy */ 199 #define EVSYS_CHSTATUS_CHBUSY3 (_U_(1) << EVSYS_CHSTATUS_CHBUSY3_Pos) 200 #define EVSYS_CHSTATUS_CHBUSY4_Pos 12 /**< \brief (EVSYS_CHSTATUS) Channel 4 Busy */ 201 #define EVSYS_CHSTATUS_CHBUSY4 (_U_(1) << EVSYS_CHSTATUS_CHBUSY4_Pos) 202 #define EVSYS_CHSTATUS_CHBUSY5_Pos 13 /**< \brief (EVSYS_CHSTATUS) Channel 5 Busy */ 203 #define EVSYS_CHSTATUS_CHBUSY5 (_U_(1) << EVSYS_CHSTATUS_CHBUSY5_Pos) 204 #define EVSYS_CHSTATUS_CHBUSY6_Pos 14 /**< \brief (EVSYS_CHSTATUS) Channel 6 Busy */ 205 #define EVSYS_CHSTATUS_CHBUSY6 (_U_(1) << EVSYS_CHSTATUS_CHBUSY6_Pos) 206 #define EVSYS_CHSTATUS_CHBUSY7_Pos 15 /**< \brief (EVSYS_CHSTATUS) Channel 7 Busy */ 207 #define EVSYS_CHSTATUS_CHBUSY7 (_U_(1) << EVSYS_CHSTATUS_CHBUSY7_Pos) 208 #define EVSYS_CHSTATUS_CHBUSY_Pos 8 /**< \brief (EVSYS_CHSTATUS) Channel x Busy */ 209 #define EVSYS_CHSTATUS_CHBUSY_Msk (_U_(0xFF) << EVSYS_CHSTATUS_CHBUSY_Pos) 210 #define EVSYS_CHSTATUS_CHBUSY(value) (EVSYS_CHSTATUS_CHBUSY_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY_Pos)) 211 #define EVSYS_CHSTATUS_MASK _U_(0x0000FFFF) /**< \brief (EVSYS_CHSTATUS) MASK Register */ 212 213 /* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */ 214 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 215 typedef union { 216 struct { 217 uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */ 218 uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */ 219 uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */ 220 uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */ 221 uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */ 222 uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */ 223 uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */ 224 uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */ 225 uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */ 226 uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */ 227 uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */ 228 uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */ 229 uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */ 230 uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */ 231 uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */ 232 uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */ 233 uint32_t :16; /*!< bit: 16..31 Reserved */ 234 } bit; /*!< Structure used for bit access */ 235 struct { 236 uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */ 237 uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */ 238 uint32_t :16; /*!< bit: 16..31 Reserved */ 239 } vec; /*!< Structure used for vec access */ 240 uint32_t reg; /*!< Type used for register access */ 241 } EVSYS_INTENCLR_Type; 242 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 243 244 #define EVSYS_INTENCLR_OFFSET 0x10 /**< \brief (EVSYS_INTENCLR offset) Interrupt Enable Clear */ 245 #define EVSYS_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (EVSYS_INTENCLR reset_value) Interrupt Enable Clear */ 246 247 #define EVSYS_INTENCLR_OVR0_Pos 0 /**< \brief (EVSYS_INTENCLR) Channel 0 Overrun Interrupt Enable */ 248 #define EVSYS_INTENCLR_OVR0 (_U_(1) << EVSYS_INTENCLR_OVR0_Pos) 249 #define EVSYS_INTENCLR_OVR1_Pos 1 /**< \brief (EVSYS_INTENCLR) Channel 1 Overrun Interrupt Enable */ 250 #define EVSYS_INTENCLR_OVR1 (_U_(1) << EVSYS_INTENCLR_OVR1_Pos) 251 #define EVSYS_INTENCLR_OVR2_Pos 2 /**< \brief (EVSYS_INTENCLR) Channel 2 Overrun Interrupt Enable */ 252 #define EVSYS_INTENCLR_OVR2 (_U_(1) << EVSYS_INTENCLR_OVR2_Pos) 253 #define EVSYS_INTENCLR_OVR3_Pos 3 /**< \brief (EVSYS_INTENCLR) Channel 3 Overrun Interrupt Enable */ 254 #define EVSYS_INTENCLR_OVR3 (_U_(1) << EVSYS_INTENCLR_OVR3_Pos) 255 #define EVSYS_INTENCLR_OVR4_Pos 4 /**< \brief (EVSYS_INTENCLR) Channel 4 Overrun Interrupt Enable */ 256 #define EVSYS_INTENCLR_OVR4 (_U_(1) << EVSYS_INTENCLR_OVR4_Pos) 257 #define EVSYS_INTENCLR_OVR5_Pos 5 /**< \brief (EVSYS_INTENCLR) Channel 5 Overrun Interrupt Enable */ 258 #define EVSYS_INTENCLR_OVR5 (_U_(1) << EVSYS_INTENCLR_OVR5_Pos) 259 #define EVSYS_INTENCLR_OVR6_Pos 6 /**< \brief (EVSYS_INTENCLR) Channel 6 Overrun Interrupt Enable */ 260 #define EVSYS_INTENCLR_OVR6 (_U_(1) << EVSYS_INTENCLR_OVR6_Pos) 261 #define EVSYS_INTENCLR_OVR7_Pos 7 /**< \brief (EVSYS_INTENCLR) Channel 7 Overrun Interrupt Enable */ 262 #define EVSYS_INTENCLR_OVR7 (_U_(1) << EVSYS_INTENCLR_OVR7_Pos) 263 #define EVSYS_INTENCLR_OVR_Pos 0 /**< \brief (EVSYS_INTENCLR) Channel x Overrun Interrupt Enable */ 264 #define EVSYS_INTENCLR_OVR_Msk (_U_(0xFF) << EVSYS_INTENCLR_OVR_Pos) 265 #define EVSYS_INTENCLR_OVR(value) (EVSYS_INTENCLR_OVR_Msk & ((value) << EVSYS_INTENCLR_OVR_Pos)) 266 #define EVSYS_INTENCLR_EVD0_Pos 8 /**< \brief (EVSYS_INTENCLR) Channel 0 Event Detection Interrupt Enable */ 267 #define EVSYS_INTENCLR_EVD0 (_U_(1) << EVSYS_INTENCLR_EVD0_Pos) 268 #define EVSYS_INTENCLR_EVD1_Pos 9 /**< \brief (EVSYS_INTENCLR) Channel 1 Event Detection Interrupt Enable */ 269 #define EVSYS_INTENCLR_EVD1 (_U_(1) << EVSYS_INTENCLR_EVD1_Pos) 270 #define EVSYS_INTENCLR_EVD2_Pos 10 /**< \brief (EVSYS_INTENCLR) Channel 2 Event Detection Interrupt Enable */ 271 #define EVSYS_INTENCLR_EVD2 (_U_(1) << EVSYS_INTENCLR_EVD2_Pos) 272 #define EVSYS_INTENCLR_EVD3_Pos 11 /**< \brief (EVSYS_INTENCLR) Channel 3 Event Detection Interrupt Enable */ 273 #define EVSYS_INTENCLR_EVD3 (_U_(1) << EVSYS_INTENCLR_EVD3_Pos) 274 #define EVSYS_INTENCLR_EVD4_Pos 12 /**< \brief (EVSYS_INTENCLR) Channel 4 Event Detection Interrupt Enable */ 275 #define EVSYS_INTENCLR_EVD4 (_U_(1) << EVSYS_INTENCLR_EVD4_Pos) 276 #define EVSYS_INTENCLR_EVD5_Pos 13 /**< \brief (EVSYS_INTENCLR) Channel 5 Event Detection Interrupt Enable */ 277 #define EVSYS_INTENCLR_EVD5 (_U_(1) << EVSYS_INTENCLR_EVD5_Pos) 278 #define EVSYS_INTENCLR_EVD6_Pos 14 /**< \brief (EVSYS_INTENCLR) Channel 6 Event Detection Interrupt Enable */ 279 #define EVSYS_INTENCLR_EVD6 (_U_(1) << EVSYS_INTENCLR_EVD6_Pos) 280 #define EVSYS_INTENCLR_EVD7_Pos 15 /**< \brief (EVSYS_INTENCLR) Channel 7 Event Detection Interrupt Enable */ 281 #define EVSYS_INTENCLR_EVD7 (_U_(1) << EVSYS_INTENCLR_EVD7_Pos) 282 #define EVSYS_INTENCLR_EVD_Pos 8 /**< \brief (EVSYS_INTENCLR) Channel x Event Detection Interrupt Enable */ 283 #define EVSYS_INTENCLR_EVD_Msk (_U_(0xFF) << EVSYS_INTENCLR_EVD_Pos) 284 #define EVSYS_INTENCLR_EVD(value) (EVSYS_INTENCLR_EVD_Msk & ((value) << EVSYS_INTENCLR_EVD_Pos)) 285 #define EVSYS_INTENCLR_MASK _U_(0x0000FFFF) /**< \brief (EVSYS_INTENCLR) MASK Register */ 286 287 /* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */ 288 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 289 typedef union { 290 struct { 291 uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */ 292 uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */ 293 uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */ 294 uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */ 295 uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */ 296 uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */ 297 uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */ 298 uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */ 299 uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */ 300 uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */ 301 uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */ 302 uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */ 303 uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */ 304 uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */ 305 uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */ 306 uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */ 307 uint32_t :16; /*!< bit: 16..31 Reserved */ 308 } bit; /*!< Structure used for bit access */ 309 struct { 310 uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */ 311 uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */ 312 uint32_t :16; /*!< bit: 16..31 Reserved */ 313 } vec; /*!< Structure used for vec access */ 314 uint32_t reg; /*!< Type used for register access */ 315 } EVSYS_INTENSET_Type; 316 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 317 318 #define EVSYS_INTENSET_OFFSET 0x14 /**< \brief (EVSYS_INTENSET offset) Interrupt Enable Set */ 319 #define EVSYS_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (EVSYS_INTENSET reset_value) Interrupt Enable Set */ 320 321 #define EVSYS_INTENSET_OVR0_Pos 0 /**< \brief (EVSYS_INTENSET) Channel 0 Overrun Interrupt Enable */ 322 #define EVSYS_INTENSET_OVR0 (_U_(1) << EVSYS_INTENSET_OVR0_Pos) 323 #define EVSYS_INTENSET_OVR1_Pos 1 /**< \brief (EVSYS_INTENSET) Channel 1 Overrun Interrupt Enable */ 324 #define EVSYS_INTENSET_OVR1 (_U_(1) << EVSYS_INTENSET_OVR1_Pos) 325 #define EVSYS_INTENSET_OVR2_Pos 2 /**< \brief (EVSYS_INTENSET) Channel 2 Overrun Interrupt Enable */ 326 #define EVSYS_INTENSET_OVR2 (_U_(1) << EVSYS_INTENSET_OVR2_Pos) 327 #define EVSYS_INTENSET_OVR3_Pos 3 /**< \brief (EVSYS_INTENSET) Channel 3 Overrun Interrupt Enable */ 328 #define EVSYS_INTENSET_OVR3 (_U_(1) << EVSYS_INTENSET_OVR3_Pos) 329 #define EVSYS_INTENSET_OVR4_Pos 4 /**< \brief (EVSYS_INTENSET) Channel 4 Overrun Interrupt Enable */ 330 #define EVSYS_INTENSET_OVR4 (_U_(1) << EVSYS_INTENSET_OVR4_Pos) 331 #define EVSYS_INTENSET_OVR5_Pos 5 /**< \brief (EVSYS_INTENSET) Channel 5 Overrun Interrupt Enable */ 332 #define EVSYS_INTENSET_OVR5 (_U_(1) << EVSYS_INTENSET_OVR5_Pos) 333 #define EVSYS_INTENSET_OVR6_Pos 6 /**< \brief (EVSYS_INTENSET) Channel 6 Overrun Interrupt Enable */ 334 #define EVSYS_INTENSET_OVR6 (_U_(1) << EVSYS_INTENSET_OVR6_Pos) 335 #define EVSYS_INTENSET_OVR7_Pos 7 /**< \brief (EVSYS_INTENSET) Channel 7 Overrun Interrupt Enable */ 336 #define EVSYS_INTENSET_OVR7 (_U_(1) << EVSYS_INTENSET_OVR7_Pos) 337 #define EVSYS_INTENSET_OVR_Pos 0 /**< \brief (EVSYS_INTENSET) Channel x Overrun Interrupt Enable */ 338 #define EVSYS_INTENSET_OVR_Msk (_U_(0xFF) << EVSYS_INTENSET_OVR_Pos) 339 #define EVSYS_INTENSET_OVR(value) (EVSYS_INTENSET_OVR_Msk & ((value) << EVSYS_INTENSET_OVR_Pos)) 340 #define EVSYS_INTENSET_EVD0_Pos 8 /**< \brief (EVSYS_INTENSET) Channel 0 Event Detection Interrupt Enable */ 341 #define EVSYS_INTENSET_EVD0 (_U_(1) << EVSYS_INTENSET_EVD0_Pos) 342 #define EVSYS_INTENSET_EVD1_Pos 9 /**< \brief (EVSYS_INTENSET) Channel 1 Event Detection Interrupt Enable */ 343 #define EVSYS_INTENSET_EVD1 (_U_(1) << EVSYS_INTENSET_EVD1_Pos) 344 #define EVSYS_INTENSET_EVD2_Pos 10 /**< \brief (EVSYS_INTENSET) Channel 2 Event Detection Interrupt Enable */ 345 #define EVSYS_INTENSET_EVD2 (_U_(1) << EVSYS_INTENSET_EVD2_Pos) 346 #define EVSYS_INTENSET_EVD3_Pos 11 /**< \brief (EVSYS_INTENSET) Channel 3 Event Detection Interrupt Enable */ 347 #define EVSYS_INTENSET_EVD3 (_U_(1) << EVSYS_INTENSET_EVD3_Pos) 348 #define EVSYS_INTENSET_EVD4_Pos 12 /**< \brief (EVSYS_INTENSET) Channel 4 Event Detection Interrupt Enable */ 349 #define EVSYS_INTENSET_EVD4 (_U_(1) << EVSYS_INTENSET_EVD4_Pos) 350 #define EVSYS_INTENSET_EVD5_Pos 13 /**< \brief (EVSYS_INTENSET) Channel 5 Event Detection Interrupt Enable */ 351 #define EVSYS_INTENSET_EVD5 (_U_(1) << EVSYS_INTENSET_EVD5_Pos) 352 #define EVSYS_INTENSET_EVD6_Pos 14 /**< \brief (EVSYS_INTENSET) Channel 6 Event Detection Interrupt Enable */ 353 #define EVSYS_INTENSET_EVD6 (_U_(1) << EVSYS_INTENSET_EVD6_Pos) 354 #define EVSYS_INTENSET_EVD7_Pos 15 /**< \brief (EVSYS_INTENSET) Channel 7 Event Detection Interrupt Enable */ 355 #define EVSYS_INTENSET_EVD7 (_U_(1) << EVSYS_INTENSET_EVD7_Pos) 356 #define EVSYS_INTENSET_EVD_Pos 8 /**< \brief (EVSYS_INTENSET) Channel x Event Detection Interrupt Enable */ 357 #define EVSYS_INTENSET_EVD_Msk (_U_(0xFF) << EVSYS_INTENSET_EVD_Pos) 358 #define EVSYS_INTENSET_EVD(value) (EVSYS_INTENSET_EVD_Msk & ((value) << EVSYS_INTENSET_EVD_Pos)) 359 #define EVSYS_INTENSET_MASK _U_(0x0000FFFF) /**< \brief (EVSYS_INTENSET) MASK Register */ 360 361 /* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */ 362 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 363 typedef union { // __I to avoid read-modify-write on write-to-clear register 364 struct { 365 __I uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */ 366 __I uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */ 367 __I uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */ 368 __I uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */ 369 __I uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */ 370 __I uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */ 371 __I uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */ 372 __I uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */ 373 __I uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection */ 374 __I uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection */ 375 __I uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection */ 376 __I uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection */ 377 __I uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection */ 378 __I uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection */ 379 __I uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection */ 380 __I uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection */ 381 __I uint32_t :16; /*!< bit: 16..31 Reserved */ 382 } bit; /*!< Structure used for bit access */ 383 struct { 384 __I uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun */ 385 __I uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection */ 386 __I uint32_t :16; /*!< bit: 16..31 Reserved */ 387 } vec; /*!< Structure used for vec access */ 388 uint32_t reg; /*!< Type used for register access */ 389 } EVSYS_INTFLAG_Type; 390 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 391 392 #define EVSYS_INTFLAG_OFFSET 0x18 /**< \brief (EVSYS_INTFLAG offset) Interrupt Flag Status and Clear */ 393 #define EVSYS_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (EVSYS_INTFLAG reset_value) Interrupt Flag Status and Clear */ 394 395 #define EVSYS_INTFLAG_OVR0_Pos 0 /**< \brief (EVSYS_INTFLAG) Channel 0 Overrun */ 396 #define EVSYS_INTFLAG_OVR0 (_U_(1) << EVSYS_INTFLAG_OVR0_Pos) 397 #define EVSYS_INTFLAG_OVR1_Pos 1 /**< \brief (EVSYS_INTFLAG) Channel 1 Overrun */ 398 #define EVSYS_INTFLAG_OVR1 (_U_(1) << EVSYS_INTFLAG_OVR1_Pos) 399 #define EVSYS_INTFLAG_OVR2_Pos 2 /**< \brief (EVSYS_INTFLAG) Channel 2 Overrun */ 400 #define EVSYS_INTFLAG_OVR2 (_U_(1) << EVSYS_INTFLAG_OVR2_Pos) 401 #define EVSYS_INTFLAG_OVR3_Pos 3 /**< \brief (EVSYS_INTFLAG) Channel 3 Overrun */ 402 #define EVSYS_INTFLAG_OVR3 (_U_(1) << EVSYS_INTFLAG_OVR3_Pos) 403 #define EVSYS_INTFLAG_OVR4_Pos 4 /**< \brief (EVSYS_INTFLAG) Channel 4 Overrun */ 404 #define EVSYS_INTFLAG_OVR4 (_U_(1) << EVSYS_INTFLAG_OVR4_Pos) 405 #define EVSYS_INTFLAG_OVR5_Pos 5 /**< \brief (EVSYS_INTFLAG) Channel 5 Overrun */ 406 #define EVSYS_INTFLAG_OVR5 (_U_(1) << EVSYS_INTFLAG_OVR5_Pos) 407 #define EVSYS_INTFLAG_OVR6_Pos 6 /**< \brief (EVSYS_INTFLAG) Channel 6 Overrun */ 408 #define EVSYS_INTFLAG_OVR6 (_U_(1) << EVSYS_INTFLAG_OVR6_Pos) 409 #define EVSYS_INTFLAG_OVR7_Pos 7 /**< \brief (EVSYS_INTFLAG) Channel 7 Overrun */ 410 #define EVSYS_INTFLAG_OVR7 (_U_(1) << EVSYS_INTFLAG_OVR7_Pos) 411 #define EVSYS_INTFLAG_OVR_Pos 0 /**< \brief (EVSYS_INTFLAG) Channel x Overrun */ 412 #define EVSYS_INTFLAG_OVR_Msk (_U_(0xFF) << EVSYS_INTFLAG_OVR_Pos) 413 #define EVSYS_INTFLAG_OVR(value) (EVSYS_INTFLAG_OVR_Msk & ((value) << EVSYS_INTFLAG_OVR_Pos)) 414 #define EVSYS_INTFLAG_EVD0_Pos 8 /**< \brief (EVSYS_INTFLAG) Channel 0 Event Detection */ 415 #define EVSYS_INTFLAG_EVD0 (_U_(1) << EVSYS_INTFLAG_EVD0_Pos) 416 #define EVSYS_INTFLAG_EVD1_Pos 9 /**< \brief (EVSYS_INTFLAG) Channel 1 Event Detection */ 417 #define EVSYS_INTFLAG_EVD1 (_U_(1) << EVSYS_INTFLAG_EVD1_Pos) 418 #define EVSYS_INTFLAG_EVD2_Pos 10 /**< \brief (EVSYS_INTFLAG) Channel 2 Event Detection */ 419 #define EVSYS_INTFLAG_EVD2 (_U_(1) << EVSYS_INTFLAG_EVD2_Pos) 420 #define EVSYS_INTFLAG_EVD3_Pos 11 /**< \brief (EVSYS_INTFLAG) Channel 3 Event Detection */ 421 #define EVSYS_INTFLAG_EVD3 (_U_(1) << EVSYS_INTFLAG_EVD3_Pos) 422 #define EVSYS_INTFLAG_EVD4_Pos 12 /**< \brief (EVSYS_INTFLAG) Channel 4 Event Detection */ 423 #define EVSYS_INTFLAG_EVD4 (_U_(1) << EVSYS_INTFLAG_EVD4_Pos) 424 #define EVSYS_INTFLAG_EVD5_Pos 13 /**< \brief (EVSYS_INTFLAG) Channel 5 Event Detection */ 425 #define EVSYS_INTFLAG_EVD5 (_U_(1) << EVSYS_INTFLAG_EVD5_Pos) 426 #define EVSYS_INTFLAG_EVD6_Pos 14 /**< \brief (EVSYS_INTFLAG) Channel 6 Event Detection */ 427 #define EVSYS_INTFLAG_EVD6 (_U_(1) << EVSYS_INTFLAG_EVD6_Pos) 428 #define EVSYS_INTFLAG_EVD7_Pos 15 /**< \brief (EVSYS_INTFLAG) Channel 7 Event Detection */ 429 #define EVSYS_INTFLAG_EVD7 (_U_(1) << EVSYS_INTFLAG_EVD7_Pos) 430 #define EVSYS_INTFLAG_EVD_Pos 8 /**< \brief (EVSYS_INTFLAG) Channel x Event Detection */ 431 #define EVSYS_INTFLAG_EVD_Msk (_U_(0xFF) << EVSYS_INTFLAG_EVD_Pos) 432 #define EVSYS_INTFLAG_EVD(value) (EVSYS_INTFLAG_EVD_Msk & ((value) << EVSYS_INTFLAG_EVD_Pos)) 433 #define EVSYS_INTFLAG_MASK _U_(0x0000FFFF) /**< \brief (EVSYS_INTFLAG) MASK Register */ 434 435 /** \brief EVSYS hardware registers */ 436 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 437 typedef struct { 438 __O EVSYS_CTRL_Type CTRL; /**< \brief Offset: 0x00 ( /W 8) Control */ 439 RoReg8 Reserved1[0x3]; 440 __IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x04 (R/W 32) Channel */ 441 __IO EVSYS_USER_Type USER; /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */ 442 RoReg8 Reserved2[0x2]; 443 __I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0C (R/ 32) Channel Status */ 444 __IO EVSYS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */ 445 __IO EVSYS_INTENSET_Type INTENSET; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */ 446 __IO EVSYS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */ 447 } Evsys; 448 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 449 450 /*@}*/ 451 452 #endif /* _SAMD20_EVSYS_COMPONENT_ */ 453
