1 /** 2 * \file 3 * 4 * \brief Component description for MCLK 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMC21_MCLK_COMPONENT_ 31 #define _SAMC21_MCLK_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR MCLK */ 35 /* ========================================================================== */ 36 /** \addtogroup SAMC21_MCLK Main Clock */ 37 /*@{*/ 38 39 #define MCLK_U2234 40 #define REV_MCLK 0x200 41 42 /* -------- MCLK_INTENCLR : (MCLK Offset: 0x01) (R/W 8) Interrupt Enable Clear -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */ 47 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 48 } bit; /*!< Structure used for bit access */ 49 uint8_t reg; /*!< Type used for register access */ 50 } MCLK_INTENCLR_Type; 51 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 52 53 #define MCLK_INTENCLR_OFFSET 0x01 /**< \brief (MCLK_INTENCLR offset) Interrupt Enable Clear */ 54 #define MCLK_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (MCLK_INTENCLR reset_value) Interrupt Enable Clear */ 55 56 #define MCLK_INTENCLR_CKRDY_Pos 0 /**< \brief (MCLK_INTENCLR) Clock Ready Interrupt Enable */ 57 #define MCLK_INTENCLR_CKRDY (_U_(0x1) << MCLK_INTENCLR_CKRDY_Pos) 58 #define MCLK_INTENCLR_MASK _U_(0x01) /**< \brief (MCLK_INTENCLR) MASK Register */ 59 60 /* -------- MCLK_INTENSET : (MCLK Offset: 0x02) (R/W 8) Interrupt Enable Set -------- */ 61 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 62 typedef union { 63 struct { 64 uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */ 65 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 66 } bit; /*!< Structure used for bit access */ 67 uint8_t reg; /*!< Type used for register access */ 68 } MCLK_INTENSET_Type; 69 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 70 71 #define MCLK_INTENSET_OFFSET 0x02 /**< \brief (MCLK_INTENSET offset) Interrupt Enable Set */ 72 #define MCLK_INTENSET_RESETVALUE _U_(0x00) /**< \brief (MCLK_INTENSET reset_value) Interrupt Enable Set */ 73 74 #define MCLK_INTENSET_CKRDY_Pos 0 /**< \brief (MCLK_INTENSET) Clock Ready Interrupt Enable */ 75 #define MCLK_INTENSET_CKRDY (_U_(0x1) << MCLK_INTENSET_CKRDY_Pos) 76 #define MCLK_INTENSET_MASK _U_(0x01) /**< \brief (MCLK_INTENSET) MASK Register */ 77 78 /* -------- MCLK_INTFLAG : (MCLK Offset: 0x03) (R/W 8) Interrupt Flag Status and Clear -------- */ 79 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 80 typedef union { // __I to avoid read-modify-write on write-to-clear register 81 struct { 82 __I uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */ 83 __I uint8_t Reserved1:7; /*!< bit: 1.. 7 Reserved */ 84 } bit; /*!< Structure used for bit access */ 85 uint8_t reg; /*!< Type used for register access */ 86 } MCLK_INTFLAG_Type; 87 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 88 89 #define MCLK_INTFLAG_OFFSET 0x03 /**< \brief (MCLK_INTFLAG offset) Interrupt Flag Status and Clear */ 90 #define MCLK_INTFLAG_RESETVALUE _U_(0x01) /**< \brief (MCLK_INTFLAG reset_value) Interrupt Flag Status and Clear */ 91 92 #define MCLK_INTFLAG_CKRDY_Pos 0 /**< \brief (MCLK_INTFLAG) Clock Ready */ 93 #define MCLK_INTFLAG_CKRDY (_U_(0x1) << MCLK_INTFLAG_CKRDY_Pos) 94 #define MCLK_INTFLAG_MASK _U_(0x01) /**< \brief (MCLK_INTFLAG) MASK Register */ 95 96 /* -------- MCLK_CPUDIV : (MCLK Offset: 0x04) (R/W 8) CPU Clock Division -------- */ 97 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 98 typedef union { 99 struct { 100 uint8_t CPUDIV:8; /*!< bit: 0.. 7 CPU Clock Division Factor */ 101 } bit; /*!< Structure used for bit access */ 102 uint8_t reg; /*!< Type used for register access */ 103 } MCLK_CPUDIV_Type; 104 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 105 106 #define MCLK_CPUDIV_OFFSET 0x04 /**< \brief (MCLK_CPUDIV offset) CPU Clock Division */ 107 #define MCLK_CPUDIV_RESETVALUE _U_(0x01) /**< \brief (MCLK_CPUDIV reset_value) CPU Clock Division */ 108 109 #define MCLK_CPUDIV_CPUDIV_Pos 0 /**< \brief (MCLK_CPUDIV) CPU Clock Division Factor */ 110 #define MCLK_CPUDIV_CPUDIV_Msk (_U_(0xFF) << MCLK_CPUDIV_CPUDIV_Pos) 111 #define MCLK_CPUDIV_CPUDIV(value) (MCLK_CPUDIV_CPUDIV_Msk & ((value) << MCLK_CPUDIV_CPUDIV_Pos)) 112 #define MCLK_CPUDIV_CPUDIV_DIV1_Val _U_(0x1) /**< \brief (MCLK_CPUDIV) Divide by 1 */ 113 #define MCLK_CPUDIV_CPUDIV_DIV2_Val _U_(0x2) /**< \brief (MCLK_CPUDIV) Divide by 2 */ 114 #define MCLK_CPUDIV_CPUDIV_DIV4_Val _U_(0x4) /**< \brief (MCLK_CPUDIV) Divide by 4 */ 115 #define MCLK_CPUDIV_CPUDIV_DIV8_Val _U_(0x8) /**< \brief (MCLK_CPUDIV) Divide by 8 */ 116 #define MCLK_CPUDIV_CPUDIV_DIV16_Val _U_(0x10) /**< \brief (MCLK_CPUDIV) Divide by 16 */ 117 #define MCLK_CPUDIV_CPUDIV_DIV32_Val _U_(0x20) /**< \brief (MCLK_CPUDIV) Divide by 32 */ 118 #define MCLK_CPUDIV_CPUDIV_DIV64_Val _U_(0x40) /**< \brief (MCLK_CPUDIV) Divide by 64 */ 119 #define MCLK_CPUDIV_CPUDIV_DIV128_Val _U_(0x80) /**< \brief (MCLK_CPUDIV) Divide by 128 */ 120 #define MCLK_CPUDIV_CPUDIV_DIV1 (MCLK_CPUDIV_CPUDIV_DIV1_Val << MCLK_CPUDIV_CPUDIV_Pos) 121 #define MCLK_CPUDIV_CPUDIV_DIV2 (MCLK_CPUDIV_CPUDIV_DIV2_Val << MCLK_CPUDIV_CPUDIV_Pos) 122 #define MCLK_CPUDIV_CPUDIV_DIV4 (MCLK_CPUDIV_CPUDIV_DIV4_Val << MCLK_CPUDIV_CPUDIV_Pos) 123 #define MCLK_CPUDIV_CPUDIV_DIV8 (MCLK_CPUDIV_CPUDIV_DIV8_Val << MCLK_CPUDIV_CPUDIV_Pos) 124 #define MCLK_CPUDIV_CPUDIV_DIV16 (MCLK_CPUDIV_CPUDIV_DIV16_Val << MCLK_CPUDIV_CPUDIV_Pos) 125 #define MCLK_CPUDIV_CPUDIV_DIV32 (MCLK_CPUDIV_CPUDIV_DIV32_Val << MCLK_CPUDIV_CPUDIV_Pos) 126 #define MCLK_CPUDIV_CPUDIV_DIV64 (MCLK_CPUDIV_CPUDIV_DIV64_Val << MCLK_CPUDIV_CPUDIV_Pos) 127 #define MCLK_CPUDIV_CPUDIV_DIV128 (MCLK_CPUDIV_CPUDIV_DIV128_Val << MCLK_CPUDIV_CPUDIV_Pos) 128 #define MCLK_CPUDIV_MASK _U_(0xFF) /**< \brief (MCLK_CPUDIV) MASK Register */ 129 130 /* -------- MCLK_AHBMASK : (MCLK Offset: 0x10) (R/W 32) AHB Mask -------- */ 131 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 132 typedef union { 133 struct { 134 uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */ 135 uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */ 136 uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */ 137 uint32_t DSU_:1; /*!< bit: 3 DSU AHB Clock Mask */ 138 uint32_t HMATRIXHS_:1; /*!< bit: 4 HMATRIXHS AHB Clock Mask */ 139 uint32_t NVMCTRL_:1; /*!< bit: 5 NVMCTRL AHB Clock Mask */ 140 uint32_t HSRAM_:1; /*!< bit: 6 HSRAM AHB Clock Mask */ 141 uint32_t DMAC_:1; /*!< bit: 7 DMAC AHB Clock Mask */ 142 uint32_t CAN0_:1; /*!< bit: 8 CAN0 AHB Clock Mask */ 143 uint32_t CAN1_:1; /*!< bit: 9 CAN1 AHB Clock Mask */ 144 uint32_t PAC_:1; /*!< bit: 10 PAC AHB Clock Mask */ 145 uint32_t NVMCTRL_PICACHU_:1; /*!< bit: 11 NVMCTRL_PICACHU AHB Clock Mask */ 146 uint32_t DIVAS_:1; /*!< bit: 12 DIVAS AHB Clock Mask */ 147 uint32_t HPB3_:1; /*!< bit: 13 HPB3 AHB Clock Mask */ 148 uint32_t :18; /*!< bit: 14..31 Reserved */ 149 } bit; /*!< Structure used for bit access */ 150 uint32_t reg; /*!< Type used for register access */ 151 } MCLK_AHBMASK_Type; 152 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 153 154 #define MCLK_AHBMASK_OFFSET 0x10 /**< \brief (MCLK_AHBMASK offset) AHB Mask */ 155 #define MCLK_AHBMASK_RESETVALUE _U_(0x00003CFF) /**< \brief (MCLK_AHBMASK reset_value) AHB Mask */ 156 157 #define MCLK_AHBMASK_HPB0_Pos 0 /**< \brief (MCLK_AHBMASK) HPB0 AHB Clock Mask */ 158 #define MCLK_AHBMASK_HPB0 (_U_(0x1) << MCLK_AHBMASK_HPB0_Pos) 159 #define MCLK_AHBMASK_HPB1_Pos 1 /**< \brief (MCLK_AHBMASK) HPB1 AHB Clock Mask */ 160 #define MCLK_AHBMASK_HPB1 (_U_(0x1) << MCLK_AHBMASK_HPB1_Pos) 161 #define MCLK_AHBMASK_HPB2_Pos 2 /**< \brief (MCLK_AHBMASK) HPB2 AHB Clock Mask */ 162 #define MCLK_AHBMASK_HPB2 (_U_(0x1) << MCLK_AHBMASK_HPB2_Pos) 163 #define MCLK_AHBMASK_DSU_Pos 3 /**< \brief (MCLK_AHBMASK) DSU AHB Clock Mask */ 164 #define MCLK_AHBMASK_DSU (_U_(0x1) << MCLK_AHBMASK_DSU_Pos) 165 #define MCLK_AHBMASK_HMATRIXHS_Pos 4 /**< \brief (MCLK_AHBMASK) HMATRIXHS AHB Clock Mask */ 166 #define MCLK_AHBMASK_HMATRIXHS (_U_(0x1) << MCLK_AHBMASK_HMATRIXHS_Pos) 167 #define MCLK_AHBMASK_NVMCTRL_Pos 5 /**< \brief (MCLK_AHBMASK) NVMCTRL AHB Clock Mask */ 168 #define MCLK_AHBMASK_NVMCTRL (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_Pos) 169 #define MCLK_AHBMASK_HSRAM_Pos 6 /**< \brief (MCLK_AHBMASK) HSRAM AHB Clock Mask */ 170 #define MCLK_AHBMASK_HSRAM (_U_(0x1) << MCLK_AHBMASK_HSRAM_Pos) 171 #define MCLK_AHBMASK_DMAC_Pos 7 /**< \brief (MCLK_AHBMASK) DMAC AHB Clock Mask */ 172 #define MCLK_AHBMASK_DMAC (_U_(0x1) << MCLK_AHBMASK_DMAC_Pos) 173 #define MCLK_AHBMASK_CAN0_Pos 8 /**< \brief (MCLK_AHBMASK) CAN0 AHB Clock Mask */ 174 #define MCLK_AHBMASK_CAN0 (_U_(0x1) << MCLK_AHBMASK_CAN0_Pos) 175 #define MCLK_AHBMASK_CAN1_Pos 9 /**< \brief (MCLK_AHBMASK) CAN1 AHB Clock Mask */ 176 #define MCLK_AHBMASK_CAN1 (_U_(0x1) << MCLK_AHBMASK_CAN1_Pos) 177 #define MCLK_AHBMASK_PAC_Pos 10 /**< \brief (MCLK_AHBMASK) PAC AHB Clock Mask */ 178 #define MCLK_AHBMASK_PAC (_U_(0x1) << MCLK_AHBMASK_PAC_Pos) 179 #define MCLK_AHBMASK_NVMCTRL_PICACHU_Pos 11 /**< \brief (MCLK_AHBMASK) NVMCTRL_PICACHU AHB Clock Mask */ 180 #define MCLK_AHBMASK_NVMCTRL_PICACHU (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_PICACHU_Pos) 181 #define MCLK_AHBMASK_DIVAS_Pos 12 /**< \brief (MCLK_AHBMASK) DIVAS AHB Clock Mask */ 182 #define MCLK_AHBMASK_DIVAS (_U_(0x1) << MCLK_AHBMASK_DIVAS_Pos) 183 #define MCLK_AHBMASK_HPB3_Pos 13 /**< \brief (MCLK_AHBMASK) HPB3 AHB Clock Mask */ 184 #define MCLK_AHBMASK_HPB3 (_U_(0x1) << MCLK_AHBMASK_HPB3_Pos) 185 #define MCLK_AHBMASK_MASK _U_(0x00003FFF) /**< \brief (MCLK_AHBMASK) MASK Register */ 186 187 /* -------- MCLK_APBAMASK : (MCLK Offset: 0x14) (R/W 32) APBA Mask -------- */ 188 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 189 typedef union { 190 struct { 191 uint32_t PAC_:1; /*!< bit: 0 PAC APB Clock Enable */ 192 uint32_t PM_:1; /*!< bit: 1 PM APB Clock Enable */ 193 uint32_t MCLK_:1; /*!< bit: 2 MCLK APB Clock Enable */ 194 uint32_t RSTC_:1; /*!< bit: 3 RSTC APB Clock Enable */ 195 uint32_t OSCCTRL_:1; /*!< bit: 4 OSCCTRL APB Clock Enable */ 196 uint32_t OSC32KCTRL_:1; /*!< bit: 5 OSC32KCTRL APB Clock Enable */ 197 uint32_t SUPC_:1; /*!< bit: 6 SUPC APB Clock Enable */ 198 uint32_t GCLK_:1; /*!< bit: 7 GCLK APB Clock Enable */ 199 uint32_t WDT_:1; /*!< bit: 8 WDT APB Clock Enable */ 200 uint32_t RTC_:1; /*!< bit: 9 RTC APB Clock Enable */ 201 uint32_t EIC_:1; /*!< bit: 10 EIC APB Clock Enable */ 202 uint32_t FREQM_:1; /*!< bit: 11 FREQM APB Clock Enable */ 203 uint32_t TSENS_:1; /*!< bit: 12 TSENS APB Clock Enable */ 204 uint32_t :19; /*!< bit: 13..31 Reserved */ 205 } bit; /*!< Structure used for bit access */ 206 uint32_t reg; /*!< Type used for register access */ 207 } MCLK_APBAMASK_Type; 208 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 209 210 #define MCLK_APBAMASK_OFFSET 0x14 /**< \brief (MCLK_APBAMASK offset) APBA Mask */ 211 #define MCLK_APBAMASK_RESETVALUE _U_(0x00000FFF) /**< \brief (MCLK_APBAMASK reset_value) APBA Mask */ 212 213 #define MCLK_APBAMASK_PAC_Pos 0 /**< \brief (MCLK_APBAMASK) PAC APB Clock Enable */ 214 #define MCLK_APBAMASK_PAC (_U_(0x1) << MCLK_APBAMASK_PAC_Pos) 215 #define MCLK_APBAMASK_PM_Pos 1 /**< \brief (MCLK_APBAMASK) PM APB Clock Enable */ 216 #define MCLK_APBAMASK_PM (_U_(0x1) << MCLK_APBAMASK_PM_Pos) 217 #define MCLK_APBAMASK_MCLK_Pos 2 /**< \brief (MCLK_APBAMASK) MCLK APB Clock Enable */ 218 #define MCLK_APBAMASK_MCLK (_U_(0x1) << MCLK_APBAMASK_MCLK_Pos) 219 #define MCLK_APBAMASK_RSTC_Pos 3 /**< \brief (MCLK_APBAMASK) RSTC APB Clock Enable */ 220 #define MCLK_APBAMASK_RSTC (_U_(0x1) << MCLK_APBAMASK_RSTC_Pos) 221 #define MCLK_APBAMASK_OSCCTRL_Pos 4 /**< \brief (MCLK_APBAMASK) OSCCTRL APB Clock Enable */ 222 #define MCLK_APBAMASK_OSCCTRL (_U_(0x1) << MCLK_APBAMASK_OSCCTRL_Pos) 223 #define MCLK_APBAMASK_OSC32KCTRL_Pos 5 /**< \brief (MCLK_APBAMASK) OSC32KCTRL APB Clock Enable */ 224 #define MCLK_APBAMASK_OSC32KCTRL (_U_(0x1) << MCLK_APBAMASK_OSC32KCTRL_Pos) 225 #define MCLK_APBAMASK_SUPC_Pos 6 /**< \brief (MCLK_APBAMASK) SUPC APB Clock Enable */ 226 #define MCLK_APBAMASK_SUPC (_U_(0x1) << MCLK_APBAMASK_SUPC_Pos) 227 #define MCLK_APBAMASK_GCLK_Pos 7 /**< \brief (MCLK_APBAMASK) GCLK APB Clock Enable */ 228 #define MCLK_APBAMASK_GCLK (_U_(0x1) << MCLK_APBAMASK_GCLK_Pos) 229 #define MCLK_APBAMASK_WDT_Pos 8 /**< \brief (MCLK_APBAMASK) WDT APB Clock Enable */ 230 #define MCLK_APBAMASK_WDT (_U_(0x1) << MCLK_APBAMASK_WDT_Pos) 231 #define MCLK_APBAMASK_RTC_Pos 9 /**< \brief (MCLK_APBAMASK) RTC APB Clock Enable */ 232 #define MCLK_APBAMASK_RTC (_U_(0x1) << MCLK_APBAMASK_RTC_Pos) 233 #define MCLK_APBAMASK_EIC_Pos 10 /**< \brief (MCLK_APBAMASK) EIC APB Clock Enable */ 234 #define MCLK_APBAMASK_EIC (_U_(0x1) << MCLK_APBAMASK_EIC_Pos) 235 #define MCLK_APBAMASK_FREQM_Pos 11 /**< \brief (MCLK_APBAMASK) FREQM APB Clock Enable */ 236 #define MCLK_APBAMASK_FREQM (_U_(0x1) << MCLK_APBAMASK_FREQM_Pos) 237 #define MCLK_APBAMASK_TSENS_Pos 12 /**< \brief (MCLK_APBAMASK) TSENS APB Clock Enable */ 238 #define MCLK_APBAMASK_TSENS (_U_(0x1) << MCLK_APBAMASK_TSENS_Pos) 239 #define MCLK_APBAMASK_MASK _U_(0x00001FFF) /**< \brief (MCLK_APBAMASK) MASK Register */ 240 241 /* -------- MCLK_APBBMASK : (MCLK Offset: 0x18) (R/W 32) APBB Mask -------- */ 242 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 243 typedef union { 244 struct { 245 uint32_t PORT_:1; /*!< bit: 0 PORT APB Clock Enable */ 246 uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */ 247 uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */ 248 uint32_t :2; /*!< bit: 3.. 4 Reserved */ 249 uint32_t HMATRIXHS_:1; /*!< bit: 5 HMATRIXHS APB Clock Enable */ 250 uint32_t :26; /*!< bit: 6..31 Reserved */ 251 } bit; /*!< Structure used for bit access */ 252 uint32_t reg; /*!< Type used for register access */ 253 } MCLK_APBBMASK_Type; 254 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 255 256 #define MCLK_APBBMASK_OFFSET 0x18 /**< \brief (MCLK_APBBMASK offset) APBB Mask */ 257 #define MCLK_APBBMASK_RESETVALUE _U_(0x00000007) /**< \brief (MCLK_APBBMASK reset_value) APBB Mask */ 258 259 #define MCLK_APBBMASK_PORT_Pos 0 /**< \brief (MCLK_APBBMASK) PORT APB Clock Enable */ 260 #define MCLK_APBBMASK_PORT (_U_(0x1) << MCLK_APBBMASK_PORT_Pos) 261 #define MCLK_APBBMASK_DSU_Pos 1 /**< \brief (MCLK_APBBMASK) DSU APB Clock Enable */ 262 #define MCLK_APBBMASK_DSU (_U_(0x1) << MCLK_APBBMASK_DSU_Pos) 263 #define MCLK_APBBMASK_NVMCTRL_Pos 2 /**< \brief (MCLK_APBBMASK) NVMCTRL APB Clock Enable */ 264 #define MCLK_APBBMASK_NVMCTRL (_U_(0x1) << MCLK_APBBMASK_NVMCTRL_Pos) 265 #define MCLK_APBBMASK_HMATRIXHS_Pos 5 /**< \brief (MCLK_APBBMASK) HMATRIXHS APB Clock Enable */ 266 #define MCLK_APBBMASK_HMATRIXHS (_U_(0x1) << MCLK_APBBMASK_HMATRIXHS_Pos) 267 #define MCLK_APBBMASK_MASK _U_(0x00000027) /**< \brief (MCLK_APBBMASK) MASK Register */ 268 269 /* -------- MCLK_APBCMASK : (MCLK Offset: 0x1C) (R/W 32) APBC Mask -------- */ 270 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 271 typedef union { 272 struct { 273 uint32_t EVSYS_:1; /*!< bit: 0 EVSYS APB Clock Enable */ 274 uint32_t SERCOM0_:1; /*!< bit: 1 SERCOM0 APB Clock Enable */ 275 uint32_t SERCOM1_:1; /*!< bit: 2 SERCOM1 APB Clock Enable */ 276 uint32_t SERCOM2_:1; /*!< bit: 3 SERCOM2 APB Clock Enable */ 277 uint32_t SERCOM3_:1; /*!< bit: 4 SERCOM3 APB Clock Enable */ 278 uint32_t SERCOM4_:1; /*!< bit: 5 SERCOM4 APB Clock Enable */ 279 uint32_t SERCOM5_:1; /*!< bit: 6 SERCOM5 APB Clock Enable */ 280 uint32_t :2; /*!< bit: 7.. 8 Reserved */ 281 uint32_t TCC0_:1; /*!< bit: 9 TCC0 APB Clock Enable */ 282 uint32_t TCC1_:1; /*!< bit: 10 TCC1 APB Clock Enable */ 283 uint32_t TCC2_:1; /*!< bit: 11 TCC2 APB Clock Enable */ 284 uint32_t TC0_:1; /*!< bit: 12 TC0 APB Clock Enable */ 285 uint32_t TC1_:1; /*!< bit: 13 TC1 APB Clock Enable */ 286 uint32_t TC2_:1; /*!< bit: 14 TC2 APB Clock Enable */ 287 uint32_t TC3_:1; /*!< bit: 15 TC3 APB Clock Enable */ 288 uint32_t TC4_:1; /*!< bit: 16 TC4 APB Clock Enable */ 289 uint32_t ADC0_:1; /*!< bit: 17 ADC0 APB Clock Enable */ 290 uint32_t ADC1_:1; /*!< bit: 18 ADC1 APB Clock Enable */ 291 uint32_t SDADC_:1; /*!< bit: 19 SDADC APB Clock Enable */ 292 uint32_t AC_:1; /*!< bit: 20 AC APB Clock Enable */ 293 uint32_t DAC_:1; /*!< bit: 21 DAC APB Clock Enable */ 294 uint32_t PTC_:1; /*!< bit: 22 PTC APB Clock Enable */ 295 uint32_t CCL_:1; /*!< bit: 23 CCL APB Clock Enable */ 296 uint32_t :8; /*!< bit: 24..31 Reserved */ 297 } bit; /*!< Structure used for bit access */ 298 uint32_t reg; /*!< Type used for register access */ 299 } MCLK_APBCMASK_Type; 300 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 301 302 #define MCLK_APBCMASK_OFFSET 0x1C /**< \brief (MCLK_APBCMASK offset) APBC Mask */ 303 #define MCLK_APBCMASK_RESETVALUE _U_(0x00000000) /**< \brief (MCLK_APBCMASK reset_value) APBC Mask */ 304 305 #define MCLK_APBCMASK_EVSYS_Pos 0 /**< \brief (MCLK_APBCMASK) EVSYS APB Clock Enable */ 306 #define MCLK_APBCMASK_EVSYS (_U_(0x1) << MCLK_APBCMASK_EVSYS_Pos) 307 #define MCLK_APBCMASK_SERCOM0_Pos 1 /**< \brief (MCLK_APBCMASK) SERCOM0 APB Clock Enable */ 308 #define MCLK_APBCMASK_SERCOM0 (_U_(0x1) << MCLK_APBCMASK_SERCOM0_Pos) 309 #define MCLK_APBCMASK_SERCOM1_Pos 2 /**< \brief (MCLK_APBCMASK) SERCOM1 APB Clock Enable */ 310 #define MCLK_APBCMASK_SERCOM1 (_U_(0x1) << MCLK_APBCMASK_SERCOM1_Pos) 311 #define MCLK_APBCMASK_SERCOM2_Pos 3 /**< \brief (MCLK_APBCMASK) SERCOM2 APB Clock Enable */ 312 #define MCLK_APBCMASK_SERCOM2 (_U_(0x1) << MCLK_APBCMASK_SERCOM2_Pos) 313 #define MCLK_APBCMASK_SERCOM3_Pos 4 /**< \brief (MCLK_APBCMASK) SERCOM3 APB Clock Enable */ 314 #define MCLK_APBCMASK_SERCOM3 (_U_(0x1) << MCLK_APBCMASK_SERCOM3_Pos) 315 #define MCLK_APBCMASK_SERCOM4_Pos 5 /**< \brief (MCLK_APBCMASK) SERCOM4 APB Clock Enable */ 316 #define MCLK_APBCMASK_SERCOM4 (_U_(0x1) << MCLK_APBCMASK_SERCOM4_Pos) 317 #define MCLK_APBCMASK_SERCOM5_Pos 6 /**< \brief (MCLK_APBCMASK) SERCOM5 APB Clock Enable */ 318 #define MCLK_APBCMASK_SERCOM5 (_U_(0x1) << MCLK_APBCMASK_SERCOM5_Pos) 319 #define MCLK_APBCMASK_TCC0_Pos 9 /**< \brief (MCLK_APBCMASK) TCC0 APB Clock Enable */ 320 #define MCLK_APBCMASK_TCC0 (_U_(0x1) << MCLK_APBCMASK_TCC0_Pos) 321 #define MCLK_APBCMASK_TCC1_Pos 10 /**< \brief (MCLK_APBCMASK) TCC1 APB Clock Enable */ 322 #define MCLK_APBCMASK_TCC1 (_U_(0x1) << MCLK_APBCMASK_TCC1_Pos) 323 #define MCLK_APBCMASK_TCC2_Pos 11 /**< \brief (MCLK_APBCMASK) TCC2 APB Clock Enable */ 324 #define MCLK_APBCMASK_TCC2 (_U_(0x1) << MCLK_APBCMASK_TCC2_Pos) 325 #define MCLK_APBCMASK_TC0_Pos 12 /**< \brief (MCLK_APBCMASK) TC0 APB Clock Enable */ 326 #define MCLK_APBCMASK_TC0 (_U_(0x1) << MCLK_APBCMASK_TC0_Pos) 327 #define MCLK_APBCMASK_TC1_Pos 13 /**< \brief (MCLK_APBCMASK) TC1 APB Clock Enable */ 328 #define MCLK_APBCMASK_TC1 (_U_(0x1) << MCLK_APBCMASK_TC1_Pos) 329 #define MCLK_APBCMASK_TC2_Pos 14 /**< \brief (MCLK_APBCMASK) TC2 APB Clock Enable */ 330 #define MCLK_APBCMASK_TC2 (_U_(0x1) << MCLK_APBCMASK_TC2_Pos) 331 #define MCLK_APBCMASK_TC3_Pos 15 /**< \brief (MCLK_APBCMASK) TC3 APB Clock Enable */ 332 #define MCLK_APBCMASK_TC3 (_U_(0x1) << MCLK_APBCMASK_TC3_Pos) 333 #define MCLK_APBCMASK_TC4_Pos 16 /**< \brief (MCLK_APBCMASK) TC4 APB Clock Enable */ 334 #define MCLK_APBCMASK_TC4 (_U_(0x1) << MCLK_APBCMASK_TC4_Pos) 335 #define MCLK_APBCMASK_ADC0_Pos 17 /**< \brief (MCLK_APBCMASK) ADC0 APB Clock Enable */ 336 #define MCLK_APBCMASK_ADC0 (_U_(0x1) << MCLK_APBCMASK_ADC0_Pos) 337 #define MCLK_APBCMASK_ADC1_Pos 18 /**< \brief (MCLK_APBCMASK) ADC1 APB Clock Enable */ 338 #define MCLK_APBCMASK_ADC1 (_U_(0x1) << MCLK_APBCMASK_ADC1_Pos) 339 #define MCLK_APBCMASK_SDADC_Pos 19 /**< \brief (MCLK_APBCMASK) SDADC APB Clock Enable */ 340 #define MCLK_APBCMASK_SDADC (_U_(0x1) << MCLK_APBCMASK_SDADC_Pos) 341 #define MCLK_APBCMASK_AC_Pos 20 /**< \brief (MCLK_APBCMASK) AC APB Clock Enable */ 342 #define MCLK_APBCMASK_AC (_U_(0x1) << MCLK_APBCMASK_AC_Pos) 343 #define MCLK_APBCMASK_DAC_Pos 21 /**< \brief (MCLK_APBCMASK) DAC APB Clock Enable */ 344 #define MCLK_APBCMASK_DAC (_U_(0x1) << MCLK_APBCMASK_DAC_Pos) 345 #define MCLK_APBCMASK_PTC_Pos 22 /**< \brief (MCLK_APBCMASK) PTC APB Clock Enable */ 346 #define MCLK_APBCMASK_PTC (_U_(0x1) << MCLK_APBCMASK_PTC_Pos) 347 #define MCLK_APBCMASK_CCL_Pos 23 /**< \brief (MCLK_APBCMASK) CCL APB Clock Enable */ 348 #define MCLK_APBCMASK_CCL (_U_(0x1) << MCLK_APBCMASK_CCL_Pos) 349 #define MCLK_APBCMASK_MASK _U_(0x00FFFE7F) /**< \brief (MCLK_APBCMASK) MASK Register */ 350 351 /* -------- MCLK_APBDMASK : (MCLK Offset: 0x20) (R/W 32) APBD Mask -------- */ 352 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 353 typedef union { 354 struct { 355 uint32_t SERCOM6_:1; /*!< bit: 0 SERCOM6 APB Clock Enable */ 356 uint32_t SERCOM7_:1; /*!< bit: 1 SERCOM7 APB Clock Enable */ 357 uint32_t TC5_:1; /*!< bit: 2 TC5 APB Clock Enable */ 358 uint32_t TC6_:1; /*!< bit: 3 TC6 APB Clock Enable */ 359 uint32_t TC7_:1; /*!< bit: 4 TC7 APB Clock Enable */ 360 uint32_t :27; /*!< bit: 5..31 Reserved */ 361 } bit; /*!< Structure used for bit access */ 362 uint32_t reg; /*!< Type used for register access */ 363 } MCLK_APBDMASK_Type; 364 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 365 366 #define MCLK_APBDMASK_OFFSET 0x20 /**< \brief (MCLK_APBDMASK offset) APBD Mask */ 367 #define MCLK_APBDMASK_RESETVALUE _U_(0x00000000) /**< \brief (MCLK_APBDMASK reset_value) APBD Mask */ 368 369 #define MCLK_APBDMASK_SERCOM6_Pos 0 /**< \brief (MCLK_APBDMASK) SERCOM6 APB Clock Enable */ 370 #define MCLK_APBDMASK_SERCOM6 (_U_(0x1) << MCLK_APBDMASK_SERCOM6_Pos) 371 #define MCLK_APBDMASK_SERCOM7_Pos 1 /**< \brief (MCLK_APBDMASK) SERCOM7 APB Clock Enable */ 372 #define MCLK_APBDMASK_SERCOM7 (_U_(0x1) << MCLK_APBDMASK_SERCOM7_Pos) 373 #define MCLK_APBDMASK_TC5_Pos 2 /**< \brief (MCLK_APBDMASK) TC5 APB Clock Enable */ 374 #define MCLK_APBDMASK_TC5 (_U_(0x1) << MCLK_APBDMASK_TC5_Pos) 375 #define MCLK_APBDMASK_TC6_Pos 3 /**< \brief (MCLK_APBDMASK) TC6 APB Clock Enable */ 376 #define MCLK_APBDMASK_TC6 (_U_(0x1) << MCLK_APBDMASK_TC6_Pos) 377 #define MCLK_APBDMASK_TC7_Pos 4 /**< \brief (MCLK_APBDMASK) TC7 APB Clock Enable */ 378 #define MCLK_APBDMASK_TC7 (_U_(0x1) << MCLK_APBDMASK_TC7_Pos) 379 #define MCLK_APBDMASK_MASK _U_(0x0000001F) /**< \brief (MCLK_APBDMASK) MASK Register */ 380 381 /** \brief MCLK hardware registers */ 382 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 383 typedef struct { 384 RoReg8 Reserved1[0x1]; 385 __IO MCLK_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x01 (R/W 8) Interrupt Enable Clear */ 386 __IO MCLK_INTENSET_Type INTENSET; /**< \brief Offset: 0x02 (R/W 8) Interrupt Enable Set */ 387 __IO MCLK_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x03 (R/W 8) Interrupt Flag Status and Clear */ 388 __IO MCLK_CPUDIV_Type CPUDIV; /**< \brief Offset: 0x04 (R/W 8) CPU Clock Division */ 389 RoReg8 Reserved2[0xB]; 390 __IO MCLK_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x10 (R/W 32) AHB Mask */ 391 __IO MCLK_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x14 (R/W 32) APBA Mask */ 392 __IO MCLK_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x18 (R/W 32) APBB Mask */ 393 __IO MCLK_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x1C (R/W 32) APBC Mask */ 394 __IO MCLK_APBDMASK_Type APBDMASK; /**< \brief Offset: 0x20 (R/W 32) APBD Mask */ 395 } Mclk; 396 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 397 398 /*@}*/ 399 400 #endif /* _SAMC21_MCLK_COMPONENT_ */ 401
