1 /** 2 * \file 3 * 4 * \brief Component description for FREQM 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMC21_FREQM_COMPONENT_ 31 #define _SAMC21_FREQM_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR FREQM */ 35 /* ========================================================================== */ 36 /** \addtogroup SAMC21_FREQM Frequency Meter */ 37 /*@{*/ 38 39 #define FREQM_U2257 40 #define REV_FREQM 0x200 41 42 /* -------- FREQM_CTRLA : (FREQM Offset: 0x00) (R/W 8) Control A Register -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint8_t SWRST:1; /*!< bit: 0 Software Reset */ 47 uint8_t ENABLE:1; /*!< bit: 1 Enable */ 48 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 49 } bit; /*!< Structure used for bit access */ 50 uint8_t reg; /*!< Type used for register access */ 51 } FREQM_CTRLA_Type; 52 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 53 54 #define FREQM_CTRLA_OFFSET 0x00 /**< \brief (FREQM_CTRLA offset) Control A Register */ 55 #define FREQM_CTRLA_RESETVALUE _U_(0x00) /**< \brief (FREQM_CTRLA reset_value) Control A Register */ 56 57 #define FREQM_CTRLA_SWRST_Pos 0 /**< \brief (FREQM_CTRLA) Software Reset */ 58 #define FREQM_CTRLA_SWRST (_U_(0x1) << FREQM_CTRLA_SWRST_Pos) 59 #define FREQM_CTRLA_ENABLE_Pos 1 /**< \brief (FREQM_CTRLA) Enable */ 60 #define FREQM_CTRLA_ENABLE (_U_(0x1) << FREQM_CTRLA_ENABLE_Pos) 61 #define FREQM_CTRLA_MASK _U_(0x03) /**< \brief (FREQM_CTRLA) MASK Register */ 62 63 /* -------- FREQM_CTRLB : (FREQM Offset: 0x01) ( /W 8) Control B Register -------- */ 64 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 65 typedef union { 66 struct { 67 uint8_t START:1; /*!< bit: 0 Start Measurement */ 68 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 69 } bit; /*!< Structure used for bit access */ 70 uint8_t reg; /*!< Type used for register access */ 71 } FREQM_CTRLB_Type; 72 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 73 74 #define FREQM_CTRLB_OFFSET 0x01 /**< \brief (FREQM_CTRLB offset) Control B Register */ 75 #define FREQM_CTRLB_RESETVALUE _U_(0x00) /**< \brief (FREQM_CTRLB reset_value) Control B Register */ 76 77 #define FREQM_CTRLB_START_Pos 0 /**< \brief (FREQM_CTRLB) Start Measurement */ 78 #define FREQM_CTRLB_START (_U_(0x1) << FREQM_CTRLB_START_Pos) 79 #define FREQM_CTRLB_MASK _U_(0x01) /**< \brief (FREQM_CTRLB) MASK Register */ 80 81 /* -------- FREQM_CFGA : (FREQM Offset: 0x02) (R/W 16) Config A register -------- */ 82 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 83 typedef union { 84 struct { 85 uint16_t REFNUM:8; /*!< bit: 0.. 7 Number of Reference Clock Cycles */ 86 uint16_t :7; /*!< bit: 8..14 Reserved */ 87 uint16_t DIVREF:1; /*!< bit: 15 Divide Reference Clock */ 88 } bit; /*!< Structure used for bit access */ 89 uint16_t reg; /*!< Type used for register access */ 90 } FREQM_CFGA_Type; 91 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 92 93 #define FREQM_CFGA_OFFSET 0x02 /**< \brief (FREQM_CFGA offset) Config A register */ 94 #define FREQM_CFGA_RESETVALUE _U_(0x0000) /**< \brief (FREQM_CFGA reset_value) Config A register */ 95 96 #define FREQM_CFGA_REFNUM_Pos 0 /**< \brief (FREQM_CFGA) Number of Reference Clock Cycles */ 97 #define FREQM_CFGA_REFNUM_Msk (_U_(0xFF) << FREQM_CFGA_REFNUM_Pos) 98 #define FREQM_CFGA_REFNUM(value) (FREQM_CFGA_REFNUM_Msk & ((value) << FREQM_CFGA_REFNUM_Pos)) 99 #define FREQM_CFGA_DIVREF_Pos 15 /**< \brief (FREQM_CFGA) Divide Reference Clock */ 100 #define FREQM_CFGA_DIVREF (_U_(0x1) << FREQM_CFGA_DIVREF_Pos) 101 #define FREQM_CFGA_MASK _U_(0x80FF) /**< \brief (FREQM_CFGA) MASK Register */ 102 103 /* -------- FREQM_INTENCLR : (FREQM Offset: 0x08) (R/W 8) Interrupt Enable Clear Register -------- */ 104 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 105 typedef union { 106 struct { 107 uint8_t DONE:1; /*!< bit: 0 Measurement Done Interrupt Enable */ 108 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 109 } bit; /*!< Structure used for bit access */ 110 uint8_t reg; /*!< Type used for register access */ 111 } FREQM_INTENCLR_Type; 112 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 113 114 #define FREQM_INTENCLR_OFFSET 0x08 /**< \brief (FREQM_INTENCLR offset) Interrupt Enable Clear Register */ 115 #define FREQM_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (FREQM_INTENCLR reset_value) Interrupt Enable Clear Register */ 116 117 #define FREQM_INTENCLR_DONE_Pos 0 /**< \brief (FREQM_INTENCLR) Measurement Done Interrupt Enable */ 118 #define FREQM_INTENCLR_DONE (_U_(0x1) << FREQM_INTENCLR_DONE_Pos) 119 #define FREQM_INTENCLR_MASK _U_(0x01) /**< \brief (FREQM_INTENCLR) MASK Register */ 120 121 /* -------- FREQM_INTENSET : (FREQM Offset: 0x09) (R/W 8) Interrupt Enable Set Register -------- */ 122 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 123 typedef union { 124 struct { 125 uint8_t DONE:1; /*!< bit: 0 Measurement Done Interrupt Enable */ 126 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 127 } bit; /*!< Structure used for bit access */ 128 uint8_t reg; /*!< Type used for register access */ 129 } FREQM_INTENSET_Type; 130 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 131 132 #define FREQM_INTENSET_OFFSET 0x09 /**< \brief (FREQM_INTENSET offset) Interrupt Enable Set Register */ 133 #define FREQM_INTENSET_RESETVALUE _U_(0x00) /**< \brief (FREQM_INTENSET reset_value) Interrupt Enable Set Register */ 134 135 #define FREQM_INTENSET_DONE_Pos 0 /**< \brief (FREQM_INTENSET) Measurement Done Interrupt Enable */ 136 #define FREQM_INTENSET_DONE (_U_(0x1) << FREQM_INTENSET_DONE_Pos) 137 #define FREQM_INTENSET_MASK _U_(0x01) /**< \brief (FREQM_INTENSET) MASK Register */ 138 139 /* -------- FREQM_INTFLAG : (FREQM Offset: 0x0A) (R/W 8) Interrupt Flag Register -------- */ 140 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 141 typedef union { // __I to avoid read-modify-write on write-to-clear register 142 struct { 143 __I uint8_t DONE:1; /*!< bit: 0 Measurement Done */ 144 __I uint8_t Reserved1:7; /*!< bit: 1.. 7 Reserved */ 145 } bit; /*!< Structure used for bit access */ 146 uint8_t reg; /*!< Type used for register access */ 147 } FREQM_INTFLAG_Type; 148 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 149 150 #define FREQM_INTFLAG_OFFSET 0x0A /**< \brief (FREQM_INTFLAG offset) Interrupt Flag Register */ 151 #define FREQM_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (FREQM_INTFLAG reset_value) Interrupt Flag Register */ 152 153 #define FREQM_INTFLAG_DONE_Pos 0 /**< \brief (FREQM_INTFLAG) Measurement Done */ 154 #define FREQM_INTFLAG_DONE (_U_(0x1) << FREQM_INTFLAG_DONE_Pos) 155 #define FREQM_INTFLAG_MASK _U_(0x01) /**< \brief (FREQM_INTFLAG) MASK Register */ 156 157 /* -------- FREQM_STATUS : (FREQM Offset: 0x0B) (R/W 8) Status Register -------- */ 158 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 159 typedef union { 160 struct { 161 uint8_t BUSY:1; /*!< bit: 0 FREQM Status */ 162 uint8_t OVF:1; /*!< bit: 1 Sticky Count Value Overflow */ 163 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 164 } bit; /*!< Structure used for bit access */ 165 uint8_t reg; /*!< Type used for register access */ 166 } FREQM_STATUS_Type; 167 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 168 169 #define FREQM_STATUS_OFFSET 0x0B /**< \brief (FREQM_STATUS offset) Status Register */ 170 #define FREQM_STATUS_RESETVALUE _U_(0x00) /**< \brief (FREQM_STATUS reset_value) Status Register */ 171 172 #define FREQM_STATUS_BUSY_Pos 0 /**< \brief (FREQM_STATUS) FREQM Status */ 173 #define FREQM_STATUS_BUSY (_U_(0x1) << FREQM_STATUS_BUSY_Pos) 174 #define FREQM_STATUS_OVF_Pos 1 /**< \brief (FREQM_STATUS) Sticky Count Value Overflow */ 175 #define FREQM_STATUS_OVF (_U_(0x1) << FREQM_STATUS_OVF_Pos) 176 #define FREQM_STATUS_MASK _U_(0x03) /**< \brief (FREQM_STATUS) MASK Register */ 177 178 /* -------- FREQM_SYNCBUSY : (FREQM Offset: 0x0C) (R/ 32) Synchronization Busy Register -------- */ 179 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 180 typedef union { 181 struct { 182 uint32_t SWRST:1; /*!< bit: 0 Software Reset */ 183 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 184 uint32_t :30; /*!< bit: 2..31 Reserved */ 185 } bit; /*!< Structure used for bit access */ 186 uint32_t reg; /*!< Type used for register access */ 187 } FREQM_SYNCBUSY_Type; 188 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 189 190 #define FREQM_SYNCBUSY_OFFSET 0x0C /**< \brief (FREQM_SYNCBUSY offset) Synchronization Busy Register */ 191 #define FREQM_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (FREQM_SYNCBUSY reset_value) Synchronization Busy Register */ 192 193 #define FREQM_SYNCBUSY_SWRST_Pos 0 /**< \brief (FREQM_SYNCBUSY) Software Reset */ 194 #define FREQM_SYNCBUSY_SWRST (_U_(0x1) << FREQM_SYNCBUSY_SWRST_Pos) 195 #define FREQM_SYNCBUSY_ENABLE_Pos 1 /**< \brief (FREQM_SYNCBUSY) Enable */ 196 #define FREQM_SYNCBUSY_ENABLE (_U_(0x1) << FREQM_SYNCBUSY_ENABLE_Pos) 197 #define FREQM_SYNCBUSY_MASK _U_(0x00000003) /**< \brief (FREQM_SYNCBUSY) MASK Register */ 198 199 /* -------- FREQM_VALUE : (FREQM Offset: 0x10) (R/ 32) Count Value Register -------- */ 200 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 201 typedef union { 202 struct { 203 uint32_t VALUE:24; /*!< bit: 0..23 Measurement Value */ 204 uint32_t :8; /*!< bit: 24..31 Reserved */ 205 } bit; /*!< Structure used for bit access */ 206 uint32_t reg; /*!< Type used for register access */ 207 } FREQM_VALUE_Type; 208 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 209 210 #define FREQM_VALUE_OFFSET 0x10 /**< \brief (FREQM_VALUE offset) Count Value Register */ 211 #define FREQM_VALUE_RESETVALUE _U_(0x00000000) /**< \brief (FREQM_VALUE reset_value) Count Value Register */ 212 213 #define FREQM_VALUE_VALUE_Pos 0 /**< \brief (FREQM_VALUE) Measurement Value */ 214 #define FREQM_VALUE_VALUE_Msk (_U_(0xFFFFFF) << FREQM_VALUE_VALUE_Pos) 215 #define FREQM_VALUE_VALUE(value) (FREQM_VALUE_VALUE_Msk & ((value) << FREQM_VALUE_VALUE_Pos)) 216 #define FREQM_VALUE_MASK _U_(0x00FFFFFF) /**< \brief (FREQM_VALUE) MASK Register */ 217 218 /** \brief FREQM hardware registers */ 219 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 220 typedef struct { 221 __IO FREQM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A Register */ 222 __O FREQM_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B Register */ 223 __IO FREQM_CFGA_Type CFGA; /**< \brief Offset: 0x02 (R/W 16) Config A register */ 224 RoReg8 Reserved1[0x4]; 225 __IO FREQM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear Register */ 226 __IO FREQM_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set Register */ 227 __IO FREQM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Register */ 228 __IO FREQM_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status Register */ 229 __I FREQM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x0C (R/ 32) Synchronization Busy Register */ 230 __I FREQM_VALUE_Type VALUE; /**< \brief Offset: 0x10 (R/ 32) Count Value Register */ 231 } Freqm; 232 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 233 234 /*@}*/ 235 236 #endif /* _SAMC21_FREQM_COMPONENT_ */ 237
