1 /** 2 * \file 3 * 4 * \brief Component description for DIVAS 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMC21_DIVAS_COMPONENT_ 31 #define _SAMC21_DIVAS_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR DIVAS */ 35 /* ========================================================================== */ 36 /** \addtogroup SAMC21_DIVAS Divide and Square Root Accelerator */ 37 /*@{*/ 38 39 #define DIVAS_U2258 40 #define REV_DIVAS 0x100 41 42 /* -------- DIVAS_CTRLA : (DIVAS Offset: 0x00) (R/W 8) Control -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint8_t SIGNED:1; /*!< bit: 0 Signed */ 47 uint8_t DLZ:1; /*!< bit: 1 Disable Leading Zero Optimization */ 48 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 49 } bit; /*!< Structure used for bit access */ 50 uint8_t reg; /*!< Type used for register access */ 51 } DIVAS_CTRLA_Type; 52 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 53 54 #define DIVAS_CTRLA_OFFSET 0x00 /**< \brief (DIVAS_CTRLA offset) Control */ 55 #define DIVAS_CTRLA_RESETVALUE _U_(0x00) /**< \brief (DIVAS_CTRLA reset_value) Control */ 56 57 #define DIVAS_CTRLA_SIGNED_Pos 0 /**< \brief (DIVAS_CTRLA) Signed */ 58 #define DIVAS_CTRLA_SIGNED (_U_(0x1) << DIVAS_CTRLA_SIGNED_Pos) 59 #define DIVAS_CTRLA_DLZ_Pos 1 /**< \brief (DIVAS_CTRLA) Disable Leading Zero Optimization */ 60 #define DIVAS_CTRLA_DLZ (_U_(0x1) << DIVAS_CTRLA_DLZ_Pos) 61 #define DIVAS_CTRLA_MASK _U_(0x03) /**< \brief (DIVAS_CTRLA) MASK Register */ 62 63 /* -------- DIVAS_STATUS : (DIVAS Offset: 0x04) (R/W 8) Status -------- */ 64 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 65 typedef union { 66 struct { 67 uint8_t BUSY:1; /*!< bit: 0 DIVAS Accelerator Busy */ 68 uint8_t DBZ:1; /*!< bit: 1 Writing a one to this bit clears DBZ to zero */ 69 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 70 } bit; /*!< Structure used for bit access */ 71 uint8_t reg; /*!< Type used for register access */ 72 } DIVAS_STATUS_Type; 73 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 74 75 #define DIVAS_STATUS_OFFSET 0x04 /**< \brief (DIVAS_STATUS offset) Status */ 76 #define DIVAS_STATUS_RESETVALUE _U_(0x00) /**< \brief (DIVAS_STATUS reset_value) Status */ 77 78 #define DIVAS_STATUS_BUSY_Pos 0 /**< \brief (DIVAS_STATUS) DIVAS Accelerator Busy */ 79 #define DIVAS_STATUS_BUSY (_U_(0x1) << DIVAS_STATUS_BUSY_Pos) 80 #define DIVAS_STATUS_DBZ_Pos 1 /**< \brief (DIVAS_STATUS) Writing a one to this bit clears DBZ to zero */ 81 #define DIVAS_STATUS_DBZ (_U_(0x1) << DIVAS_STATUS_DBZ_Pos) 82 #define DIVAS_STATUS_MASK _U_(0x03) /**< \brief (DIVAS_STATUS) MASK Register */ 83 84 /* -------- DIVAS_DIVIDEND : (DIVAS Offset: 0x08) (R/W 32) Dividend -------- */ 85 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 86 typedef union { 87 struct { 88 uint32_t DIVIDEND:32; /*!< bit: 0..31 DIVIDEND */ 89 } bit; /*!< Structure used for bit access */ 90 uint32_t reg; /*!< Type used for register access */ 91 } DIVAS_DIVIDEND_Type; 92 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 93 94 #define DIVAS_DIVIDEND_OFFSET 0x08 /**< \brief (DIVAS_DIVIDEND offset) Dividend */ 95 #define DIVAS_DIVIDEND_RESETVALUE _U_(0x00000000) /**< \brief (DIVAS_DIVIDEND reset_value) Dividend */ 96 97 #define DIVAS_DIVIDEND_DIVIDEND_Pos 0 /**< \brief (DIVAS_DIVIDEND) DIVIDEND */ 98 #define DIVAS_DIVIDEND_DIVIDEND_Msk (_U_(0xFFFFFFFF) << DIVAS_DIVIDEND_DIVIDEND_Pos) 99 #define DIVAS_DIVIDEND_DIVIDEND(value) (DIVAS_DIVIDEND_DIVIDEND_Msk & ((value) << DIVAS_DIVIDEND_DIVIDEND_Pos)) 100 #define DIVAS_DIVIDEND_MASK _U_(0xFFFFFFFF) /**< \brief (DIVAS_DIVIDEND) MASK Register */ 101 102 /* -------- DIVAS_DIVISOR : (DIVAS Offset: 0x0C) (R/W 32) Divisor -------- */ 103 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 104 typedef union { 105 struct { 106 uint32_t DIVISOR:32; /*!< bit: 0..31 DIVISOR */ 107 } bit; /*!< Structure used for bit access */ 108 uint32_t reg; /*!< Type used for register access */ 109 } DIVAS_DIVISOR_Type; 110 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 111 112 #define DIVAS_DIVISOR_OFFSET 0x0C /**< \brief (DIVAS_DIVISOR offset) Divisor */ 113 #define DIVAS_DIVISOR_RESETVALUE _U_(0x00000000) /**< \brief (DIVAS_DIVISOR reset_value) Divisor */ 114 115 #define DIVAS_DIVISOR_DIVISOR_Pos 0 /**< \brief (DIVAS_DIVISOR) DIVISOR */ 116 #define DIVAS_DIVISOR_DIVISOR_Msk (_U_(0xFFFFFFFF) << DIVAS_DIVISOR_DIVISOR_Pos) 117 #define DIVAS_DIVISOR_DIVISOR(value) (DIVAS_DIVISOR_DIVISOR_Msk & ((value) << DIVAS_DIVISOR_DIVISOR_Pos)) 118 #define DIVAS_DIVISOR_MASK _U_(0xFFFFFFFF) /**< \brief (DIVAS_DIVISOR) MASK Register */ 119 120 /* -------- DIVAS_RESULT : (DIVAS Offset: 0x10) (R/ 32) Result -------- */ 121 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 122 typedef union { 123 struct { 124 uint32_t RESULT:32; /*!< bit: 0..31 RESULT */ 125 } bit; /*!< Structure used for bit access */ 126 uint32_t reg; /*!< Type used for register access */ 127 } DIVAS_RESULT_Type; 128 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 129 130 #define DIVAS_RESULT_OFFSET 0x10 /**< \brief (DIVAS_RESULT offset) Result */ 131 #define DIVAS_RESULT_RESETVALUE _U_(0x00000000) /**< \brief (DIVAS_RESULT reset_value) Result */ 132 133 #define DIVAS_RESULT_RESULT_Pos 0 /**< \brief (DIVAS_RESULT) RESULT */ 134 #define DIVAS_RESULT_RESULT_Msk (_U_(0xFFFFFFFF) << DIVAS_RESULT_RESULT_Pos) 135 #define DIVAS_RESULT_RESULT(value) (DIVAS_RESULT_RESULT_Msk & ((value) << DIVAS_RESULT_RESULT_Pos)) 136 #define DIVAS_RESULT_MASK _U_(0xFFFFFFFF) /**< \brief (DIVAS_RESULT) MASK Register */ 137 138 /* -------- DIVAS_REM : (DIVAS Offset: 0x14) (R/ 32) Remainder -------- */ 139 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 140 typedef union { 141 struct { 142 uint32_t REM:32; /*!< bit: 0..31 REM */ 143 } bit; /*!< Structure used for bit access */ 144 uint32_t reg; /*!< Type used for register access */ 145 } DIVAS_REM_Type; 146 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 147 148 #define DIVAS_REM_OFFSET 0x14 /**< \brief (DIVAS_REM offset) Remainder */ 149 #define DIVAS_REM_RESETVALUE _U_(0x00000000) /**< \brief (DIVAS_REM reset_value) Remainder */ 150 151 #define DIVAS_REM_REM_Pos 0 /**< \brief (DIVAS_REM) REM */ 152 #define DIVAS_REM_REM_Msk (_U_(0xFFFFFFFF) << DIVAS_REM_REM_Pos) 153 #define DIVAS_REM_REM(value) (DIVAS_REM_REM_Msk & ((value) << DIVAS_REM_REM_Pos)) 154 #define DIVAS_REM_MASK _U_(0xFFFFFFFF) /**< \brief (DIVAS_REM) MASK Register */ 155 156 /* -------- DIVAS_SQRNUM : (DIVAS Offset: 0x18) (R/W 32) Square Root Input -------- */ 157 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 158 typedef union { 159 struct { 160 uint32_t SQRNUM:32; /*!< bit: 0..31 Square Root Input */ 161 } bit; /*!< Structure used for bit access */ 162 uint32_t reg; /*!< Type used for register access */ 163 } DIVAS_SQRNUM_Type; 164 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 165 166 #define DIVAS_SQRNUM_OFFSET 0x18 /**< \brief (DIVAS_SQRNUM offset) Square Root Input */ 167 #define DIVAS_SQRNUM_RESETVALUE _U_(0x00000000) /**< \brief (DIVAS_SQRNUM reset_value) Square Root Input */ 168 169 #define DIVAS_SQRNUM_SQRNUM_Pos 0 /**< \brief (DIVAS_SQRNUM) Square Root Input */ 170 #define DIVAS_SQRNUM_SQRNUM_Msk (_U_(0xFFFFFFFF) << DIVAS_SQRNUM_SQRNUM_Pos) 171 #define DIVAS_SQRNUM_SQRNUM(value) (DIVAS_SQRNUM_SQRNUM_Msk & ((value) << DIVAS_SQRNUM_SQRNUM_Pos)) 172 #define DIVAS_SQRNUM_MASK _U_(0xFFFFFFFF) /**< \brief (DIVAS_SQRNUM) MASK Register */ 173 174 /** \brief DIVAS hardware registers */ 175 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 176 typedef struct { 177 __IO DIVAS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control */ 178 RoReg8 Reserved1[0x3]; 179 __IO DIVAS_STATUS_Type STATUS; /**< \brief Offset: 0x04 (R/W 8) Status */ 180 RoReg8 Reserved2[0x3]; 181 __IO DIVAS_DIVIDEND_Type DIVIDEND; /**< \brief Offset: 0x08 (R/W 32) Dividend */ 182 __IO DIVAS_DIVISOR_Type DIVISOR; /**< \brief Offset: 0x0C (R/W 32) Divisor */ 183 __I DIVAS_RESULT_Type RESULT; /**< \brief Offset: 0x10 (R/ 32) Result */ 184 __I DIVAS_REM_Type REM; /**< \brief Offset: 0x14 (R/ 32) Remainder */ 185 __IO DIVAS_SQRNUM_Type SQRNUM; /**< \brief Offset: 0x18 (R/W 32) Square Root Input */ 186 } Divas; 187 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 188 189 /*@}*/ 190 191 #endif /* _SAMC21_DIVAS_COMPONENT_ */ 192
