1 /** 2 * \file 3 * 4 * \brief Instance description for TSENS 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMC21_TSENS_INSTANCE_ 31 #define _SAMC21_TSENS_INSTANCE_ 32 33 /* ========== Register definition for TSENS peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_TSENS_CTRLA (0x40003000) /**< \brief (TSENS) Control A Register */ 36 #define REG_TSENS_CTRLB (0x40003001) /**< \brief (TSENS) Control B Register */ 37 #define REG_TSENS_CTRLC (0x40003002) /**< \brief (TSENS) Control C Register */ 38 #define REG_TSENS_EVCTRL (0x40003003) /**< \brief (TSENS) Event Control Register */ 39 #define REG_TSENS_INTENCLR (0x40003004) /**< \brief (TSENS) Interrupt Enable Clear Register */ 40 #define REG_TSENS_INTENSET (0x40003005) /**< \brief (TSENS) Interrupt Enable Set Register */ 41 #define REG_TSENS_INTFLAG (0x40003006) /**< \brief (TSENS) Interrupt Flag Status and Clear Register */ 42 #define REG_TSENS_STATUS (0x40003007) /**< \brief (TSENS) Status Register */ 43 #define REG_TSENS_SYNCBUSY (0x40003008) /**< \brief (TSENS) Synchronization Busy Register */ 44 #define REG_TSENS_VALUE (0x4000300C) /**< \brief (TSENS) Value Register */ 45 #define REG_TSENS_WINLT (0x40003010) /**< \brief (TSENS) Window Monitor Lower Threshold Register */ 46 #define REG_TSENS_WINUT (0x40003014) /**< \brief (TSENS) Window Monitor Upper Threshold Register */ 47 #define REG_TSENS_GAIN (0x40003018) /**< \brief (TSENS) Gain Register */ 48 #define REG_TSENS_OFFSET (0x4000301C) /**< \brief (TSENS) Offset Register */ 49 #define REG_TSENS_CAL (0x40003020) /**< \brief (TSENS) Calibration Register */ 50 #define REG_TSENS_DBGCTRL (0x40003024) /**< \brief (TSENS) Debug Control Register */ 51 #else 52 #define REG_TSENS_CTRLA (*(RwReg8 *)0x40003000UL) /**< \brief (TSENS) Control A Register */ 53 #define REG_TSENS_CTRLB (*(WoReg8 *)0x40003001UL) /**< \brief (TSENS) Control B Register */ 54 #define REG_TSENS_CTRLC (*(RwReg8 *)0x40003002UL) /**< \brief (TSENS) Control C Register */ 55 #define REG_TSENS_EVCTRL (*(RwReg8 *)0x40003003UL) /**< \brief (TSENS) Event Control Register */ 56 #define REG_TSENS_INTENCLR (*(RwReg8 *)0x40003004UL) /**< \brief (TSENS) Interrupt Enable Clear Register */ 57 #define REG_TSENS_INTENSET (*(RwReg8 *)0x40003005UL) /**< \brief (TSENS) Interrupt Enable Set Register */ 58 #define REG_TSENS_INTFLAG (*(RwReg8 *)0x40003006UL) /**< \brief (TSENS) Interrupt Flag Status and Clear Register */ 59 #define REG_TSENS_STATUS (*(RoReg8 *)0x40003007UL) /**< \brief (TSENS) Status Register */ 60 #define REG_TSENS_SYNCBUSY (*(RoReg *)0x40003008UL) /**< \brief (TSENS) Synchronization Busy Register */ 61 #define REG_TSENS_VALUE (*(RoReg *)0x4000300CUL) /**< \brief (TSENS) Value Register */ 62 #define REG_TSENS_WINLT (*(RwReg *)0x40003010UL) /**< \brief (TSENS) Window Monitor Lower Threshold Register */ 63 #define REG_TSENS_WINUT (*(RwReg *)0x40003014UL) /**< \brief (TSENS) Window Monitor Upper Threshold Register */ 64 #define REG_TSENS_GAIN (*(RwReg *)0x40003018UL) /**< \brief (TSENS) Gain Register */ 65 #define REG_TSENS_OFFSET (*(RwReg *)0x4000301CUL) /**< \brief (TSENS) Offset Register */ 66 #define REG_TSENS_CAL (*(RwReg *)0x40003020UL) /**< \brief (TSENS) Calibration Register */ 67 #define REG_TSENS_DBGCTRL (*(RwReg8 *)0x40003024UL) /**< \brief (TSENS) Debug Control Register */ 68 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 69 70 /* ========== Instance parameters for TSENS peripheral ========== */ 71 #define TSENS_DMAC_ID_RESRDY 1 // Index of DMA RESRDY trigger 72 #define TSENS_GCLK_ID 5 // Index of Generic Clock 73 74 #endif /* _SAMC21_TSENS_INSTANCE_ */ 75
