1 /** 2 * \file 3 * 4 * \brief Instance description for SDADC 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMC21_SDADC_INSTANCE_ 31 #define _SAMC21_SDADC_INSTANCE_ 32 33 /* ========== Register definition for SDADC peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_SDADC_CTRLA (0x42004C00) /**< \brief (SDADC) Control A */ 36 #define REG_SDADC_REFCTRL (0x42004C01) /**< \brief (SDADC) Reference Control */ 37 #define REG_SDADC_CTRLB (0x42004C02) /**< \brief (SDADC) Control B */ 38 #define REG_SDADC_EVCTRL (0x42004C04) /**< \brief (SDADC) Event Control */ 39 #define REG_SDADC_INTENCLR (0x42004C05) /**< \brief (SDADC) Interrupt Enable Clear */ 40 #define REG_SDADC_INTENSET (0x42004C06) /**< \brief (SDADC) Interrupt Enable Set */ 41 #define REG_SDADC_INTFLAG (0x42004C07) /**< \brief (SDADC) Interrupt Flag Status and Clear */ 42 #define REG_SDADC_SEQSTATUS (0x42004C08) /**< \brief (SDADC) Sequence Status */ 43 #define REG_SDADC_INPUTCTRL (0x42004C09) /**< \brief (SDADC) Input Control */ 44 #define REG_SDADC_CTRLC (0x42004C0A) /**< \brief (SDADC) Control C */ 45 #define REG_SDADC_WINCTRL (0x42004C0B) /**< \brief (SDADC) Window Monitor Control */ 46 #define REG_SDADC_WINLT (0x42004C0C) /**< \brief (SDADC) Window Monitor Lower Threshold */ 47 #define REG_SDADC_WINUT (0x42004C10) /**< \brief (SDADC) Window Monitor Upper Threshold */ 48 #define REG_SDADC_OFFSETCORR (0x42004C14) /**< \brief (SDADC) Offset Correction */ 49 #define REG_SDADC_GAINCORR (0x42004C18) /**< \brief (SDADC) Gain Correction */ 50 #define REG_SDADC_SHIFTCORR (0x42004C1A) /**< \brief (SDADC) Shift Correction */ 51 #define REG_SDADC_SWTRIG (0x42004C1C) /**< \brief (SDADC) Software Trigger */ 52 #define REG_SDADC_SYNCBUSY (0x42004C20) /**< \brief (SDADC) Synchronization Busy */ 53 #define REG_SDADC_RESULT (0x42004C24) /**< \brief (SDADC) Result */ 54 #define REG_SDADC_SEQCTRL (0x42004C28) /**< \brief (SDADC) Sequence Control */ 55 #define REG_SDADC_ANACTRL (0x42004C2C) /**< \brief (SDADC) Analog Control */ 56 #define REG_SDADC_DBGCTRL (0x42004C2E) /**< \brief (SDADC) Debug Control */ 57 #else 58 #define REG_SDADC_CTRLA (*(RwReg8 *)0x42004C00UL) /**< \brief (SDADC) Control A */ 59 #define REG_SDADC_REFCTRL (*(RwReg8 *)0x42004C01UL) /**< \brief (SDADC) Reference Control */ 60 #define REG_SDADC_CTRLB (*(RwReg16*)0x42004C02UL) /**< \brief (SDADC) Control B */ 61 #define REG_SDADC_EVCTRL (*(RwReg8 *)0x42004C04UL) /**< \brief (SDADC) Event Control */ 62 #define REG_SDADC_INTENCLR (*(RwReg8 *)0x42004C05UL) /**< \brief (SDADC) Interrupt Enable Clear */ 63 #define REG_SDADC_INTENSET (*(RwReg8 *)0x42004C06UL) /**< \brief (SDADC) Interrupt Enable Set */ 64 #define REG_SDADC_INTFLAG (*(RwReg8 *)0x42004C07UL) /**< \brief (SDADC) Interrupt Flag Status and Clear */ 65 #define REG_SDADC_SEQSTATUS (*(RoReg8 *)0x42004C08UL) /**< \brief (SDADC) Sequence Status */ 66 #define REG_SDADC_INPUTCTRL (*(RwReg8 *)0x42004C09UL) /**< \brief (SDADC) Input Control */ 67 #define REG_SDADC_CTRLC (*(RwReg8 *)0x42004C0AUL) /**< \brief (SDADC) Control C */ 68 #define REG_SDADC_WINCTRL (*(RwReg8 *)0x42004C0BUL) /**< \brief (SDADC) Window Monitor Control */ 69 #define REG_SDADC_WINLT (*(RwReg *)0x42004C0CUL) /**< \brief (SDADC) Window Monitor Lower Threshold */ 70 #define REG_SDADC_WINUT (*(RwReg *)0x42004C10UL) /**< \brief (SDADC) Window Monitor Upper Threshold */ 71 #define REG_SDADC_OFFSETCORR (*(RwReg *)0x42004C14UL) /**< \brief (SDADC) Offset Correction */ 72 #define REG_SDADC_GAINCORR (*(RwReg16*)0x42004C18UL) /**< \brief (SDADC) Gain Correction */ 73 #define REG_SDADC_SHIFTCORR (*(RwReg8 *)0x42004C1AUL) /**< \brief (SDADC) Shift Correction */ 74 #define REG_SDADC_SWTRIG (*(RwReg8 *)0x42004C1CUL) /**< \brief (SDADC) Software Trigger */ 75 #define REG_SDADC_SYNCBUSY (*(RoReg *)0x42004C20UL) /**< \brief (SDADC) Synchronization Busy */ 76 #define REG_SDADC_RESULT (*(RoReg *)0x42004C24UL) /**< \brief (SDADC) Result */ 77 #define REG_SDADC_SEQCTRL (*(RwReg8 *)0x42004C28UL) /**< \brief (SDADC) Sequence Control */ 78 #define REG_SDADC_ANACTRL (*(RwReg8 *)0x42004C2CUL) /**< \brief (SDADC) Analog Control */ 79 #define REG_SDADC_DBGCTRL (*(RwReg8 *)0x42004C2EUL) /**< \brief (SDADC) Debug Control */ 80 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 81 82 /* ========== Instance parameters for SDADC peripheral ========== */ 83 #define SDADC_DMAC_ID_RESRDY 44 // Index of DMA RESRDY trigger 84 #define SDADC_EXT_CHANNELS 3 // Number of external channels 85 #define SDADC_GCLK_ID 35 // Index of generic clock 86 87 #endif /* _SAMC21_SDADC_INSTANCE_ */ 88
