1 /** 2 * \file 3 * 4 * \brief Instance description for OSCCTRL 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMC21_OSCCTRL_INSTANCE_ 31 #define _SAMC21_OSCCTRL_INSTANCE_ 32 33 /* ========== Register definition for OSCCTRL peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_OSCCTRL_INTENCLR (0x40001000) /**< \brief (OSCCTRL) Interrupt Enable Clear */ 36 #define REG_OSCCTRL_INTENSET (0x40001004) /**< \brief (OSCCTRL) Interrupt Enable Set */ 37 #define REG_OSCCTRL_INTFLAG (0x40001008) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */ 38 #define REG_OSCCTRL_STATUS (0x4000100C) /**< \brief (OSCCTRL) Power and Clocks Status */ 39 #define REG_OSCCTRL_XOSCCTRL (0x40001010) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */ 40 #define REG_OSCCTRL_CFDPRESC (0x40001012) /**< \brief (OSCCTRL) Clock Failure Detector Prescaler */ 41 #define REG_OSCCTRL_EVCTRL (0x40001013) /**< \brief (OSCCTRL) Event Control */ 42 #define REG_OSCCTRL_OSC48MCTRL (0x40001014) /**< \brief (OSCCTRL) 48MHz Internal Oscillator (OSC48M) Control */ 43 #define REG_OSCCTRL_OSC48MDIV (0x40001015) /**< \brief (OSCCTRL) OSC48M Divider */ 44 #define REG_OSCCTRL_OSC48MSTUP (0x40001016) /**< \brief (OSCCTRL) OSC48M Startup Time */ 45 #define REG_OSCCTRL_OSC48MSYNCBUSY (0x40001018) /**< \brief (OSCCTRL) OSC48M Synchronization Busy */ 46 #define REG_OSCCTRL_DPLLCTRLA (0x4000101C) /**< \brief (OSCCTRL) DPLL Control */ 47 #define REG_OSCCTRL_DPLLRATIO (0x40001020) /**< \brief (OSCCTRL) DPLL Ratio Control */ 48 #define REG_OSCCTRL_DPLLCTRLB (0x40001024) /**< \brief (OSCCTRL) Digital Core Configuration */ 49 #define REG_OSCCTRL_DPLLPRESC (0x40001028) /**< \brief (OSCCTRL) DPLL Prescaler */ 50 #define REG_OSCCTRL_DPLLSYNCBUSY (0x4000102C) /**< \brief (OSCCTRL) DPLL Synchronization Busy */ 51 #define REG_OSCCTRL_DPLLSTATUS (0x40001030) /**< \brief (OSCCTRL) DPLL Status */ 52 #define REG_OSCCTRL_CAL48M (0x40001038) /**< \brief (OSCCTRL) 48MHz Oscillator Calibration */ 53 #else 54 #define REG_OSCCTRL_INTENCLR (*(RwReg *)0x40001000UL) /**< \brief (OSCCTRL) Interrupt Enable Clear */ 55 #define REG_OSCCTRL_INTENSET (*(RwReg *)0x40001004UL) /**< \brief (OSCCTRL) Interrupt Enable Set */ 56 #define REG_OSCCTRL_INTFLAG (*(RwReg *)0x40001008UL) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */ 57 #define REG_OSCCTRL_STATUS (*(RoReg *)0x4000100CUL) /**< \brief (OSCCTRL) Power and Clocks Status */ 58 #define REG_OSCCTRL_XOSCCTRL (*(RwReg16*)0x40001010UL) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */ 59 #define REG_OSCCTRL_CFDPRESC (*(RwReg8 *)0x40001012UL) /**< \brief (OSCCTRL) Clock Failure Detector Prescaler */ 60 #define REG_OSCCTRL_EVCTRL (*(RwReg8 *)0x40001013UL) /**< \brief (OSCCTRL) Event Control */ 61 #define REG_OSCCTRL_OSC48MCTRL (*(RwReg8 *)0x40001014UL) /**< \brief (OSCCTRL) 48MHz Internal Oscillator (OSC48M) Control */ 62 #define REG_OSCCTRL_OSC48MDIV (*(RwReg8 *)0x40001015UL) /**< \brief (OSCCTRL) OSC48M Divider */ 63 #define REG_OSCCTRL_OSC48MSTUP (*(RwReg8 *)0x40001016UL) /**< \brief (OSCCTRL) OSC48M Startup Time */ 64 #define REG_OSCCTRL_OSC48MSYNCBUSY (*(RoReg *)0x40001018UL) /**< \brief (OSCCTRL) OSC48M Synchronization Busy */ 65 #define REG_OSCCTRL_DPLLCTRLA (*(RwReg8 *)0x4000101CUL) /**< \brief (OSCCTRL) DPLL Control */ 66 #define REG_OSCCTRL_DPLLRATIO (*(RwReg *)0x40001020UL) /**< \brief (OSCCTRL) DPLL Ratio Control */ 67 #define REG_OSCCTRL_DPLLCTRLB (*(RwReg *)0x40001024UL) /**< \brief (OSCCTRL) Digital Core Configuration */ 68 #define REG_OSCCTRL_DPLLPRESC (*(RwReg8 *)0x40001028UL) /**< \brief (OSCCTRL) DPLL Prescaler */ 69 #define REG_OSCCTRL_DPLLSYNCBUSY (*(RoReg8 *)0x4000102CUL) /**< \brief (OSCCTRL) DPLL Synchronization Busy */ 70 #define REG_OSCCTRL_DPLLSTATUS (*(RoReg8 *)0x40001030UL) /**< \brief (OSCCTRL) DPLL Status */ 71 #define REG_OSCCTRL_CAL48M (*(RwReg *)0x40001038UL) /**< \brief (OSCCTRL) 48MHz Oscillator Calibration */ 72 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 73 74 /* ========== Instance parameters for OSCCTRL peripheral ========== */ 75 #define OSCCTRL_GCLK_ID_FDPLL 0 // Index of Generic Clock for DPLL 76 #define OSCCTRL_GCLK_ID_FDPLL32K 1 // Index of Generic Clock for DPLL 32K 77 #define OSCCTRL_FDPLL_VERSION 0x211 78 #define OSCCTRL_OSC48M_VERSION 0x101 79 #define OSCCTRL_XOSC_VERSION 0x201 80 81 #endif /* _SAMC21_OSCCTRL_INSTANCE_ */ 82
