1 /** 2 * \file 3 * 4 * \brief Instance description for CAN0 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMC21_CAN0_INSTANCE_ 31 #define _SAMC21_CAN0_INSTANCE_ 32 33 /* ========== Register definition for CAN0 peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_CAN0_CREL (0x42001C00) /**< \brief (CAN0) Core Release */ 36 #define REG_CAN0_ENDN (0x42001C04) /**< \brief (CAN0) Endian */ 37 #define REG_CAN0_MRCFG (0x42001C08) /**< \brief (CAN0) Message RAM Configuration */ 38 #define REG_CAN0_DBTP (0x42001C0C) /**< \brief (CAN0) Fast Bit Timing and Prescaler */ 39 #define REG_CAN0_TEST (0x42001C10) /**< \brief (CAN0) Test */ 40 #define REG_CAN0_RWD (0x42001C14) /**< \brief (CAN0) RAM Watchdog */ 41 #define REG_CAN0_CCCR (0x42001C18) /**< \brief (CAN0) CC Control */ 42 #define REG_CAN0_NBTP (0x42001C1C) /**< \brief (CAN0) Nominal Bit Timing and Prescaler */ 43 #define REG_CAN0_TSCC (0x42001C20) /**< \brief (CAN0) Timestamp Counter Configuration */ 44 #define REG_CAN0_TSCV (0x42001C24) /**< \brief (CAN0) Timestamp Counter Value */ 45 #define REG_CAN0_TOCC (0x42001C28) /**< \brief (CAN0) Timeout Counter Configuration */ 46 #define REG_CAN0_TOCV (0x42001C2C) /**< \brief (CAN0) Timeout Counter Value */ 47 #define REG_CAN0_ECR (0x42001C40) /**< \brief (CAN0) Error Counter */ 48 #define REG_CAN0_PSR (0x42001C44) /**< \brief (CAN0) Protocol Status */ 49 #define REG_CAN0_TDCR (0x42001C48) /**< \brief (CAN0) Extended ID Filter Configuration */ 50 #define REG_CAN0_IR (0x42001C50) /**< \brief (CAN0) Interrupt */ 51 #define REG_CAN0_IE (0x42001C54) /**< \brief (CAN0) Interrupt Enable */ 52 #define REG_CAN0_ILS (0x42001C58) /**< \brief (CAN0) Interrupt Line Select */ 53 #define REG_CAN0_ILE (0x42001C5C) /**< \brief (CAN0) Interrupt Line Enable */ 54 #define REG_CAN0_GFC (0x42001C80) /**< \brief (CAN0) Global Filter Configuration */ 55 #define REG_CAN0_SIDFC (0x42001C84) /**< \brief (CAN0) Standard ID Filter Configuration */ 56 #define REG_CAN0_XIDFC (0x42001C88) /**< \brief (CAN0) Extended ID Filter Configuration */ 57 #define REG_CAN0_XIDAM (0x42001C90) /**< \brief (CAN0) Extended ID AND Mask */ 58 #define REG_CAN0_HPMS (0x42001C94) /**< \brief (CAN0) High Priority Message Status */ 59 #define REG_CAN0_NDAT1 (0x42001C98) /**< \brief (CAN0) New Data 1 */ 60 #define REG_CAN0_NDAT2 (0x42001C9C) /**< \brief (CAN0) New Data 2 */ 61 #define REG_CAN0_RXF0C (0x42001CA0) /**< \brief (CAN0) Rx FIFO 0 Configuration */ 62 #define REG_CAN0_RXF0S (0x42001CA4) /**< \brief (CAN0) Rx FIFO 0 Status */ 63 #define REG_CAN0_RXF0A (0x42001CA8) /**< \brief (CAN0) Rx FIFO 0 Acknowledge */ 64 #define REG_CAN0_RXBC (0x42001CAC) /**< \brief (CAN0) Rx Buffer Configuration */ 65 #define REG_CAN0_RXF1C (0x42001CB0) /**< \brief (CAN0) Rx FIFO 1 Configuration */ 66 #define REG_CAN0_RXF1S (0x42001CB4) /**< \brief (CAN0) Rx FIFO 1 Status */ 67 #define REG_CAN0_RXF1A (0x42001CB8) /**< \brief (CAN0) Rx FIFO 1 Acknowledge */ 68 #define REG_CAN0_RXESC (0x42001CBC) /**< \brief (CAN0) Rx Buffer / FIFO Element Size Configuration */ 69 #define REG_CAN0_TXBC (0x42001CC0) /**< \brief (CAN0) Tx Buffer Configuration */ 70 #define REG_CAN0_TXFQS (0x42001CC4) /**< \brief (CAN0) Tx FIFO / Queue Status */ 71 #define REG_CAN0_TXESC (0x42001CC8) /**< \brief (CAN0) Tx Buffer Element Size Configuration */ 72 #define REG_CAN0_TXBRP (0x42001CCC) /**< \brief (CAN0) Tx Buffer Request Pending */ 73 #define REG_CAN0_TXBAR (0x42001CD0) /**< \brief (CAN0) Tx Buffer Add Request */ 74 #define REG_CAN0_TXBCR (0x42001CD4) /**< \brief (CAN0) Tx Buffer Cancellation Request */ 75 #define REG_CAN0_TXBTO (0x42001CD8) /**< \brief (CAN0) Tx Buffer Transmission Occurred */ 76 #define REG_CAN0_TXBCF (0x42001CDC) /**< \brief (CAN0) Tx Buffer Cancellation Finished */ 77 #define REG_CAN0_TXBTIE (0x42001CE0) /**< \brief (CAN0) Tx Buffer Transmission Interrupt Enable */ 78 #define REG_CAN0_TXBCIE (0x42001CE4) /**< \brief (CAN0) Tx Buffer Cancellation Finished Interrupt Enable */ 79 #define REG_CAN0_TXEFC (0x42001CF0) /**< \brief (CAN0) Tx Event FIFO Configuration */ 80 #define REG_CAN0_TXEFS (0x42001CF4) /**< \brief (CAN0) Tx Event FIFO Status */ 81 #define REG_CAN0_TXEFA (0x42001CF8) /**< \brief (CAN0) Tx Event FIFO Acknowledge */ 82 #else 83 #define REG_CAN0_CREL (*(RoReg *)0x42001C00UL) /**< \brief (CAN0) Core Release */ 84 #define REG_CAN0_ENDN (*(RoReg *)0x42001C04UL) /**< \brief (CAN0) Endian */ 85 #define REG_CAN0_MRCFG (*(RwReg *)0x42001C08UL) /**< \brief (CAN0) Message RAM Configuration */ 86 #define REG_CAN0_DBTP (*(RwReg *)0x42001C0CUL) /**< \brief (CAN0) Fast Bit Timing and Prescaler */ 87 #define REG_CAN0_TEST (*(RwReg *)0x42001C10UL) /**< \brief (CAN0) Test */ 88 #define REG_CAN0_RWD (*(RwReg *)0x42001C14UL) /**< \brief (CAN0) RAM Watchdog */ 89 #define REG_CAN0_CCCR (*(RwReg *)0x42001C18UL) /**< \brief (CAN0) CC Control */ 90 #define REG_CAN0_NBTP (*(RwReg *)0x42001C1CUL) /**< \brief (CAN0) Nominal Bit Timing and Prescaler */ 91 #define REG_CAN0_TSCC (*(RwReg *)0x42001C20UL) /**< \brief (CAN0) Timestamp Counter Configuration */ 92 #define REG_CAN0_TSCV (*(RoReg *)0x42001C24UL) /**< \brief (CAN0) Timestamp Counter Value */ 93 #define REG_CAN0_TOCC (*(RwReg *)0x42001C28UL) /**< \brief (CAN0) Timeout Counter Configuration */ 94 #define REG_CAN0_TOCV (*(RwReg *)0x42001C2CUL) /**< \brief (CAN0) Timeout Counter Value */ 95 #define REG_CAN0_ECR (*(RoReg *)0x42001C40UL) /**< \brief (CAN0) Error Counter */ 96 #define REG_CAN0_PSR (*(RoReg *)0x42001C44UL) /**< \brief (CAN0) Protocol Status */ 97 #define REG_CAN0_TDCR (*(RwReg *)0x42001C48UL) /**< \brief (CAN0) Extended ID Filter Configuration */ 98 #define REG_CAN0_IR (*(RwReg *)0x42001C50UL) /**< \brief (CAN0) Interrupt */ 99 #define REG_CAN0_IE (*(RwReg *)0x42001C54UL) /**< \brief (CAN0) Interrupt Enable */ 100 #define REG_CAN0_ILS (*(RwReg *)0x42001C58UL) /**< \brief (CAN0) Interrupt Line Select */ 101 #define REG_CAN0_ILE (*(RwReg *)0x42001C5CUL) /**< \brief (CAN0) Interrupt Line Enable */ 102 #define REG_CAN0_GFC (*(RwReg *)0x42001C80UL) /**< \brief (CAN0) Global Filter Configuration */ 103 #define REG_CAN0_SIDFC (*(RwReg *)0x42001C84UL) /**< \brief (CAN0) Standard ID Filter Configuration */ 104 #define REG_CAN0_XIDFC (*(RwReg *)0x42001C88UL) /**< \brief (CAN0) Extended ID Filter Configuration */ 105 #define REG_CAN0_XIDAM (*(RwReg *)0x42001C90UL) /**< \brief (CAN0) Extended ID AND Mask */ 106 #define REG_CAN0_HPMS (*(RoReg *)0x42001C94UL) /**< \brief (CAN0) High Priority Message Status */ 107 #define REG_CAN0_NDAT1 (*(RwReg *)0x42001C98UL) /**< \brief (CAN0) New Data 1 */ 108 #define REG_CAN0_NDAT2 (*(RwReg *)0x42001C9CUL) /**< \brief (CAN0) New Data 2 */ 109 #define REG_CAN0_RXF0C (*(RwReg *)0x42001CA0UL) /**< \brief (CAN0) Rx FIFO 0 Configuration */ 110 #define REG_CAN0_RXF0S (*(RoReg *)0x42001CA4UL) /**< \brief (CAN0) Rx FIFO 0 Status */ 111 #define REG_CAN0_RXF0A (*(RwReg *)0x42001CA8UL) /**< \brief (CAN0) Rx FIFO 0 Acknowledge */ 112 #define REG_CAN0_RXBC (*(RwReg *)0x42001CACUL) /**< \brief (CAN0) Rx Buffer Configuration */ 113 #define REG_CAN0_RXF1C (*(RwReg *)0x42001CB0UL) /**< \brief (CAN0) Rx FIFO 1 Configuration */ 114 #define REG_CAN0_RXF1S (*(RoReg *)0x42001CB4UL) /**< \brief (CAN0) Rx FIFO 1 Status */ 115 #define REG_CAN0_RXF1A (*(RwReg *)0x42001CB8UL) /**< \brief (CAN0) Rx FIFO 1 Acknowledge */ 116 #define REG_CAN0_RXESC (*(RwReg *)0x42001CBCUL) /**< \brief (CAN0) Rx Buffer / FIFO Element Size Configuration */ 117 #define REG_CAN0_TXBC (*(RwReg *)0x42001CC0UL) /**< \brief (CAN0) Tx Buffer Configuration */ 118 #define REG_CAN0_TXFQS (*(RoReg *)0x42001CC4UL) /**< \brief (CAN0) Tx FIFO / Queue Status */ 119 #define REG_CAN0_TXESC (*(RwReg *)0x42001CC8UL) /**< \brief (CAN0) Tx Buffer Element Size Configuration */ 120 #define REG_CAN0_TXBRP (*(RoReg *)0x42001CCCUL) /**< \brief (CAN0) Tx Buffer Request Pending */ 121 #define REG_CAN0_TXBAR (*(RwReg *)0x42001CD0UL) /**< \brief (CAN0) Tx Buffer Add Request */ 122 #define REG_CAN0_TXBCR (*(RwReg *)0x42001CD4UL) /**< \brief (CAN0) Tx Buffer Cancellation Request */ 123 #define REG_CAN0_TXBTO (*(RoReg *)0x42001CD8UL) /**< \brief (CAN0) Tx Buffer Transmission Occurred */ 124 #define REG_CAN0_TXBCF (*(RoReg *)0x42001CDCUL) /**< \brief (CAN0) Tx Buffer Cancellation Finished */ 125 #define REG_CAN0_TXBTIE (*(RwReg *)0x42001CE0UL) /**< \brief (CAN0) Tx Buffer Transmission Interrupt Enable */ 126 #define REG_CAN0_TXBCIE (*(RwReg *)0x42001CE4UL) /**< \brief (CAN0) Tx Buffer Cancellation Finished Interrupt Enable */ 127 #define REG_CAN0_TXEFC (*(RwReg *)0x42001CF0UL) /**< \brief (CAN0) Tx Event FIFO Configuration */ 128 #define REG_CAN0_TXEFS (*(RoReg *)0x42001CF4UL) /**< \brief (CAN0) Tx Event FIFO Status */ 129 #define REG_CAN0_TXEFA (*(RwReg *)0x42001CF8UL) /**< \brief (CAN0) Tx Event FIFO Acknowledge */ 130 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 131 132 /* ========== Instance parameters for CAN0 peripheral ========== */ 133 #define CAN0_CLK_AHB_ID 8 // Index of AHB clock 134 #define CAN0_DMAC_ID_DEBUG 14 // DMA CAN Debug Req 135 #define CAN0_GCLK_ID 26 // Index of Generic Clock 136 #define CAN0_MSG_RAM_ADDR 0x200000000 137 #define CAN0_QOS_RESET_VAL 2 // QOS reset value 138 139 #endif /* _SAMC21_CAN0_INSTANCE_ */ 140
