1 /** 2 * \file 3 * 4 * \brief Component description for TSENS 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMC21_TSENS_COMPONENT_ 31 #define _SAMC21_TSENS_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR TSENS */ 35 /* ========================================================================== */ 36 /** \addtogroup SAMC21_TSENS Temperature Sensor */ 37 /*@{*/ 38 39 #define TSENS_U2261 40 #define REV_TSENS 0x101 41 42 /* -------- TSENS_CTRLA : (TSENS Offset: 0x00) (R/W 8) Control A Register -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint8_t SWRST:1; /*!< bit: 0 Software Reset */ 47 uint8_t ENABLE:1; /*!< bit: 1 Enable */ 48 uint8_t :4; /*!< bit: 2.. 5 Reserved */ 49 uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ 50 uint8_t :1; /*!< bit: 7 Reserved */ 51 } bit; /*!< Structure used for bit access */ 52 uint8_t reg; /*!< Type used for register access */ 53 } TSENS_CTRLA_Type; 54 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 55 56 #define TSENS_CTRLA_OFFSET 0x00 /**< \brief (TSENS_CTRLA offset) Control A Register */ 57 #define TSENS_CTRLA_RESETVALUE _U_(0x00) /**< \brief (TSENS_CTRLA reset_value) Control A Register */ 58 59 #define TSENS_CTRLA_SWRST_Pos 0 /**< \brief (TSENS_CTRLA) Software Reset */ 60 #define TSENS_CTRLA_SWRST (_U_(0x1) << TSENS_CTRLA_SWRST_Pos) 61 #define TSENS_CTRLA_ENABLE_Pos 1 /**< \brief (TSENS_CTRLA) Enable */ 62 #define TSENS_CTRLA_ENABLE (_U_(0x1) << TSENS_CTRLA_ENABLE_Pos) 63 #define TSENS_CTRLA_RUNSTDBY_Pos 6 /**< \brief (TSENS_CTRLA) Run in Standby */ 64 #define TSENS_CTRLA_RUNSTDBY (_U_(0x1) << TSENS_CTRLA_RUNSTDBY_Pos) 65 #define TSENS_CTRLA_MASK _U_(0x43) /**< \brief (TSENS_CTRLA) MASK Register */ 66 67 /* -------- TSENS_CTRLB : (TSENS Offset: 0x01) ( /W 8) Control B Register -------- */ 68 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 69 typedef union { 70 struct { 71 uint8_t START:1; /*!< bit: 0 Start Measurement */ 72 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 73 } bit; /*!< Structure used for bit access */ 74 uint8_t reg; /*!< Type used for register access */ 75 } TSENS_CTRLB_Type; 76 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 77 78 #define TSENS_CTRLB_OFFSET 0x01 /**< \brief (TSENS_CTRLB offset) Control B Register */ 79 #define TSENS_CTRLB_RESETVALUE _U_(0x00) /**< \brief (TSENS_CTRLB reset_value) Control B Register */ 80 81 #define TSENS_CTRLB_START_Pos 0 /**< \brief (TSENS_CTRLB) Start Measurement */ 82 #define TSENS_CTRLB_START (_U_(0x1) << TSENS_CTRLB_START_Pos) 83 #define TSENS_CTRLB_MASK _U_(0x01) /**< \brief (TSENS_CTRLB) MASK Register */ 84 85 /* -------- TSENS_CTRLC : (TSENS Offset: 0x02) (R/W 8) Control C Register -------- */ 86 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 87 typedef union { 88 struct { 89 uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */ 90 uint8_t :1; /*!< bit: 3 Reserved */ 91 uint8_t FREERUN:1; /*!< bit: 4 Free Running Measurement */ 92 uint8_t :3; /*!< bit: 5.. 7 Reserved */ 93 } bit; /*!< Structure used for bit access */ 94 uint8_t reg; /*!< Type used for register access */ 95 } TSENS_CTRLC_Type; 96 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 97 98 #define TSENS_CTRLC_OFFSET 0x02 /**< \brief (TSENS_CTRLC offset) Control C Register */ 99 #define TSENS_CTRLC_RESETVALUE _U_(0x00) /**< \brief (TSENS_CTRLC reset_value) Control C Register */ 100 101 #define TSENS_CTRLC_WINMODE_Pos 0 /**< \brief (TSENS_CTRLC) Window Monitor Mode */ 102 #define TSENS_CTRLC_WINMODE_Msk (_U_(0x7) << TSENS_CTRLC_WINMODE_Pos) 103 #define TSENS_CTRLC_WINMODE(value) (TSENS_CTRLC_WINMODE_Msk & ((value) << TSENS_CTRLC_WINMODE_Pos)) 104 #define TSENS_CTRLC_WINMODE_DISABLE_Val _U_(0x0) /**< \brief (TSENS_CTRLC) No window mode (default) */ 105 #define TSENS_CTRLC_WINMODE_ABOVE_Val _U_(0x1) /**< \brief (TSENS_CTRLC) VALUE greater than WINLT */ 106 #define TSENS_CTRLC_WINMODE_BELOW_Val _U_(0x2) /**< \brief (TSENS_CTRLC) VALUE less than WINUT */ 107 #define TSENS_CTRLC_WINMODE_INSIDE_Val _U_(0x3) /**< \brief (TSENS_CTRLC) VALUE greater than WINLT and VALUE less than WINUT */ 108 #define TSENS_CTRLC_WINMODE_OUTSIDE_Val _U_(0x4) /**< \brief (TSENS_CTRLC) VALUE less than WINLT or VALUE greater than WINUT */ 109 #define TSENS_CTRLC_WINMODE_HYST_ABOVE_Val _U_(0x5) /**< \brief (TSENS_CTRLC) VALUE greater than WINUT with hysteresis to WINLT */ 110 #define TSENS_CTRLC_WINMODE_HYST_BELOW_Val _U_(0x6) /**< \brief (TSENS_CTRLC) VALUE less than WINLST with hysteresis to WINUT */ 111 #define TSENS_CTRLC_WINMODE_DISABLE (TSENS_CTRLC_WINMODE_DISABLE_Val << TSENS_CTRLC_WINMODE_Pos) 112 #define TSENS_CTRLC_WINMODE_ABOVE (TSENS_CTRLC_WINMODE_ABOVE_Val << TSENS_CTRLC_WINMODE_Pos) 113 #define TSENS_CTRLC_WINMODE_BELOW (TSENS_CTRLC_WINMODE_BELOW_Val << TSENS_CTRLC_WINMODE_Pos) 114 #define TSENS_CTRLC_WINMODE_INSIDE (TSENS_CTRLC_WINMODE_INSIDE_Val << TSENS_CTRLC_WINMODE_Pos) 115 #define TSENS_CTRLC_WINMODE_OUTSIDE (TSENS_CTRLC_WINMODE_OUTSIDE_Val << TSENS_CTRLC_WINMODE_Pos) 116 #define TSENS_CTRLC_WINMODE_HYST_ABOVE (TSENS_CTRLC_WINMODE_HYST_ABOVE_Val << TSENS_CTRLC_WINMODE_Pos) 117 #define TSENS_CTRLC_WINMODE_HYST_BELOW (TSENS_CTRLC_WINMODE_HYST_BELOW_Val << TSENS_CTRLC_WINMODE_Pos) 118 #define TSENS_CTRLC_FREERUN_Pos 4 /**< \brief (TSENS_CTRLC) Free Running Measurement */ 119 #define TSENS_CTRLC_FREERUN (_U_(0x1) << TSENS_CTRLC_FREERUN_Pos) 120 #define TSENS_CTRLC_MASK _U_(0x17) /**< \brief (TSENS_CTRLC) MASK Register */ 121 122 /* -------- TSENS_EVCTRL : (TSENS Offset: 0x03) (R/W 8) Event Control Register -------- */ 123 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 124 typedef union { 125 struct { 126 uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event Input Enable */ 127 uint8_t STARTINV:1; /*!< bit: 1 Start Conversion Event Invert Enable */ 128 uint8_t WINEO:1; /*!< bit: 2 Window Monitor Event Out */ 129 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 130 } bit; /*!< Structure used for bit access */ 131 uint8_t reg; /*!< Type used for register access */ 132 } TSENS_EVCTRL_Type; 133 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 134 135 #define TSENS_EVCTRL_OFFSET 0x03 /**< \brief (TSENS_EVCTRL offset) Event Control Register */ 136 #define TSENS_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (TSENS_EVCTRL reset_value) Event Control Register */ 137 138 #define TSENS_EVCTRL_STARTEI_Pos 0 /**< \brief (TSENS_EVCTRL) Start Conversion Event Input Enable */ 139 #define TSENS_EVCTRL_STARTEI (_U_(0x1) << TSENS_EVCTRL_STARTEI_Pos) 140 #define TSENS_EVCTRL_STARTINV_Pos 1 /**< \brief (TSENS_EVCTRL) Start Conversion Event Invert Enable */ 141 #define TSENS_EVCTRL_STARTINV (_U_(0x1) << TSENS_EVCTRL_STARTINV_Pos) 142 #define TSENS_EVCTRL_WINEO_Pos 2 /**< \brief (TSENS_EVCTRL) Window Monitor Event Out */ 143 #define TSENS_EVCTRL_WINEO (_U_(0x1) << TSENS_EVCTRL_WINEO_Pos) 144 #define TSENS_EVCTRL_MASK _U_(0x07) /**< \brief (TSENS_EVCTRL) MASK Register */ 145 146 /* -------- TSENS_INTENCLR : (TSENS Offset: 0x04) (R/W 8) Interrupt Enable Clear Register -------- */ 147 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 148 typedef union { 149 struct { 150 uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ 151 uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ 152 uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ 153 uint8_t OVF:1; /*!< bit: 3 Overflow Interrupt Enable */ 154 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 155 } bit; /*!< Structure used for bit access */ 156 uint8_t reg; /*!< Type used for register access */ 157 } TSENS_INTENCLR_Type; 158 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 159 160 #define TSENS_INTENCLR_OFFSET 0x04 /**< \brief (TSENS_INTENCLR offset) Interrupt Enable Clear Register */ 161 #define TSENS_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (TSENS_INTENCLR reset_value) Interrupt Enable Clear Register */ 162 163 #define TSENS_INTENCLR_RESRDY_Pos 0 /**< \brief (TSENS_INTENCLR) Result Ready Interrupt Enable */ 164 #define TSENS_INTENCLR_RESRDY (_U_(0x1) << TSENS_INTENCLR_RESRDY_Pos) 165 #define TSENS_INTENCLR_OVERRUN_Pos 1 /**< \brief (TSENS_INTENCLR) Overrun Interrupt Enable */ 166 #define TSENS_INTENCLR_OVERRUN (_U_(0x1) << TSENS_INTENCLR_OVERRUN_Pos) 167 #define TSENS_INTENCLR_WINMON_Pos 2 /**< \brief (TSENS_INTENCLR) Window Monitor Interrupt Enable */ 168 #define TSENS_INTENCLR_WINMON (_U_(0x1) << TSENS_INTENCLR_WINMON_Pos) 169 #define TSENS_INTENCLR_OVF_Pos 3 /**< \brief (TSENS_INTENCLR) Overflow Interrupt Enable */ 170 #define TSENS_INTENCLR_OVF (_U_(0x1) << TSENS_INTENCLR_OVF_Pos) 171 #define TSENS_INTENCLR_MASK _U_(0x0F) /**< \brief (TSENS_INTENCLR) MASK Register */ 172 173 /* -------- TSENS_INTENSET : (TSENS Offset: 0x05) (R/W 8) Interrupt Enable Set Register -------- */ 174 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 175 typedef union { 176 struct { 177 uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ 178 uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ 179 uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ 180 uint8_t OVF:1; /*!< bit: 3 Overflow Interrupt Enable */ 181 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 182 } bit; /*!< Structure used for bit access */ 183 uint8_t reg; /*!< Type used for register access */ 184 } TSENS_INTENSET_Type; 185 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 186 187 #define TSENS_INTENSET_OFFSET 0x05 /**< \brief (TSENS_INTENSET offset) Interrupt Enable Set Register */ 188 #define TSENS_INTENSET_RESETVALUE _U_(0x00) /**< \brief (TSENS_INTENSET reset_value) Interrupt Enable Set Register */ 189 190 #define TSENS_INTENSET_RESRDY_Pos 0 /**< \brief (TSENS_INTENSET) Result Ready Interrupt Enable */ 191 #define TSENS_INTENSET_RESRDY (_U_(0x1) << TSENS_INTENSET_RESRDY_Pos) 192 #define TSENS_INTENSET_OVERRUN_Pos 1 /**< \brief (TSENS_INTENSET) Overrun Interrupt Enable */ 193 #define TSENS_INTENSET_OVERRUN (_U_(0x1) << TSENS_INTENSET_OVERRUN_Pos) 194 #define TSENS_INTENSET_WINMON_Pos 2 /**< \brief (TSENS_INTENSET) Window Monitor Interrupt Enable */ 195 #define TSENS_INTENSET_WINMON (_U_(0x1) << TSENS_INTENSET_WINMON_Pos) 196 #define TSENS_INTENSET_OVF_Pos 3 /**< \brief (TSENS_INTENSET) Overflow Interrupt Enable */ 197 #define TSENS_INTENSET_OVF (_U_(0x1) << TSENS_INTENSET_OVF_Pos) 198 #define TSENS_INTENSET_MASK _U_(0x0F) /**< \brief (TSENS_INTENSET) MASK Register */ 199 200 /* -------- TSENS_INTFLAG : (TSENS Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear Register -------- */ 201 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 202 typedef union { // __I to avoid read-modify-write on write-to-clear register 203 struct { 204 __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready */ 205 __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun */ 206 __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor */ 207 __I uint8_t OVF:1; /*!< bit: 3 Overflow */ 208 __I uint8_t Reserved1:4; /*!< bit: 4.. 7 Reserved */ 209 } bit; /*!< Structure used for bit access */ 210 uint8_t reg; /*!< Type used for register access */ 211 } TSENS_INTFLAG_Type; 212 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 213 214 #define TSENS_INTFLAG_OFFSET 0x06 /**< \brief (TSENS_INTFLAG offset) Interrupt Flag Status and Clear Register */ 215 #define TSENS_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (TSENS_INTFLAG reset_value) Interrupt Flag Status and Clear Register */ 216 217 #define TSENS_INTFLAG_RESRDY_Pos 0 /**< \brief (TSENS_INTFLAG) Result Ready */ 218 #define TSENS_INTFLAG_RESRDY (_U_(0x1) << TSENS_INTFLAG_RESRDY_Pos) 219 #define TSENS_INTFLAG_OVERRUN_Pos 1 /**< \brief (TSENS_INTFLAG) Overrun */ 220 #define TSENS_INTFLAG_OVERRUN (_U_(0x1) << TSENS_INTFLAG_OVERRUN_Pos) 221 #define TSENS_INTFLAG_WINMON_Pos 2 /**< \brief (TSENS_INTFLAG) Window Monitor */ 222 #define TSENS_INTFLAG_WINMON (_U_(0x1) << TSENS_INTFLAG_WINMON_Pos) 223 #define TSENS_INTFLAG_OVF_Pos 3 /**< \brief (TSENS_INTFLAG) Overflow */ 224 #define TSENS_INTFLAG_OVF (_U_(0x1) << TSENS_INTFLAG_OVF_Pos) 225 #define TSENS_INTFLAG_MASK _U_(0x0F) /**< \brief (TSENS_INTFLAG) MASK Register */ 226 227 /* -------- TSENS_STATUS : (TSENS Offset: 0x07) (R/ 8) Status Register -------- */ 228 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 229 typedef union { 230 struct { 231 uint8_t OVF:1; /*!< bit: 0 Result Overflow */ 232 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 233 } bit; /*!< Structure used for bit access */ 234 uint8_t reg; /*!< Type used for register access */ 235 } TSENS_STATUS_Type; 236 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 237 238 #define TSENS_STATUS_OFFSET 0x07 /**< \brief (TSENS_STATUS offset) Status Register */ 239 #define TSENS_STATUS_RESETVALUE _U_(0x00) /**< \brief (TSENS_STATUS reset_value) Status Register */ 240 241 #define TSENS_STATUS_OVF_Pos 0 /**< \brief (TSENS_STATUS) Result Overflow */ 242 #define TSENS_STATUS_OVF (_U_(0x1) << TSENS_STATUS_OVF_Pos) 243 #define TSENS_STATUS_MASK _U_(0x01) /**< \brief (TSENS_STATUS) MASK Register */ 244 245 /* -------- TSENS_SYNCBUSY : (TSENS Offset: 0x08) (R/ 32) Synchronization Busy Register -------- */ 246 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 247 typedef union { 248 struct { 249 uint32_t SWRST:1; /*!< bit: 0 Software Reset Busy */ 250 uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */ 251 uint32_t :30; /*!< bit: 2..31 Reserved */ 252 } bit; /*!< Structure used for bit access */ 253 uint32_t reg; /*!< Type used for register access */ 254 } TSENS_SYNCBUSY_Type; 255 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 256 257 #define TSENS_SYNCBUSY_OFFSET 0x08 /**< \brief (TSENS_SYNCBUSY offset) Synchronization Busy Register */ 258 #define TSENS_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (TSENS_SYNCBUSY reset_value) Synchronization Busy Register */ 259 260 #define TSENS_SYNCBUSY_SWRST_Pos 0 /**< \brief (TSENS_SYNCBUSY) Software Reset Busy */ 261 #define TSENS_SYNCBUSY_SWRST (_U_(0x1) << TSENS_SYNCBUSY_SWRST_Pos) 262 #define TSENS_SYNCBUSY_ENABLE_Pos 1 /**< \brief (TSENS_SYNCBUSY) Enable Busy */ 263 #define TSENS_SYNCBUSY_ENABLE (_U_(0x1) << TSENS_SYNCBUSY_ENABLE_Pos) 264 #define TSENS_SYNCBUSY_MASK _U_(0x00000003) /**< \brief (TSENS_SYNCBUSY) MASK Register */ 265 266 /* -------- TSENS_VALUE : (TSENS Offset: 0x0C) (R/ 32) Value Register -------- */ 267 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 268 typedef union { 269 struct { 270 uint32_t VALUE:24; /*!< bit: 0..23 Measurement Value */ 271 uint32_t :8; /*!< bit: 24..31 Reserved */ 272 } bit; /*!< Structure used for bit access */ 273 uint32_t reg; /*!< Type used for register access */ 274 } TSENS_VALUE_Type; 275 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 276 277 #define TSENS_VALUE_OFFSET 0x0C /**< \brief (TSENS_VALUE offset) Value Register */ 278 #define TSENS_VALUE_RESETVALUE _U_(0x00000000) /**< \brief (TSENS_VALUE reset_value) Value Register */ 279 280 #define TSENS_VALUE_VALUE_Pos 0 /**< \brief (TSENS_VALUE) Measurement Value */ 281 #define TSENS_VALUE_VALUE_Msk (_U_(0xFFFFFF) << TSENS_VALUE_VALUE_Pos) 282 #define TSENS_VALUE_VALUE(value) (TSENS_VALUE_VALUE_Msk & ((value) << TSENS_VALUE_VALUE_Pos)) 283 #define TSENS_VALUE_MASK _U_(0x00FFFFFF) /**< \brief (TSENS_VALUE) MASK Register */ 284 285 /* -------- TSENS_WINLT : (TSENS Offset: 0x10) (R/W 32) Window Monitor Lower Threshold Register -------- */ 286 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 287 typedef union { 288 struct { 289 uint32_t WINLT:24; /*!< bit: 0..23 Window Lower Threshold */ 290 uint32_t :8; /*!< bit: 24..31 Reserved */ 291 } bit; /*!< Structure used for bit access */ 292 uint32_t reg; /*!< Type used for register access */ 293 } TSENS_WINLT_Type; 294 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 295 296 #define TSENS_WINLT_OFFSET 0x10 /**< \brief (TSENS_WINLT offset) Window Monitor Lower Threshold Register */ 297 #define TSENS_WINLT_RESETVALUE _U_(0x00000000) /**< \brief (TSENS_WINLT reset_value) Window Monitor Lower Threshold Register */ 298 299 #define TSENS_WINLT_WINLT_Pos 0 /**< \brief (TSENS_WINLT) Window Lower Threshold */ 300 #define TSENS_WINLT_WINLT_Msk (_U_(0xFFFFFF) << TSENS_WINLT_WINLT_Pos) 301 #define TSENS_WINLT_WINLT(value) (TSENS_WINLT_WINLT_Msk & ((value) << TSENS_WINLT_WINLT_Pos)) 302 #define TSENS_WINLT_MASK _U_(0x00FFFFFF) /**< \brief (TSENS_WINLT) MASK Register */ 303 304 /* -------- TSENS_WINUT : (TSENS Offset: 0x14) (R/W 32) Window Monitor Upper Threshold Register -------- */ 305 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 306 typedef union { 307 struct { 308 uint32_t WINUT:24; /*!< bit: 0..23 Window Upper Threshold */ 309 uint32_t :8; /*!< bit: 24..31 Reserved */ 310 } bit; /*!< Structure used for bit access */ 311 uint32_t reg; /*!< Type used for register access */ 312 } TSENS_WINUT_Type; 313 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 314 315 #define TSENS_WINUT_OFFSET 0x14 /**< \brief (TSENS_WINUT offset) Window Monitor Upper Threshold Register */ 316 #define TSENS_WINUT_RESETVALUE _U_(0x00000000) /**< \brief (TSENS_WINUT reset_value) Window Monitor Upper Threshold Register */ 317 318 #define TSENS_WINUT_WINUT_Pos 0 /**< \brief (TSENS_WINUT) Window Upper Threshold */ 319 #define TSENS_WINUT_WINUT_Msk (_U_(0xFFFFFF) << TSENS_WINUT_WINUT_Pos) 320 #define TSENS_WINUT_WINUT(value) (TSENS_WINUT_WINUT_Msk & ((value) << TSENS_WINUT_WINUT_Pos)) 321 #define TSENS_WINUT_MASK _U_(0x00FFFFFF) /**< \brief (TSENS_WINUT) MASK Register */ 322 323 /* -------- TSENS_GAIN : (TSENS Offset: 0x18) (R/W 32) Gain Register -------- */ 324 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 325 typedef union { 326 struct { 327 uint32_t GAIN:24; /*!< bit: 0..23 Time Amplifier Gain */ 328 uint32_t :8; /*!< bit: 24..31 Reserved */ 329 } bit; /*!< Structure used for bit access */ 330 uint32_t reg; /*!< Type used for register access */ 331 } TSENS_GAIN_Type; 332 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 333 334 #define TSENS_GAIN_OFFSET 0x18 /**< \brief (TSENS_GAIN offset) Gain Register */ 335 #define TSENS_GAIN_RESETVALUE _U_(0x00000000) /**< \brief (TSENS_GAIN reset_value) Gain Register */ 336 337 #define TSENS_GAIN_GAIN_Pos 0 /**< \brief (TSENS_GAIN) Time Amplifier Gain */ 338 #define TSENS_GAIN_GAIN_Msk (_U_(0xFFFFFF) << TSENS_GAIN_GAIN_Pos) 339 #define TSENS_GAIN_GAIN(value) (TSENS_GAIN_GAIN_Msk & ((value) << TSENS_GAIN_GAIN_Pos)) 340 #define TSENS_GAIN_MASK _U_(0x00FFFFFF) /**< \brief (TSENS_GAIN) MASK Register */ 341 342 /* -------- TSENS_OFFSET : (TSENS Offset: 0x1C) (R/W 32) Offset Register -------- */ 343 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 344 typedef union { 345 struct { 346 uint32_t OFFSETC:24; /*!< bit: 0..23 Offset Correction */ 347 uint32_t :8; /*!< bit: 24..31 Reserved */ 348 } bit; /*!< Structure used for bit access */ 349 uint32_t reg; /*!< Type used for register access */ 350 } TSENS_OFFSET_Type; 351 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 352 353 #define TSENS_OFFSET_OFFSET 0x1C /**< \brief (TSENS_OFFSET offset) Offset Register */ 354 #define TSENS_OFFSET_RESETVALUE _U_(0x00000000) /**< \brief (TSENS_OFFSET reset_value) Offset Register */ 355 356 #define TSENS_OFFSET_OFFSETC_Pos 0 /**< \brief (TSENS_OFFSET) Offset Correction */ 357 #define TSENS_OFFSET_OFFSETC_Msk (_U_(0xFFFFFF) << TSENS_OFFSET_OFFSETC_Pos) 358 #define TSENS_OFFSET_OFFSETC(value) (TSENS_OFFSET_OFFSETC_Msk & ((value) << TSENS_OFFSET_OFFSETC_Pos)) 359 #define TSENS_OFFSET_MASK _U_(0x00FFFFFF) /**< \brief (TSENS_OFFSET) MASK Register */ 360 361 /* -------- TSENS_CAL : (TSENS Offset: 0x20) (R/W 32) Calibration Register -------- */ 362 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 363 typedef union { 364 struct { 365 uint32_t FCAL:6; /*!< bit: 0.. 5 Frequency Calibration */ 366 uint32_t :2; /*!< bit: 6.. 7 Reserved */ 367 uint32_t TCAL:6; /*!< bit: 8..13 Temperature Calibration */ 368 uint32_t :18; /*!< bit: 14..31 Reserved */ 369 } bit; /*!< Structure used for bit access */ 370 uint32_t reg; /*!< Type used for register access */ 371 } TSENS_CAL_Type; 372 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 373 374 #define TSENS_CAL_OFFSET 0x20 /**< \brief (TSENS_CAL offset) Calibration Register */ 375 #define TSENS_CAL_RESETVALUE _U_(0x00000000) /**< \brief (TSENS_CAL reset_value) Calibration Register */ 376 377 #define TSENS_CAL_FCAL_Pos 0 /**< \brief (TSENS_CAL) Frequency Calibration */ 378 #define TSENS_CAL_FCAL_Msk (_U_(0x3F) << TSENS_CAL_FCAL_Pos) 379 #define TSENS_CAL_FCAL(value) (TSENS_CAL_FCAL_Msk & ((value) << TSENS_CAL_FCAL_Pos)) 380 #define TSENS_CAL_TCAL_Pos 8 /**< \brief (TSENS_CAL) Temperature Calibration */ 381 #define TSENS_CAL_TCAL_Msk (_U_(0x3F) << TSENS_CAL_TCAL_Pos) 382 #define TSENS_CAL_TCAL(value) (TSENS_CAL_TCAL_Msk & ((value) << TSENS_CAL_TCAL_Pos)) 383 #define TSENS_CAL_MASK _U_(0x00003F3F) /**< \brief (TSENS_CAL) MASK Register */ 384 385 /* -------- TSENS_DBGCTRL : (TSENS Offset: 0x24) (R/W 8) Debug Control Register -------- */ 386 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 387 typedef union { 388 struct { 389 uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ 390 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 391 } bit; /*!< Structure used for bit access */ 392 uint8_t reg; /*!< Type used for register access */ 393 } TSENS_DBGCTRL_Type; 394 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 395 396 #define TSENS_DBGCTRL_OFFSET 0x24 /**< \brief (TSENS_DBGCTRL offset) Debug Control Register */ 397 #define TSENS_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (TSENS_DBGCTRL reset_value) Debug Control Register */ 398 399 #define TSENS_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TSENS_DBGCTRL) Debug Run */ 400 #define TSENS_DBGCTRL_DBGRUN (_U_(0x1) << TSENS_DBGCTRL_DBGRUN_Pos) 401 #define TSENS_DBGCTRL_MASK _U_(0x01) /**< \brief (TSENS_DBGCTRL) MASK Register */ 402 403 /** \brief TSENS hardware registers */ 404 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 405 typedef struct { 406 __IO TSENS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A Register */ 407 __O TSENS_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B Register */ 408 __IO TSENS_CTRLC_Type CTRLC; /**< \brief Offset: 0x02 (R/W 8) Control C Register */ 409 __IO TSENS_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x03 (R/W 8) Event Control Register */ 410 __IO TSENS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear Register */ 411 __IO TSENS_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set Register */ 412 __IO TSENS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear Register */ 413 __I TSENS_STATUS_Type STATUS; /**< \brief Offset: 0x07 (R/ 8) Status Register */ 414 __I TSENS_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy Register */ 415 __I TSENS_VALUE_Type VALUE; /**< \brief Offset: 0x0C (R/ 32) Value Register */ 416 __IO TSENS_WINLT_Type WINLT; /**< \brief Offset: 0x10 (R/W 32) Window Monitor Lower Threshold Register */ 417 __IO TSENS_WINUT_Type WINUT; /**< \brief Offset: 0x14 (R/W 32) Window Monitor Upper Threshold Register */ 418 __IO TSENS_GAIN_Type GAIN; /**< \brief Offset: 0x18 (R/W 32) Gain Register */ 419 __IO TSENS_OFFSET_Type OFFSET; /**< \brief Offset: 0x1C (R/W 32) Offset Register */ 420 __IO TSENS_CAL_Type CAL; /**< \brief Offset: 0x20 (R/W 32) Calibration Register */ 421 __IO TSENS_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x24 (R/W 8) Debug Control Register */ 422 } Tsens; 423 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 424 425 /*@}*/ 426 427 #endif /* _SAMC21_TSENS_COMPONENT_ */ 428
