1 /** 2 * \file 3 * 4 * \brief Component description for TC 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMC21_TC_COMPONENT_ 31 #define _SAMC21_TC_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR TC */ 35 /* ========================================================================== */ 36 /** \addtogroup SAMC21_TC Basic Timer Counter */ 37 /*@{*/ 38 39 #define TC_U2249 40 #define REV_TC 0x200 41 42 /* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 32) Control A -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint32_t SWRST:1; /*!< bit: 0 Software Reset */ 47 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 48 uint32_t MODE:2; /*!< bit: 2.. 3 Timer Counter Mode */ 49 uint32_t PRESCSYNC:2; /*!< bit: 4.. 5 Prescaler and Counter Synchronization */ 50 uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ 51 uint32_t ONDEMAND:1; /*!< bit: 7 Clock On Demand */ 52 uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */ 53 uint32_t ALOCK:1; /*!< bit: 11 Auto Lock */ 54 uint32_t :4; /*!< bit: 12..15 Reserved */ 55 uint32_t CAPTEN0:1; /*!< bit: 16 Capture Channel 0 Enable */ 56 uint32_t CAPTEN1:1; /*!< bit: 17 Capture Channel 1 Enable */ 57 uint32_t :2; /*!< bit: 18..19 Reserved */ 58 uint32_t COPEN0:1; /*!< bit: 20 Capture On Pin 0 Enable */ 59 uint32_t COPEN1:1; /*!< bit: 21 Capture On Pin 1 Enable */ 60 uint32_t :10; /*!< bit: 22..31 Reserved */ 61 } bit; /*!< Structure used for bit access */ 62 struct { 63 uint32_t :16; /*!< bit: 0..15 Reserved */ 64 uint32_t CAPTEN:2; /*!< bit: 16..17 Capture Channel x Enable */ 65 uint32_t :2; /*!< bit: 18..19 Reserved */ 66 uint32_t COPEN:2; /*!< bit: 20..21 Capture On Pin x Enable */ 67 uint32_t :10; /*!< bit: 22..31 Reserved */ 68 } vec; /*!< Structure used for vec access */ 69 uint32_t reg; /*!< Type used for register access */ 70 } TC_CTRLA_Type; 71 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 72 73 #define TC_CTRLA_OFFSET 0x00 /**< \brief (TC_CTRLA offset) Control A */ 74 #define TC_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (TC_CTRLA reset_value) Control A */ 75 76 #define TC_CTRLA_SWRST_Pos 0 /**< \brief (TC_CTRLA) Software Reset */ 77 #define TC_CTRLA_SWRST (_U_(0x1) << TC_CTRLA_SWRST_Pos) 78 #define TC_CTRLA_ENABLE_Pos 1 /**< \brief (TC_CTRLA) Enable */ 79 #define TC_CTRLA_ENABLE (_U_(0x1) << TC_CTRLA_ENABLE_Pos) 80 #define TC_CTRLA_MODE_Pos 2 /**< \brief (TC_CTRLA) Timer Counter Mode */ 81 #define TC_CTRLA_MODE_Msk (_U_(0x3) << TC_CTRLA_MODE_Pos) 82 #define TC_CTRLA_MODE(value) (TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos)) 83 #define TC_CTRLA_MODE_COUNT16_Val _U_(0x0) /**< \brief (TC_CTRLA) Counter in 16-bit mode */ 84 #define TC_CTRLA_MODE_COUNT8_Val _U_(0x1) /**< \brief (TC_CTRLA) Counter in 8-bit mode */ 85 #define TC_CTRLA_MODE_COUNT32_Val _U_(0x2) /**< \brief (TC_CTRLA) Counter in 32-bit mode */ 86 #define TC_CTRLA_MODE_COUNT16 (TC_CTRLA_MODE_COUNT16_Val << TC_CTRLA_MODE_Pos) 87 #define TC_CTRLA_MODE_COUNT8 (TC_CTRLA_MODE_COUNT8_Val << TC_CTRLA_MODE_Pos) 88 #define TC_CTRLA_MODE_COUNT32 (TC_CTRLA_MODE_COUNT32_Val << TC_CTRLA_MODE_Pos) 89 #define TC_CTRLA_PRESCSYNC_Pos 4 /**< \brief (TC_CTRLA) Prescaler and Counter Synchronization */ 90 #define TC_CTRLA_PRESCSYNC_Msk (_U_(0x3) << TC_CTRLA_PRESCSYNC_Pos) 91 #define TC_CTRLA_PRESCSYNC(value) (TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos)) 92 #define TC_CTRLA_PRESCSYNC_GCLK_Val _U_(0x0) /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock */ 93 #define TC_CTRLA_PRESCSYNC_PRESC_Val _U_(0x1) /**< \brief (TC_CTRLA) Reload or reset the counter on next prescaler clock */ 94 #define TC_CTRLA_PRESCSYNC_RESYNC_Val _U_(0x2) /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock and reset the prescaler counter */ 95 #define TC_CTRLA_PRESCSYNC_GCLK (TC_CTRLA_PRESCSYNC_GCLK_Val << TC_CTRLA_PRESCSYNC_Pos) 96 #define TC_CTRLA_PRESCSYNC_PRESC (TC_CTRLA_PRESCSYNC_PRESC_Val << TC_CTRLA_PRESCSYNC_Pos) 97 #define TC_CTRLA_PRESCSYNC_RESYNC (TC_CTRLA_PRESCSYNC_RESYNC_Val << TC_CTRLA_PRESCSYNC_Pos) 98 #define TC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (TC_CTRLA) Run during Standby */ 99 #define TC_CTRLA_RUNSTDBY (_U_(0x1) << TC_CTRLA_RUNSTDBY_Pos) 100 #define TC_CTRLA_ONDEMAND_Pos 7 /**< \brief (TC_CTRLA) Clock On Demand */ 101 #define TC_CTRLA_ONDEMAND (_U_(0x1) << TC_CTRLA_ONDEMAND_Pos) 102 #define TC_CTRLA_PRESCALER_Pos 8 /**< \brief (TC_CTRLA) Prescaler */ 103 #define TC_CTRLA_PRESCALER_Msk (_U_(0x7) << TC_CTRLA_PRESCALER_Pos) 104 #define TC_CTRLA_PRESCALER(value) (TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos)) 105 #define TC_CTRLA_PRESCALER_DIV1_Val _U_(0x0) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC */ 106 #define TC_CTRLA_PRESCALER_DIV2_Val _U_(0x1) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/2 */ 107 #define TC_CTRLA_PRESCALER_DIV4_Val _U_(0x2) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/4 */ 108 #define TC_CTRLA_PRESCALER_DIV8_Val _U_(0x3) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/8 */ 109 #define TC_CTRLA_PRESCALER_DIV16_Val _U_(0x4) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/16 */ 110 #define TC_CTRLA_PRESCALER_DIV64_Val _U_(0x5) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/64 */ 111 #define TC_CTRLA_PRESCALER_DIV256_Val _U_(0x6) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/256 */ 112 #define TC_CTRLA_PRESCALER_DIV1024_Val _U_(0x7) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/1024 */ 113 #define TC_CTRLA_PRESCALER_DIV1 (TC_CTRLA_PRESCALER_DIV1_Val << TC_CTRLA_PRESCALER_Pos) 114 #define TC_CTRLA_PRESCALER_DIV2 (TC_CTRLA_PRESCALER_DIV2_Val << TC_CTRLA_PRESCALER_Pos) 115 #define TC_CTRLA_PRESCALER_DIV4 (TC_CTRLA_PRESCALER_DIV4_Val << TC_CTRLA_PRESCALER_Pos) 116 #define TC_CTRLA_PRESCALER_DIV8 (TC_CTRLA_PRESCALER_DIV8_Val << TC_CTRLA_PRESCALER_Pos) 117 #define TC_CTRLA_PRESCALER_DIV16 (TC_CTRLA_PRESCALER_DIV16_Val << TC_CTRLA_PRESCALER_Pos) 118 #define TC_CTRLA_PRESCALER_DIV64 (TC_CTRLA_PRESCALER_DIV64_Val << TC_CTRLA_PRESCALER_Pos) 119 #define TC_CTRLA_PRESCALER_DIV256 (TC_CTRLA_PRESCALER_DIV256_Val << TC_CTRLA_PRESCALER_Pos) 120 #define TC_CTRLA_PRESCALER_DIV1024 (TC_CTRLA_PRESCALER_DIV1024_Val << TC_CTRLA_PRESCALER_Pos) 121 #define TC_CTRLA_ALOCK_Pos 11 /**< \brief (TC_CTRLA) Auto Lock */ 122 #define TC_CTRLA_ALOCK (_U_(0x1) << TC_CTRLA_ALOCK_Pos) 123 #define TC_CTRLA_CAPTEN0_Pos 16 /**< \brief (TC_CTRLA) Capture Channel 0 Enable */ 124 #define TC_CTRLA_CAPTEN0 (_U_(1) << TC_CTRLA_CAPTEN0_Pos) 125 #define TC_CTRLA_CAPTEN1_Pos 17 /**< \brief (TC_CTRLA) Capture Channel 1 Enable */ 126 #define TC_CTRLA_CAPTEN1 (_U_(1) << TC_CTRLA_CAPTEN1_Pos) 127 #define TC_CTRLA_CAPTEN_Pos 16 /**< \brief (TC_CTRLA) Capture Channel x Enable */ 128 #define TC_CTRLA_CAPTEN_Msk (_U_(0x3) << TC_CTRLA_CAPTEN_Pos) 129 #define TC_CTRLA_CAPTEN(value) (TC_CTRLA_CAPTEN_Msk & ((value) << TC_CTRLA_CAPTEN_Pos)) 130 #define TC_CTRLA_COPEN0_Pos 20 /**< \brief (TC_CTRLA) Capture On Pin 0 Enable */ 131 #define TC_CTRLA_COPEN0 (_U_(1) << TC_CTRLA_COPEN0_Pos) 132 #define TC_CTRLA_COPEN1_Pos 21 /**< \brief (TC_CTRLA) Capture On Pin 1 Enable */ 133 #define TC_CTRLA_COPEN1 (_U_(1) << TC_CTRLA_COPEN1_Pos) 134 #define TC_CTRLA_COPEN_Pos 20 /**< \brief (TC_CTRLA) Capture On Pin x Enable */ 135 #define TC_CTRLA_COPEN_Msk (_U_(0x3) << TC_CTRLA_COPEN_Pos) 136 #define TC_CTRLA_COPEN(value) (TC_CTRLA_COPEN_Msk & ((value) << TC_CTRLA_COPEN_Pos)) 137 #define TC_CTRLA_MASK _U_(0x00330FFF) /**< \brief (TC_CTRLA) MASK Register */ 138 139 /* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W 8) Control B Clear -------- */ 140 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 141 typedef union { 142 struct { 143 uint8_t DIR:1; /*!< bit: 0 Counter Direction */ 144 uint8_t LUPD:1; /*!< bit: 1 Lock Update */ 145 uint8_t ONESHOT:1; /*!< bit: 2 One-Shot on Counter */ 146 uint8_t :2; /*!< bit: 3.. 4 Reserved */ 147 uint8_t CMD:3; /*!< bit: 5.. 7 Command */ 148 } bit; /*!< Structure used for bit access */ 149 uint8_t reg; /*!< Type used for register access */ 150 } TC_CTRLBCLR_Type; 151 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 152 153 #define TC_CTRLBCLR_OFFSET 0x04 /**< \brief (TC_CTRLBCLR offset) Control B Clear */ 154 #define TC_CTRLBCLR_RESETVALUE _U_(0x00) /**< \brief (TC_CTRLBCLR reset_value) Control B Clear */ 155 156 #define TC_CTRLBCLR_DIR_Pos 0 /**< \brief (TC_CTRLBCLR) Counter Direction */ 157 #define TC_CTRLBCLR_DIR (_U_(0x1) << TC_CTRLBCLR_DIR_Pos) 158 #define TC_CTRLBCLR_LUPD_Pos 1 /**< \brief (TC_CTRLBCLR) Lock Update */ 159 #define TC_CTRLBCLR_LUPD (_U_(0x1) << TC_CTRLBCLR_LUPD_Pos) 160 #define TC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TC_CTRLBCLR) One-Shot on Counter */ 161 #define TC_CTRLBCLR_ONESHOT (_U_(0x1) << TC_CTRLBCLR_ONESHOT_Pos) 162 #define TC_CTRLBCLR_CMD_Pos 5 /**< \brief (TC_CTRLBCLR) Command */ 163 #define TC_CTRLBCLR_CMD_Msk (_U_(0x7) << TC_CTRLBCLR_CMD_Pos) 164 #define TC_CTRLBCLR_CMD(value) (TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos)) 165 #define TC_CTRLBCLR_CMD_NONE_Val _U_(0x0) /**< \brief (TC_CTRLBCLR) No action */ 166 #define TC_CTRLBCLR_CMD_RETRIGGER_Val _U_(0x1) /**< \brief (TC_CTRLBCLR) Force a start, restart or retrigger */ 167 #define TC_CTRLBCLR_CMD_STOP_Val _U_(0x2) /**< \brief (TC_CTRLBCLR) Force a stop */ 168 #define TC_CTRLBCLR_CMD_UPDATE_Val _U_(0x3) /**< \brief (TC_CTRLBCLR) Force update of double-buffered register */ 169 #define TC_CTRLBCLR_CMD_READSYNC_Val _U_(0x4) /**< \brief (TC_CTRLBCLR) Force a read synchronization of COUNT */ 170 #define TC_CTRLBCLR_CMD_DMAOS_Val _U_(0x5) /**< \brief (TC_CTRLBCLR) One-shot DMA trigger */ 171 #define TC_CTRLBCLR_CMD_NONE (TC_CTRLBCLR_CMD_NONE_Val << TC_CTRLBCLR_CMD_Pos) 172 #define TC_CTRLBCLR_CMD_RETRIGGER (TC_CTRLBCLR_CMD_RETRIGGER_Val << TC_CTRLBCLR_CMD_Pos) 173 #define TC_CTRLBCLR_CMD_STOP (TC_CTRLBCLR_CMD_STOP_Val << TC_CTRLBCLR_CMD_Pos) 174 #define TC_CTRLBCLR_CMD_UPDATE (TC_CTRLBCLR_CMD_UPDATE_Val << TC_CTRLBCLR_CMD_Pos) 175 #define TC_CTRLBCLR_CMD_READSYNC (TC_CTRLBCLR_CMD_READSYNC_Val << TC_CTRLBCLR_CMD_Pos) 176 #define TC_CTRLBCLR_CMD_DMAOS (TC_CTRLBCLR_CMD_DMAOS_Val << TC_CTRLBCLR_CMD_Pos) 177 #define TC_CTRLBCLR_MASK _U_(0xE7) /**< \brief (TC_CTRLBCLR) MASK Register */ 178 179 /* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W 8) Control B Set -------- */ 180 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 181 typedef union { 182 struct { 183 uint8_t DIR:1; /*!< bit: 0 Counter Direction */ 184 uint8_t LUPD:1; /*!< bit: 1 Lock Update */ 185 uint8_t ONESHOT:1; /*!< bit: 2 One-Shot on Counter */ 186 uint8_t :2; /*!< bit: 3.. 4 Reserved */ 187 uint8_t CMD:3; /*!< bit: 5.. 7 Command */ 188 } bit; /*!< Structure used for bit access */ 189 uint8_t reg; /*!< Type used for register access */ 190 } TC_CTRLBSET_Type; 191 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 192 193 #define TC_CTRLBSET_OFFSET 0x05 /**< \brief (TC_CTRLBSET offset) Control B Set */ 194 #define TC_CTRLBSET_RESETVALUE _U_(0x00) /**< \brief (TC_CTRLBSET reset_value) Control B Set */ 195 196 #define TC_CTRLBSET_DIR_Pos 0 /**< \brief (TC_CTRLBSET) Counter Direction */ 197 #define TC_CTRLBSET_DIR (_U_(0x1) << TC_CTRLBSET_DIR_Pos) 198 #define TC_CTRLBSET_LUPD_Pos 1 /**< \brief (TC_CTRLBSET) Lock Update */ 199 #define TC_CTRLBSET_LUPD (_U_(0x1) << TC_CTRLBSET_LUPD_Pos) 200 #define TC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TC_CTRLBSET) One-Shot on Counter */ 201 #define TC_CTRLBSET_ONESHOT (_U_(0x1) << TC_CTRLBSET_ONESHOT_Pos) 202 #define TC_CTRLBSET_CMD_Pos 5 /**< \brief (TC_CTRLBSET) Command */ 203 #define TC_CTRLBSET_CMD_Msk (_U_(0x7) << TC_CTRLBSET_CMD_Pos) 204 #define TC_CTRLBSET_CMD(value) (TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos)) 205 #define TC_CTRLBSET_CMD_NONE_Val _U_(0x0) /**< \brief (TC_CTRLBSET) No action */ 206 #define TC_CTRLBSET_CMD_RETRIGGER_Val _U_(0x1) /**< \brief (TC_CTRLBSET) Force a start, restart or retrigger */ 207 #define TC_CTRLBSET_CMD_STOP_Val _U_(0x2) /**< \brief (TC_CTRLBSET) Force a stop */ 208 #define TC_CTRLBSET_CMD_UPDATE_Val _U_(0x3) /**< \brief (TC_CTRLBSET) Force update of double-buffered register */ 209 #define TC_CTRLBSET_CMD_READSYNC_Val _U_(0x4) /**< \brief (TC_CTRLBSET) Force a read synchronization of COUNT */ 210 #define TC_CTRLBSET_CMD_DMAOS_Val _U_(0x5) /**< \brief (TC_CTRLBSET) One-shot DMA trigger */ 211 #define TC_CTRLBSET_CMD_NONE (TC_CTRLBSET_CMD_NONE_Val << TC_CTRLBSET_CMD_Pos) 212 #define TC_CTRLBSET_CMD_RETRIGGER (TC_CTRLBSET_CMD_RETRIGGER_Val << TC_CTRLBSET_CMD_Pos) 213 #define TC_CTRLBSET_CMD_STOP (TC_CTRLBSET_CMD_STOP_Val << TC_CTRLBSET_CMD_Pos) 214 #define TC_CTRLBSET_CMD_UPDATE (TC_CTRLBSET_CMD_UPDATE_Val << TC_CTRLBSET_CMD_Pos) 215 #define TC_CTRLBSET_CMD_READSYNC (TC_CTRLBSET_CMD_READSYNC_Val << TC_CTRLBSET_CMD_Pos) 216 #define TC_CTRLBSET_CMD_DMAOS (TC_CTRLBSET_CMD_DMAOS_Val << TC_CTRLBSET_CMD_Pos) 217 #define TC_CTRLBSET_MASK _U_(0xE7) /**< \brief (TC_CTRLBSET) MASK Register */ 218 219 /* -------- TC_EVCTRL : (TC Offset: 0x06) (R/W 16) Event Control -------- */ 220 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 221 typedef union { 222 struct { 223 uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */ 224 uint16_t :1; /*!< bit: 3 Reserved */ 225 uint16_t TCINV:1; /*!< bit: 4 TC Event Input Polarity */ 226 uint16_t TCEI:1; /*!< bit: 5 TC Event Enable */ 227 uint16_t :2; /*!< bit: 6.. 7 Reserved */ 228 uint16_t OVFEO:1; /*!< bit: 8 Event Output Enable */ 229 uint16_t :3; /*!< bit: 9..11 Reserved */ 230 uint16_t MCEO0:1; /*!< bit: 12 MC Event Output Enable 0 */ 231 uint16_t MCEO1:1; /*!< bit: 13 MC Event Output Enable 1 */ 232 uint16_t :2; /*!< bit: 14..15 Reserved */ 233 } bit; /*!< Structure used for bit access */ 234 struct { 235 uint16_t :12; /*!< bit: 0..11 Reserved */ 236 uint16_t MCEO:2; /*!< bit: 12..13 MC Event Output Enable x */ 237 uint16_t :2; /*!< bit: 14..15 Reserved */ 238 } vec; /*!< Structure used for vec access */ 239 uint16_t reg; /*!< Type used for register access */ 240 } TC_EVCTRL_Type; 241 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 242 243 #define TC_EVCTRL_OFFSET 0x06 /**< \brief (TC_EVCTRL offset) Event Control */ 244 #define TC_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (TC_EVCTRL reset_value) Event Control */ 245 246 #define TC_EVCTRL_EVACT_Pos 0 /**< \brief (TC_EVCTRL) Event Action */ 247 #define TC_EVCTRL_EVACT_Msk (_U_(0x7) << TC_EVCTRL_EVACT_Pos) 248 #define TC_EVCTRL_EVACT(value) (TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos)) 249 #define TC_EVCTRL_EVACT_OFF_Val _U_(0x0) /**< \brief (TC_EVCTRL) Event action disabled */ 250 #define TC_EVCTRL_EVACT_RETRIGGER_Val _U_(0x1) /**< \brief (TC_EVCTRL) Start, restart or retrigger TC on event */ 251 #define TC_EVCTRL_EVACT_COUNT_Val _U_(0x2) /**< \brief (TC_EVCTRL) Count on event */ 252 #define TC_EVCTRL_EVACT_START_Val _U_(0x3) /**< \brief (TC_EVCTRL) Start TC on event */ 253 #define TC_EVCTRL_EVACT_STAMP_Val _U_(0x4) /**< \brief (TC_EVCTRL) Time stamp capture */ 254 #define TC_EVCTRL_EVACT_PPW_Val _U_(0x5) /**< \brief (TC_EVCTRL) Period catured in CC0, pulse width in CC1 */ 255 #define TC_EVCTRL_EVACT_PWP_Val _U_(0x6) /**< \brief (TC_EVCTRL) Period catured in CC1, pulse width in CC0 */ 256 #define TC_EVCTRL_EVACT_PW_Val _U_(0x7) /**< \brief (TC_EVCTRL) Pulse width capture */ 257 #define TC_EVCTRL_EVACT_OFF (TC_EVCTRL_EVACT_OFF_Val << TC_EVCTRL_EVACT_Pos) 258 #define TC_EVCTRL_EVACT_RETRIGGER (TC_EVCTRL_EVACT_RETRIGGER_Val << TC_EVCTRL_EVACT_Pos) 259 #define TC_EVCTRL_EVACT_COUNT (TC_EVCTRL_EVACT_COUNT_Val << TC_EVCTRL_EVACT_Pos) 260 #define TC_EVCTRL_EVACT_START (TC_EVCTRL_EVACT_START_Val << TC_EVCTRL_EVACT_Pos) 261 #define TC_EVCTRL_EVACT_STAMP (TC_EVCTRL_EVACT_STAMP_Val << TC_EVCTRL_EVACT_Pos) 262 #define TC_EVCTRL_EVACT_PPW (TC_EVCTRL_EVACT_PPW_Val << TC_EVCTRL_EVACT_Pos) 263 #define TC_EVCTRL_EVACT_PWP (TC_EVCTRL_EVACT_PWP_Val << TC_EVCTRL_EVACT_Pos) 264 #define TC_EVCTRL_EVACT_PW (TC_EVCTRL_EVACT_PW_Val << TC_EVCTRL_EVACT_Pos) 265 #define TC_EVCTRL_TCINV_Pos 4 /**< \brief (TC_EVCTRL) TC Event Input Polarity */ 266 #define TC_EVCTRL_TCINV (_U_(0x1) << TC_EVCTRL_TCINV_Pos) 267 #define TC_EVCTRL_TCEI_Pos 5 /**< \brief (TC_EVCTRL) TC Event Enable */ 268 #define TC_EVCTRL_TCEI (_U_(0x1) << TC_EVCTRL_TCEI_Pos) 269 #define TC_EVCTRL_OVFEO_Pos 8 /**< \brief (TC_EVCTRL) Event Output Enable */ 270 #define TC_EVCTRL_OVFEO (_U_(0x1) << TC_EVCTRL_OVFEO_Pos) 271 #define TC_EVCTRL_MCEO0_Pos 12 /**< \brief (TC_EVCTRL) MC Event Output Enable 0 */ 272 #define TC_EVCTRL_MCEO0 (_U_(1) << TC_EVCTRL_MCEO0_Pos) 273 #define TC_EVCTRL_MCEO1_Pos 13 /**< \brief (TC_EVCTRL) MC Event Output Enable 1 */ 274 #define TC_EVCTRL_MCEO1 (_U_(1) << TC_EVCTRL_MCEO1_Pos) 275 #define TC_EVCTRL_MCEO_Pos 12 /**< \brief (TC_EVCTRL) MC Event Output Enable x */ 276 #define TC_EVCTRL_MCEO_Msk (_U_(0x3) << TC_EVCTRL_MCEO_Pos) 277 #define TC_EVCTRL_MCEO(value) (TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos)) 278 #define TC_EVCTRL_MASK _U_(0x3137) /**< \brief (TC_EVCTRL) MASK Register */ 279 280 /* -------- TC_INTENCLR : (TC Offset: 0x08) (R/W 8) Interrupt Enable Clear -------- */ 281 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 282 typedef union { 283 struct { 284 uint8_t OVF:1; /*!< bit: 0 OVF Interrupt Disable */ 285 uint8_t ERR:1; /*!< bit: 1 ERR Interrupt Disable */ 286 uint8_t :2; /*!< bit: 2.. 3 Reserved */ 287 uint8_t MC0:1; /*!< bit: 4 MC Interrupt Disable 0 */ 288 uint8_t MC1:1; /*!< bit: 5 MC Interrupt Disable 1 */ 289 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 290 } bit; /*!< Structure used for bit access */ 291 struct { 292 uint8_t :4; /*!< bit: 0.. 3 Reserved */ 293 uint8_t MC:2; /*!< bit: 4.. 5 MC Interrupt Disable x */ 294 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 295 } vec; /*!< Structure used for vec access */ 296 uint8_t reg; /*!< Type used for register access */ 297 } TC_INTENCLR_Type; 298 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 299 300 #define TC_INTENCLR_OFFSET 0x08 /**< \brief (TC_INTENCLR offset) Interrupt Enable Clear */ 301 #define TC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (TC_INTENCLR reset_value) Interrupt Enable Clear */ 302 303 #define TC_INTENCLR_OVF_Pos 0 /**< \brief (TC_INTENCLR) OVF Interrupt Disable */ 304 #define TC_INTENCLR_OVF (_U_(0x1) << TC_INTENCLR_OVF_Pos) 305 #define TC_INTENCLR_ERR_Pos 1 /**< \brief (TC_INTENCLR) ERR Interrupt Disable */ 306 #define TC_INTENCLR_ERR (_U_(0x1) << TC_INTENCLR_ERR_Pos) 307 #define TC_INTENCLR_MC0_Pos 4 /**< \brief (TC_INTENCLR) MC Interrupt Disable 0 */ 308 #define TC_INTENCLR_MC0 (_U_(1) << TC_INTENCLR_MC0_Pos) 309 #define TC_INTENCLR_MC1_Pos 5 /**< \brief (TC_INTENCLR) MC Interrupt Disable 1 */ 310 #define TC_INTENCLR_MC1 (_U_(1) << TC_INTENCLR_MC1_Pos) 311 #define TC_INTENCLR_MC_Pos 4 /**< \brief (TC_INTENCLR) MC Interrupt Disable x */ 312 #define TC_INTENCLR_MC_Msk (_U_(0x3) << TC_INTENCLR_MC_Pos) 313 #define TC_INTENCLR_MC(value) (TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos)) 314 #define TC_INTENCLR_MASK _U_(0x33) /**< \brief (TC_INTENCLR) MASK Register */ 315 316 /* -------- TC_INTENSET : (TC Offset: 0x09) (R/W 8) Interrupt Enable Set -------- */ 317 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 318 typedef union { 319 struct { 320 uint8_t OVF:1; /*!< bit: 0 OVF Interrupt Enable */ 321 uint8_t ERR:1; /*!< bit: 1 ERR Interrupt Enable */ 322 uint8_t :2; /*!< bit: 2.. 3 Reserved */ 323 uint8_t MC0:1; /*!< bit: 4 MC Interrupt Enable 0 */ 324 uint8_t MC1:1; /*!< bit: 5 MC Interrupt Enable 1 */ 325 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 326 } bit; /*!< Structure used for bit access */ 327 struct { 328 uint8_t :4; /*!< bit: 0.. 3 Reserved */ 329 uint8_t MC:2; /*!< bit: 4.. 5 MC Interrupt Enable x */ 330 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 331 } vec; /*!< Structure used for vec access */ 332 uint8_t reg; /*!< Type used for register access */ 333 } TC_INTENSET_Type; 334 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 335 336 #define TC_INTENSET_OFFSET 0x09 /**< \brief (TC_INTENSET offset) Interrupt Enable Set */ 337 #define TC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (TC_INTENSET reset_value) Interrupt Enable Set */ 338 339 #define TC_INTENSET_OVF_Pos 0 /**< \brief (TC_INTENSET) OVF Interrupt Enable */ 340 #define TC_INTENSET_OVF (_U_(0x1) << TC_INTENSET_OVF_Pos) 341 #define TC_INTENSET_ERR_Pos 1 /**< \brief (TC_INTENSET) ERR Interrupt Enable */ 342 #define TC_INTENSET_ERR (_U_(0x1) << TC_INTENSET_ERR_Pos) 343 #define TC_INTENSET_MC0_Pos 4 /**< \brief (TC_INTENSET) MC Interrupt Enable 0 */ 344 #define TC_INTENSET_MC0 (_U_(1) << TC_INTENSET_MC0_Pos) 345 #define TC_INTENSET_MC1_Pos 5 /**< \brief (TC_INTENSET) MC Interrupt Enable 1 */ 346 #define TC_INTENSET_MC1 (_U_(1) << TC_INTENSET_MC1_Pos) 347 #define TC_INTENSET_MC_Pos 4 /**< \brief (TC_INTENSET) MC Interrupt Enable x */ 348 #define TC_INTENSET_MC_Msk (_U_(0x3) << TC_INTENSET_MC_Pos) 349 #define TC_INTENSET_MC(value) (TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos)) 350 #define TC_INTENSET_MASK _U_(0x33) /**< \brief (TC_INTENSET) MASK Register */ 351 352 /* -------- TC_INTFLAG : (TC Offset: 0x0A) (R/W 8) Interrupt Flag Status and Clear -------- */ 353 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 354 typedef union { // __I to avoid read-modify-write on write-to-clear register 355 struct { 356 __I uint8_t OVF:1; /*!< bit: 0 OVF Interrupt Flag */ 357 __I uint8_t ERR:1; /*!< bit: 1 ERR Interrupt Flag */ 358 __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ 359 __I uint8_t MC0:1; /*!< bit: 4 MC Interrupt Flag 0 */ 360 __I uint8_t MC1:1; /*!< bit: 5 MC Interrupt Flag 1 */ 361 __I uint8_t :2; /*!< bit: 6.. 7 Reserved */ 362 } bit; /*!< Structure used for bit access */ 363 struct { 364 __I uint8_t :4; /*!< bit: 0.. 3 Reserved */ 365 __I uint8_t MC:2; /*!< bit: 4.. 5 MC Interrupt Flag x */ 366 __I uint8_t :2; /*!< bit: 6.. 7 Reserved */ 367 } vec; /*!< Structure used for vec access */ 368 uint8_t reg; /*!< Type used for register access */ 369 } TC_INTFLAG_Type; 370 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 371 372 #define TC_INTFLAG_OFFSET 0x0A /**< \brief (TC_INTFLAG offset) Interrupt Flag Status and Clear */ 373 #define TC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (TC_INTFLAG reset_value) Interrupt Flag Status and Clear */ 374 375 #define TC_INTFLAG_OVF_Pos 0 /**< \brief (TC_INTFLAG) OVF Interrupt Flag */ 376 #define TC_INTFLAG_OVF (_U_(0x1) << TC_INTFLAG_OVF_Pos) 377 #define TC_INTFLAG_ERR_Pos 1 /**< \brief (TC_INTFLAG) ERR Interrupt Flag */ 378 #define TC_INTFLAG_ERR (_U_(0x1) << TC_INTFLAG_ERR_Pos) 379 #define TC_INTFLAG_MC0_Pos 4 /**< \brief (TC_INTFLAG) MC Interrupt Flag 0 */ 380 #define TC_INTFLAG_MC0 (_U_(1) << TC_INTFLAG_MC0_Pos) 381 #define TC_INTFLAG_MC1_Pos 5 /**< \brief (TC_INTFLAG) MC Interrupt Flag 1 */ 382 #define TC_INTFLAG_MC1 (_U_(1) << TC_INTFLAG_MC1_Pos) 383 #define TC_INTFLAG_MC_Pos 4 /**< \brief (TC_INTFLAG) MC Interrupt Flag x */ 384 #define TC_INTFLAG_MC_Msk (_U_(0x3) << TC_INTFLAG_MC_Pos) 385 #define TC_INTFLAG_MC(value) (TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos)) 386 #define TC_INTFLAG_MASK _U_(0x33) /**< \brief (TC_INTFLAG) MASK Register */ 387 388 /* -------- TC_STATUS : (TC Offset: 0x0B) (R/W 8) Status -------- */ 389 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 390 typedef union { 391 struct { 392 uint8_t STOP:1; /*!< bit: 0 Stop Status Flag */ 393 uint8_t SLAVE:1; /*!< bit: 1 Slave Status Flag */ 394 uint8_t :1; /*!< bit: 2 Reserved */ 395 uint8_t PERBUFV:1; /*!< bit: 3 Synchronization Busy Status */ 396 uint8_t CCBUFV0:1; /*!< bit: 4 Compare channel buffer 0 valid */ 397 uint8_t CCBUFV1:1; /*!< bit: 5 Compare channel buffer 1 valid */ 398 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 399 } bit; /*!< Structure used for bit access */ 400 struct { 401 uint8_t :4; /*!< bit: 0.. 3 Reserved */ 402 uint8_t CCBUFV:2; /*!< bit: 4.. 5 Compare channel buffer x valid */ 403 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 404 } vec; /*!< Structure used for vec access */ 405 uint8_t reg; /*!< Type used for register access */ 406 } TC_STATUS_Type; 407 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 408 409 #define TC_STATUS_OFFSET 0x0B /**< \brief (TC_STATUS offset) Status */ 410 #define TC_STATUS_RESETVALUE _U_(0x01) /**< \brief (TC_STATUS reset_value) Status */ 411 412 #define TC_STATUS_STOP_Pos 0 /**< \brief (TC_STATUS) Stop Status Flag */ 413 #define TC_STATUS_STOP (_U_(0x1) << TC_STATUS_STOP_Pos) 414 #define TC_STATUS_SLAVE_Pos 1 /**< \brief (TC_STATUS) Slave Status Flag */ 415 #define TC_STATUS_SLAVE (_U_(0x1) << TC_STATUS_SLAVE_Pos) 416 #define TC_STATUS_PERBUFV_Pos 3 /**< \brief (TC_STATUS) Synchronization Busy Status */ 417 #define TC_STATUS_PERBUFV (_U_(0x1) << TC_STATUS_PERBUFV_Pos) 418 #define TC_STATUS_CCBUFV0_Pos 4 /**< \brief (TC_STATUS) Compare channel buffer 0 valid */ 419 #define TC_STATUS_CCBUFV0 (_U_(1) << TC_STATUS_CCBUFV0_Pos) 420 #define TC_STATUS_CCBUFV1_Pos 5 /**< \brief (TC_STATUS) Compare channel buffer 1 valid */ 421 #define TC_STATUS_CCBUFV1 (_U_(1) << TC_STATUS_CCBUFV1_Pos) 422 #define TC_STATUS_CCBUFV_Pos 4 /**< \brief (TC_STATUS) Compare channel buffer x valid */ 423 #define TC_STATUS_CCBUFV_Msk (_U_(0x3) << TC_STATUS_CCBUFV_Pos) 424 #define TC_STATUS_CCBUFV(value) (TC_STATUS_CCBUFV_Msk & ((value) << TC_STATUS_CCBUFV_Pos)) 425 #define TC_STATUS_MASK _U_(0x3B) /**< \brief (TC_STATUS) MASK Register */ 426 427 /* -------- TC_WAVE : (TC Offset: 0x0C) (R/W 8) Waveform Generation Control -------- */ 428 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 429 typedef union { 430 struct { 431 uint8_t WAVEGEN:2; /*!< bit: 0.. 1 Waveform Generation Mode */ 432 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 433 } bit; /*!< Structure used for bit access */ 434 uint8_t reg; /*!< Type used for register access */ 435 } TC_WAVE_Type; 436 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 437 438 #define TC_WAVE_OFFSET 0x0C /**< \brief (TC_WAVE offset) Waveform Generation Control */ 439 #define TC_WAVE_RESETVALUE _U_(0x00) /**< \brief (TC_WAVE reset_value) Waveform Generation Control */ 440 441 #define TC_WAVE_WAVEGEN_Pos 0 /**< \brief (TC_WAVE) Waveform Generation Mode */ 442 #define TC_WAVE_WAVEGEN_Msk (_U_(0x3) << TC_WAVE_WAVEGEN_Pos) 443 #define TC_WAVE_WAVEGEN(value) (TC_WAVE_WAVEGEN_Msk & ((value) << TC_WAVE_WAVEGEN_Pos)) 444 #define TC_WAVE_WAVEGEN_NFRQ_Val _U_(0x0) /**< \brief (TC_WAVE) Normal frequency */ 445 #define TC_WAVE_WAVEGEN_MFRQ_Val _U_(0x1) /**< \brief (TC_WAVE) Match frequency */ 446 #define TC_WAVE_WAVEGEN_NPWM_Val _U_(0x2) /**< \brief (TC_WAVE) Normal PWM */ 447 #define TC_WAVE_WAVEGEN_MPWM_Val _U_(0x3) /**< \brief (TC_WAVE) Match PWM */ 448 #define TC_WAVE_WAVEGEN_NFRQ (TC_WAVE_WAVEGEN_NFRQ_Val << TC_WAVE_WAVEGEN_Pos) 449 #define TC_WAVE_WAVEGEN_MFRQ (TC_WAVE_WAVEGEN_MFRQ_Val << TC_WAVE_WAVEGEN_Pos) 450 #define TC_WAVE_WAVEGEN_NPWM (TC_WAVE_WAVEGEN_NPWM_Val << TC_WAVE_WAVEGEN_Pos) 451 #define TC_WAVE_WAVEGEN_MPWM (TC_WAVE_WAVEGEN_MPWM_Val << TC_WAVE_WAVEGEN_Pos) 452 #define TC_WAVE_MASK _U_(0x03) /**< \brief (TC_WAVE) MASK Register */ 453 454 /* -------- TC_DRVCTRL : (TC Offset: 0x0D) (R/W 8) Control C -------- */ 455 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 456 typedef union { 457 struct { 458 uint8_t INVEN0:1; /*!< bit: 0 Output Waveform Invert Enable 0 */ 459 uint8_t INVEN1:1; /*!< bit: 1 Output Waveform Invert Enable 1 */ 460 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 461 } bit; /*!< Structure used for bit access */ 462 struct { 463 uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform Invert Enable x */ 464 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 465 } vec; /*!< Structure used for vec access */ 466 uint8_t reg; /*!< Type used for register access */ 467 } TC_DRVCTRL_Type; 468 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 469 470 #define TC_DRVCTRL_OFFSET 0x0D /**< \brief (TC_DRVCTRL offset) Control C */ 471 #define TC_DRVCTRL_RESETVALUE _U_(0x00) /**< \brief (TC_DRVCTRL reset_value) Control C */ 472 473 #define TC_DRVCTRL_INVEN0_Pos 0 /**< \brief (TC_DRVCTRL) Output Waveform Invert Enable 0 */ 474 #define TC_DRVCTRL_INVEN0 (_U_(1) << TC_DRVCTRL_INVEN0_Pos) 475 #define TC_DRVCTRL_INVEN1_Pos 1 /**< \brief (TC_DRVCTRL) Output Waveform Invert Enable 1 */ 476 #define TC_DRVCTRL_INVEN1 (_U_(1) << TC_DRVCTRL_INVEN1_Pos) 477 #define TC_DRVCTRL_INVEN_Pos 0 /**< \brief (TC_DRVCTRL) Output Waveform Invert Enable x */ 478 #define TC_DRVCTRL_INVEN_Msk (_U_(0x3) << TC_DRVCTRL_INVEN_Pos) 479 #define TC_DRVCTRL_INVEN(value) (TC_DRVCTRL_INVEN_Msk & ((value) << TC_DRVCTRL_INVEN_Pos)) 480 #define TC_DRVCTRL_MASK _U_(0x03) /**< \brief (TC_DRVCTRL) MASK Register */ 481 482 /* -------- TC_DBGCTRL : (TC Offset: 0x0F) (R/W 8) Debug Control -------- */ 483 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 484 typedef union { 485 struct { 486 uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */ 487 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 488 } bit; /*!< Structure used for bit access */ 489 uint8_t reg; /*!< Type used for register access */ 490 } TC_DBGCTRL_Type; 491 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 492 493 #define TC_DBGCTRL_OFFSET 0x0F /**< \brief (TC_DBGCTRL offset) Debug Control */ 494 #define TC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (TC_DBGCTRL reset_value) Debug Control */ 495 496 #define TC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TC_DBGCTRL) Run During Debug */ 497 #define TC_DBGCTRL_DBGRUN (_U_(0x1) << TC_DBGCTRL_DBGRUN_Pos) 498 #define TC_DBGCTRL_MASK _U_(0x01) /**< \brief (TC_DBGCTRL) MASK Register */ 499 500 /* -------- TC_SYNCBUSY : (TC Offset: 0x10) (R/ 32) Synchronization Status -------- */ 501 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 502 typedef union { 503 struct { 504 uint32_t SWRST:1; /*!< bit: 0 swrst */ 505 uint32_t ENABLE:1; /*!< bit: 1 enable */ 506 uint32_t CTRLB:1; /*!< bit: 2 CTRLB */ 507 uint32_t STATUS:1; /*!< bit: 3 STATUS */ 508 uint32_t COUNT:1; /*!< bit: 4 Counter */ 509 uint32_t PER:1; /*!< bit: 5 Period */ 510 uint32_t CC0:1; /*!< bit: 6 Compare Channel 0 */ 511 uint32_t CC1:1; /*!< bit: 7 Compare Channel 1 */ 512 uint32_t :24; /*!< bit: 8..31 Reserved */ 513 } bit; /*!< Structure used for bit access */ 514 struct { 515 uint32_t :6; /*!< bit: 0.. 5 Reserved */ 516 uint32_t CC:2; /*!< bit: 6.. 7 Compare Channel x */ 517 uint32_t :24; /*!< bit: 8..31 Reserved */ 518 } vec; /*!< Structure used for vec access */ 519 uint32_t reg; /*!< Type used for register access */ 520 } TC_SYNCBUSY_Type; 521 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 522 523 #define TC_SYNCBUSY_OFFSET 0x10 /**< \brief (TC_SYNCBUSY offset) Synchronization Status */ 524 #define TC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (TC_SYNCBUSY reset_value) Synchronization Status */ 525 526 #define TC_SYNCBUSY_SWRST_Pos 0 /**< \brief (TC_SYNCBUSY) swrst */ 527 #define TC_SYNCBUSY_SWRST (_U_(0x1) << TC_SYNCBUSY_SWRST_Pos) 528 #define TC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (TC_SYNCBUSY) enable */ 529 #define TC_SYNCBUSY_ENABLE (_U_(0x1) << TC_SYNCBUSY_ENABLE_Pos) 530 #define TC_SYNCBUSY_CTRLB_Pos 2 /**< \brief (TC_SYNCBUSY) CTRLB */ 531 #define TC_SYNCBUSY_CTRLB (_U_(0x1) << TC_SYNCBUSY_CTRLB_Pos) 532 #define TC_SYNCBUSY_STATUS_Pos 3 /**< \brief (TC_SYNCBUSY) STATUS */ 533 #define TC_SYNCBUSY_STATUS (_U_(0x1) << TC_SYNCBUSY_STATUS_Pos) 534 #define TC_SYNCBUSY_COUNT_Pos 4 /**< \brief (TC_SYNCBUSY) Counter */ 535 #define TC_SYNCBUSY_COUNT (_U_(0x1) << TC_SYNCBUSY_COUNT_Pos) 536 #define TC_SYNCBUSY_PER_Pos 5 /**< \brief (TC_SYNCBUSY) Period */ 537 #define TC_SYNCBUSY_PER (_U_(0x1) << TC_SYNCBUSY_PER_Pos) 538 #define TC_SYNCBUSY_CC0_Pos 6 /**< \brief (TC_SYNCBUSY) Compare Channel 0 */ 539 #define TC_SYNCBUSY_CC0 (_U_(1) << TC_SYNCBUSY_CC0_Pos) 540 #define TC_SYNCBUSY_CC1_Pos 7 /**< \brief (TC_SYNCBUSY) Compare Channel 1 */ 541 #define TC_SYNCBUSY_CC1 (_U_(1) << TC_SYNCBUSY_CC1_Pos) 542 #define TC_SYNCBUSY_CC_Pos 6 /**< \brief (TC_SYNCBUSY) Compare Channel x */ 543 #define TC_SYNCBUSY_CC_Msk (_U_(0x3) << TC_SYNCBUSY_CC_Pos) 544 #define TC_SYNCBUSY_CC(value) (TC_SYNCBUSY_CC_Msk & ((value) << TC_SYNCBUSY_CC_Pos)) 545 #define TC_SYNCBUSY_MASK _U_(0x000000FF) /**< \brief (TC_SYNCBUSY) MASK Register */ 546 547 /* -------- TC_COUNT16_COUNT : (TC Offset: 0x14) (R/W 16) COUNT16 COUNT16 Count -------- */ 548 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 549 typedef union { 550 struct { 551 uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */ 552 } bit; /*!< Structure used for bit access */ 553 uint16_t reg; /*!< Type used for register access */ 554 } TC_COUNT16_COUNT_Type; 555 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 556 557 #define TC_COUNT16_COUNT_OFFSET 0x14 /**< \brief (TC_COUNT16_COUNT offset) COUNT16 Count */ 558 #define TC_COUNT16_COUNT_RESETVALUE _U_(0x0000) /**< \brief (TC_COUNT16_COUNT reset_value) COUNT16 Count */ 559 560 #define TC_COUNT16_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT16_COUNT) Counter Value */ 561 #define TC_COUNT16_COUNT_COUNT_Msk (_U_(0xFFFF) << TC_COUNT16_COUNT_COUNT_Pos) 562 #define TC_COUNT16_COUNT_COUNT(value) (TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos)) 563 #define TC_COUNT16_COUNT_MASK _U_(0xFFFF) /**< \brief (TC_COUNT16_COUNT) MASK Register */ 564 565 /* -------- TC_COUNT32_COUNT : (TC Offset: 0x14) (R/W 32) COUNT32 COUNT32 Count -------- */ 566 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 567 typedef union { 568 struct { 569 uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */ 570 } bit; /*!< Structure used for bit access */ 571 uint32_t reg; /*!< Type used for register access */ 572 } TC_COUNT32_COUNT_Type; 573 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 574 575 #define TC_COUNT32_COUNT_OFFSET 0x14 /**< \brief (TC_COUNT32_COUNT offset) COUNT32 Count */ 576 #define TC_COUNT32_COUNT_RESETVALUE _U_(0x00000000) /**< \brief (TC_COUNT32_COUNT reset_value) COUNT32 Count */ 577 578 #define TC_COUNT32_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT32_COUNT) Counter Value */ 579 #define TC_COUNT32_COUNT_COUNT_Msk (_U_(0xFFFFFFFF) << TC_COUNT32_COUNT_COUNT_Pos) 580 #define TC_COUNT32_COUNT_COUNT(value) (TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos)) 581 #define TC_COUNT32_COUNT_MASK _U_(0xFFFFFFFF) /**< \brief (TC_COUNT32_COUNT) MASK Register */ 582 583 /* -------- TC_COUNT8_COUNT : (TC Offset: 0x14) (R/W 8) COUNT8 COUNT8 Count -------- */ 584 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 585 typedef union { 586 struct { 587 uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */ 588 } bit; /*!< Structure used for bit access */ 589 uint8_t reg; /*!< Type used for register access */ 590 } TC_COUNT8_COUNT_Type; 591 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 592 593 #define TC_COUNT8_COUNT_OFFSET 0x14 /**< \brief (TC_COUNT8_COUNT offset) COUNT8 Count */ 594 #define TC_COUNT8_COUNT_RESETVALUE _U_(0x00) /**< \brief (TC_COUNT8_COUNT reset_value) COUNT8 Count */ 595 596 #define TC_COUNT8_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT8_COUNT) Counter Value */ 597 #define TC_COUNT8_COUNT_COUNT_Msk (_U_(0xFF) << TC_COUNT8_COUNT_COUNT_Pos) 598 #define TC_COUNT8_COUNT_COUNT(value) (TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos)) 599 #define TC_COUNT8_COUNT_MASK _U_(0xFF) /**< \brief (TC_COUNT8_COUNT) MASK Register */ 600 601 /* -------- TC_COUNT8_PER : (TC Offset: 0x1B) (R/W 8) COUNT8 COUNT8 Period -------- */ 602 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 603 typedef union { 604 struct { 605 uint8_t PER:8; /*!< bit: 0.. 7 Period Value */ 606 } bit; /*!< Structure used for bit access */ 607 uint8_t reg; /*!< Type used for register access */ 608 } TC_COUNT8_PER_Type; 609 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 610 611 #define TC_COUNT8_PER_OFFSET 0x1B /**< \brief (TC_COUNT8_PER offset) COUNT8 Period */ 612 #define TC_COUNT8_PER_RESETVALUE _U_(0xFF) /**< \brief (TC_COUNT8_PER reset_value) COUNT8 Period */ 613 614 #define TC_COUNT8_PER_PER_Pos 0 /**< \brief (TC_COUNT8_PER) Period Value */ 615 #define TC_COUNT8_PER_PER_Msk (_U_(0xFF) << TC_COUNT8_PER_PER_Pos) 616 #define TC_COUNT8_PER_PER(value) (TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos)) 617 #define TC_COUNT8_PER_MASK _U_(0xFF) /**< \brief (TC_COUNT8_PER) MASK Register */ 618 619 /* -------- TC_COUNT16_CC : (TC Offset: 0x1C) (R/W 16) COUNT16 COUNT16 Compare and Capture -------- */ 620 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 621 typedef union { 622 struct { 623 uint16_t CC:16; /*!< bit: 0..15 Counter/Compare Value */ 624 } bit; /*!< Structure used for bit access */ 625 uint16_t reg; /*!< Type used for register access */ 626 } TC_COUNT16_CC_Type; 627 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 628 629 #define TC_COUNT16_CC_OFFSET 0x1C /**< \brief (TC_COUNT16_CC offset) COUNT16 Compare and Capture */ 630 #define TC_COUNT16_CC_RESETVALUE _U_(0x0000) /**< \brief (TC_COUNT16_CC reset_value) COUNT16 Compare and Capture */ 631 632 #define TC_COUNT16_CC_CC_Pos 0 /**< \brief (TC_COUNT16_CC) Counter/Compare Value */ 633 #define TC_COUNT16_CC_CC_Msk (_U_(0xFFFF) << TC_COUNT16_CC_CC_Pos) 634 #define TC_COUNT16_CC_CC(value) (TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos)) 635 #define TC_COUNT16_CC_MASK _U_(0xFFFF) /**< \brief (TC_COUNT16_CC) MASK Register */ 636 637 /* -------- TC_COUNT32_CC : (TC Offset: 0x1C) (R/W 32) COUNT32 COUNT32 Compare and Capture -------- */ 638 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 639 typedef union { 640 struct { 641 uint32_t CC:32; /*!< bit: 0..31 Counter/Compare Value */ 642 } bit; /*!< Structure used for bit access */ 643 uint32_t reg; /*!< Type used for register access */ 644 } TC_COUNT32_CC_Type; 645 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 646 647 #define TC_COUNT32_CC_OFFSET 0x1C /**< \brief (TC_COUNT32_CC offset) COUNT32 Compare and Capture */ 648 #define TC_COUNT32_CC_RESETVALUE _U_(0x00000000) /**< \brief (TC_COUNT32_CC reset_value) COUNT32 Compare and Capture */ 649 650 #define TC_COUNT32_CC_CC_Pos 0 /**< \brief (TC_COUNT32_CC) Counter/Compare Value */ 651 #define TC_COUNT32_CC_CC_Msk (_U_(0xFFFFFFFF) << TC_COUNT32_CC_CC_Pos) 652 #define TC_COUNT32_CC_CC(value) (TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos)) 653 #define TC_COUNT32_CC_MASK _U_(0xFFFFFFFF) /**< \brief (TC_COUNT32_CC) MASK Register */ 654 655 /* -------- TC_COUNT8_CC : (TC Offset: 0x1C) (R/W 8) COUNT8 COUNT8 Compare and Capture -------- */ 656 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 657 typedef union { 658 struct { 659 uint8_t CC:8; /*!< bit: 0.. 7 Counter/Compare Value */ 660 } bit; /*!< Structure used for bit access */ 661 uint8_t reg; /*!< Type used for register access */ 662 } TC_COUNT8_CC_Type; 663 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 664 665 #define TC_COUNT8_CC_OFFSET 0x1C /**< \brief (TC_COUNT8_CC offset) COUNT8 Compare and Capture */ 666 #define TC_COUNT8_CC_RESETVALUE _U_(0x00) /**< \brief (TC_COUNT8_CC reset_value) COUNT8 Compare and Capture */ 667 668 #define TC_COUNT8_CC_CC_Pos 0 /**< \brief (TC_COUNT8_CC) Counter/Compare Value */ 669 #define TC_COUNT8_CC_CC_Msk (_U_(0xFF) << TC_COUNT8_CC_CC_Pos) 670 #define TC_COUNT8_CC_CC(value) (TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos)) 671 #define TC_COUNT8_CC_MASK _U_(0xFF) /**< \brief (TC_COUNT8_CC) MASK Register */ 672 673 /* -------- TC_COUNT8_PERBUF : (TC Offset: 0x2F) (R/W 8) COUNT8 COUNT8 Period Buffer -------- */ 674 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 675 typedef union { 676 struct { 677 uint8_t PERBUF:8; /*!< bit: 0.. 7 Period Buffer Value */ 678 } bit; /*!< Structure used for bit access */ 679 uint8_t reg; /*!< Type used for register access */ 680 } TC_COUNT8_PERBUF_Type; 681 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 682 683 #define TC_COUNT8_PERBUF_OFFSET 0x2F /**< \brief (TC_COUNT8_PERBUF offset) COUNT8 Period Buffer */ 684 #define TC_COUNT8_PERBUF_RESETVALUE _U_(0xFF) /**< \brief (TC_COUNT8_PERBUF reset_value) COUNT8 Period Buffer */ 685 686 #define TC_COUNT8_PERBUF_PERBUF_Pos 0 /**< \brief (TC_COUNT8_PERBUF) Period Buffer Value */ 687 #define TC_COUNT8_PERBUF_PERBUF_Msk (_U_(0xFF) << TC_COUNT8_PERBUF_PERBUF_Pos) 688 #define TC_COUNT8_PERBUF_PERBUF(value) (TC_COUNT8_PERBUF_PERBUF_Msk & ((value) << TC_COUNT8_PERBUF_PERBUF_Pos)) 689 #define TC_COUNT8_PERBUF_MASK _U_(0xFF) /**< \brief (TC_COUNT8_PERBUF) MASK Register */ 690 691 /* -------- TC_COUNT16_CCBUF : (TC Offset: 0x30) (R/W 16) COUNT16 COUNT16 Compare and Capture Buffer -------- */ 692 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 693 typedef union { 694 struct { 695 uint16_t CCBUF:16; /*!< bit: 0..15 Counter/Compare Buffer Value */ 696 } bit; /*!< Structure used for bit access */ 697 uint16_t reg; /*!< Type used for register access */ 698 } TC_COUNT16_CCBUF_Type; 699 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 700 701 #define TC_COUNT16_CCBUF_OFFSET 0x30 /**< \brief (TC_COUNT16_CCBUF offset) COUNT16 Compare and Capture Buffer */ 702 #define TC_COUNT16_CCBUF_RESETVALUE _U_(0x0000) /**< \brief (TC_COUNT16_CCBUF reset_value) COUNT16 Compare and Capture Buffer */ 703 704 #define TC_COUNT16_CCBUF_CCBUF_Pos 0 /**< \brief (TC_COUNT16_CCBUF) Counter/Compare Buffer Value */ 705 #define TC_COUNT16_CCBUF_CCBUF_Msk (_U_(0xFFFF) << TC_COUNT16_CCBUF_CCBUF_Pos) 706 #define TC_COUNT16_CCBUF_CCBUF(value) (TC_COUNT16_CCBUF_CCBUF_Msk & ((value) << TC_COUNT16_CCBUF_CCBUF_Pos)) 707 #define TC_COUNT16_CCBUF_MASK _U_(0xFFFF) /**< \brief (TC_COUNT16_CCBUF) MASK Register */ 708 709 /* -------- TC_COUNT32_CCBUF : (TC Offset: 0x30) (R/W 32) COUNT32 COUNT32 Compare and Capture Buffer -------- */ 710 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 711 typedef union { 712 struct { 713 uint32_t CCBUF:32; /*!< bit: 0..31 Counter/Compare Buffer Value */ 714 } bit; /*!< Structure used for bit access */ 715 uint32_t reg; /*!< Type used for register access */ 716 } TC_COUNT32_CCBUF_Type; 717 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 718 719 #define TC_COUNT32_CCBUF_OFFSET 0x30 /**< \brief (TC_COUNT32_CCBUF offset) COUNT32 Compare and Capture Buffer */ 720 #define TC_COUNT32_CCBUF_RESETVALUE _U_(0x00000000) /**< \brief (TC_COUNT32_CCBUF reset_value) COUNT32 Compare and Capture Buffer */ 721 722 #define TC_COUNT32_CCBUF_CCBUF_Pos 0 /**< \brief (TC_COUNT32_CCBUF) Counter/Compare Buffer Value */ 723 #define TC_COUNT32_CCBUF_CCBUF_Msk (_U_(0xFFFFFFFF) << TC_COUNT32_CCBUF_CCBUF_Pos) 724 #define TC_COUNT32_CCBUF_CCBUF(value) (TC_COUNT32_CCBUF_CCBUF_Msk & ((value) << TC_COUNT32_CCBUF_CCBUF_Pos)) 725 #define TC_COUNT32_CCBUF_MASK _U_(0xFFFFFFFF) /**< \brief (TC_COUNT32_CCBUF) MASK Register */ 726 727 /* -------- TC_COUNT8_CCBUF : (TC Offset: 0x30) (R/W 8) COUNT8 COUNT8 Compare and Capture Buffer -------- */ 728 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 729 typedef union { 730 struct { 731 uint8_t CCBUF:8; /*!< bit: 0.. 7 Counter/Compare Buffer Value */ 732 } bit; /*!< Structure used for bit access */ 733 uint8_t reg; /*!< Type used for register access */ 734 } TC_COUNT8_CCBUF_Type; 735 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 736 737 #define TC_COUNT8_CCBUF_OFFSET 0x30 /**< \brief (TC_COUNT8_CCBUF offset) COUNT8 Compare and Capture Buffer */ 738 #define TC_COUNT8_CCBUF_RESETVALUE _U_(0x00) /**< \brief (TC_COUNT8_CCBUF reset_value) COUNT8 Compare and Capture Buffer */ 739 740 #define TC_COUNT8_CCBUF_CCBUF_Pos 0 /**< \brief (TC_COUNT8_CCBUF) Counter/Compare Buffer Value */ 741 #define TC_COUNT8_CCBUF_CCBUF_Msk (_U_(0xFF) << TC_COUNT8_CCBUF_CCBUF_Pos) 742 #define TC_COUNT8_CCBUF_CCBUF(value) (TC_COUNT8_CCBUF_CCBUF_Msk & ((value) << TC_COUNT8_CCBUF_CCBUF_Pos)) 743 #define TC_COUNT8_CCBUF_MASK _U_(0xFF) /**< \brief (TC_COUNT8_CCBUF) MASK Register */ 744 745 /** \brief TC_COUNT8 hardware registers */ 746 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 747 typedef struct { /* 8-bit Counter Mode */ 748 __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ 749 __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ 750 __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ 751 __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */ 752 __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */ 753 __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */ 754 __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */ 755 __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */ 756 __IO TC_WAVE_Type WAVE; /**< \brief Offset: 0x0C (R/W 8) Waveform Generation Control */ 757 __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */ 758 RoReg8 Reserved1[0x1]; 759 __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0F (R/W 8) Debug Control */ 760 __I TC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Status */ 761 __IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Count */ 762 RoReg8 Reserved2[0x6]; 763 __IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x1B (R/W 8) COUNT8 Period */ 764 __IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x1C (R/W 8) COUNT8 Compare and Capture */ 765 RoReg8 Reserved3[0x11]; 766 __IO TC_COUNT8_PERBUF_Type PERBUF; /**< \brief Offset: 0x2F (R/W 8) COUNT8 Period Buffer */ 767 __IO TC_COUNT8_CCBUF_Type CCBUF[2]; /**< \brief Offset: 0x30 (R/W 8) COUNT8 Compare and Capture Buffer */ 768 } TcCount8; 769 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 770 771 /** \brief TC_COUNT16 hardware registers */ 772 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 773 typedef struct { /* 16-bit Counter Mode */ 774 __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ 775 __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ 776 __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ 777 __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */ 778 __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */ 779 __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */ 780 __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */ 781 __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */ 782 __IO TC_WAVE_Type WAVE; /**< \brief Offset: 0x0C (R/W 8) Waveform Generation Control */ 783 __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */ 784 RoReg8 Reserved1[0x1]; 785 __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0F (R/W 8) Debug Control */ 786 __I TC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Status */ 787 __IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x14 (R/W 16) COUNT16 Count */ 788 RoReg8 Reserved2[0x6]; 789 __IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x1C (R/W 16) COUNT16 Compare and Capture */ 790 RoReg8 Reserved3[0x10]; 791 __IO TC_COUNT16_CCBUF_Type CCBUF[2]; /**< \brief Offset: 0x30 (R/W 16) COUNT16 Compare and Capture Buffer */ 792 } TcCount16; 793 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 794 795 /** \brief TC_COUNT32 hardware registers */ 796 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 797 typedef struct { /* 32-bit Counter Mode */ 798 __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ 799 __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ 800 __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ 801 __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */ 802 __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */ 803 __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */ 804 __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */ 805 __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */ 806 __IO TC_WAVE_Type WAVE; /**< \brief Offset: 0x0C (R/W 8) Waveform Generation Control */ 807 __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */ 808 RoReg8 Reserved1[0x1]; 809 __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0F (R/W 8) Debug Control */ 810 __I TC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Status */ 811 __IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x14 (R/W 32) COUNT32 Count */ 812 RoReg8 Reserved2[0x4]; 813 __IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x1C (R/W 32) COUNT32 Compare and Capture */ 814 RoReg8 Reserved3[0xC]; 815 __IO TC_COUNT32_CCBUF_Type CCBUF[2]; /**< \brief Offset: 0x30 (R/W 32) COUNT32 Compare and Capture Buffer */ 816 } TcCount32; 817 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 818 819 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 820 typedef union { 821 TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */ 822 TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */ 823 TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */ 824 } Tc; 825 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 826 827 /*@}*/ 828 829 #endif /* _SAMC21_TC_COMPONENT_ */ 830
