1 /** 2 * \file 3 * 4 * \brief Component description for SDADC 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMC21_SDADC_COMPONENT_ 31 #define _SAMC21_SDADC_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR SDADC */ 35 /* ========================================================================== */ 36 /** \addtogroup SAMC21_SDADC Sigma-Delta Analog Digital Converter */ 37 /*@{*/ 38 39 #define SDADC_U2260 40 #define REV_SDADC 0x101 41 42 /* -------- SDADC_CTRLA : (SDADC Offset: 0x00) (R/W 8) Control A -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint8_t SWRST:1; /*!< bit: 0 Software Reset */ 47 uint8_t ENABLE:1; /*!< bit: 1 Enable */ 48 uint8_t :4; /*!< bit: 2.. 5 Reserved */ 49 uint8_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ 50 uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ 51 } bit; /*!< Structure used for bit access */ 52 uint8_t reg; /*!< Type used for register access */ 53 } SDADC_CTRLA_Type; 54 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 55 56 #define SDADC_CTRLA_OFFSET 0x00 /**< \brief (SDADC_CTRLA offset) Control A */ 57 #define SDADC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (SDADC_CTRLA reset_value) Control A */ 58 59 #define SDADC_CTRLA_SWRST_Pos 0 /**< \brief (SDADC_CTRLA) Software Reset */ 60 #define SDADC_CTRLA_SWRST (_U_(0x1) << SDADC_CTRLA_SWRST_Pos) 61 #define SDADC_CTRLA_ENABLE_Pos 1 /**< \brief (SDADC_CTRLA) Enable */ 62 #define SDADC_CTRLA_ENABLE (_U_(0x1) << SDADC_CTRLA_ENABLE_Pos) 63 #define SDADC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (SDADC_CTRLA) Run during Standby */ 64 #define SDADC_CTRLA_RUNSTDBY (_U_(0x1) << SDADC_CTRLA_RUNSTDBY_Pos) 65 #define SDADC_CTRLA_ONDEMAND_Pos 7 /**< \brief (SDADC_CTRLA) On Demand Control */ 66 #define SDADC_CTRLA_ONDEMAND (_U_(0x1) << SDADC_CTRLA_ONDEMAND_Pos) 67 #define SDADC_CTRLA_MASK _U_(0xC3) /**< \brief (SDADC_CTRLA) MASK Register */ 68 69 /* -------- SDADC_REFCTRL : (SDADC Offset: 0x01) (R/W 8) Reference Control -------- */ 70 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 71 typedef union { 72 struct { 73 uint8_t REFSEL:2; /*!< bit: 0.. 1 Reference Selection */ 74 uint8_t :2; /*!< bit: 2.. 3 Reserved */ 75 uint8_t REFRANGE:2; /*!< bit: 4.. 5 Reference Range */ 76 uint8_t :1; /*!< bit: 6 Reserved */ 77 uint8_t ONREFBUF:1; /*!< bit: 7 Reference Buffer */ 78 } bit; /*!< Structure used for bit access */ 79 uint8_t reg; /*!< Type used for register access */ 80 } SDADC_REFCTRL_Type; 81 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 82 83 #define SDADC_REFCTRL_OFFSET 0x01 /**< \brief (SDADC_REFCTRL offset) Reference Control */ 84 #define SDADC_REFCTRL_RESETVALUE _U_(0x00) /**< \brief (SDADC_REFCTRL reset_value) Reference Control */ 85 86 #define SDADC_REFCTRL_REFSEL_Pos 0 /**< \brief (SDADC_REFCTRL) Reference Selection */ 87 #define SDADC_REFCTRL_REFSEL_Msk (_U_(0x3) << SDADC_REFCTRL_REFSEL_Pos) 88 #define SDADC_REFCTRL_REFSEL(value) (SDADC_REFCTRL_REFSEL_Msk & ((value) << SDADC_REFCTRL_REFSEL_Pos)) 89 #define SDADC_REFCTRL_REFSEL_INTREF_Val _U_(0x0) /**< \brief (SDADC_REFCTRL) Internal Bandgap Reference */ 90 #define SDADC_REFCTRL_REFSEL_AREFB_Val _U_(0x1) /**< \brief (SDADC_REFCTRL) External Reference */ 91 #define SDADC_REFCTRL_REFSEL_DAC_Val _U_(0x2) /**< \brief (SDADC_REFCTRL) Internal DAC Output */ 92 #define SDADC_REFCTRL_REFSEL_INTVCC_Val _U_(0x3) /**< \brief (SDADC_REFCTRL) VDDANA */ 93 #define SDADC_REFCTRL_REFSEL_INTREF (SDADC_REFCTRL_REFSEL_INTREF_Val << SDADC_REFCTRL_REFSEL_Pos) 94 #define SDADC_REFCTRL_REFSEL_AREFB (SDADC_REFCTRL_REFSEL_AREFB_Val << SDADC_REFCTRL_REFSEL_Pos) 95 #define SDADC_REFCTRL_REFSEL_DAC (SDADC_REFCTRL_REFSEL_DAC_Val << SDADC_REFCTRL_REFSEL_Pos) 96 #define SDADC_REFCTRL_REFSEL_INTVCC (SDADC_REFCTRL_REFSEL_INTVCC_Val << SDADC_REFCTRL_REFSEL_Pos) 97 #define SDADC_REFCTRL_REFRANGE_Pos 4 /**< \brief (SDADC_REFCTRL) Reference Range */ 98 #define SDADC_REFCTRL_REFRANGE_Msk (_U_(0x3) << SDADC_REFCTRL_REFRANGE_Pos) 99 #define SDADC_REFCTRL_REFRANGE(value) (SDADC_REFCTRL_REFRANGE_Msk & ((value) << SDADC_REFCTRL_REFRANGE_Pos)) 100 #define SDADC_REFCTRL_ONREFBUF_Pos 7 /**< \brief (SDADC_REFCTRL) Reference Buffer */ 101 #define SDADC_REFCTRL_ONREFBUF (_U_(0x1) << SDADC_REFCTRL_ONREFBUF_Pos) 102 #define SDADC_REFCTRL_MASK _U_(0xB3) /**< \brief (SDADC_REFCTRL) MASK Register */ 103 104 /* -------- SDADC_CTRLB : (SDADC Offset: 0x02) (R/W 16) Control B -------- */ 105 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 106 typedef union { 107 struct { 108 uint16_t PRESCALER:8; /*!< bit: 0.. 7 Prescaler Configuration */ 109 uint16_t OSR:3; /*!< bit: 8..10 Over Sampling Ratio */ 110 uint16_t :1; /*!< bit: 11 Reserved */ 111 uint16_t SKPCNT:4; /*!< bit: 12..15 Skip Sample Count */ 112 } bit; /*!< Structure used for bit access */ 113 uint16_t reg; /*!< Type used for register access */ 114 } SDADC_CTRLB_Type; 115 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 116 117 #define SDADC_CTRLB_OFFSET 0x02 /**< \brief (SDADC_CTRLB offset) Control B */ 118 #define SDADC_CTRLB_RESETVALUE _U_(0x2000) /**< \brief (SDADC_CTRLB reset_value) Control B */ 119 120 #define SDADC_CTRLB_PRESCALER_Pos 0 /**< \brief (SDADC_CTRLB) Prescaler Configuration */ 121 #define SDADC_CTRLB_PRESCALER_Msk (_U_(0xFF) << SDADC_CTRLB_PRESCALER_Pos) 122 #define SDADC_CTRLB_PRESCALER(value) (SDADC_CTRLB_PRESCALER_Msk & ((value) << SDADC_CTRLB_PRESCALER_Pos)) 123 #define SDADC_CTRLB_OSR_Pos 8 /**< \brief (SDADC_CTRLB) Over Sampling Ratio */ 124 #define SDADC_CTRLB_OSR_Msk (_U_(0x7) << SDADC_CTRLB_OSR_Pos) 125 #define SDADC_CTRLB_OSR(value) (SDADC_CTRLB_OSR_Msk & ((value) << SDADC_CTRLB_OSR_Pos)) 126 #define SDADC_CTRLB_SKPCNT_Pos 12 /**< \brief (SDADC_CTRLB) Skip Sample Count */ 127 #define SDADC_CTRLB_SKPCNT_Msk (_U_(0xF) << SDADC_CTRLB_SKPCNT_Pos) 128 #define SDADC_CTRLB_SKPCNT(value) (SDADC_CTRLB_SKPCNT_Msk & ((value) << SDADC_CTRLB_SKPCNT_Pos)) 129 #define SDADC_CTRLB_MASK _U_(0xF7FF) /**< \brief (SDADC_CTRLB) MASK Register */ 130 131 /* -------- SDADC_EVCTRL : (SDADC Offset: 0x04) (R/W 8) Event Control -------- */ 132 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 133 typedef union { 134 struct { 135 uint8_t FLUSHEI:1; /*!< bit: 0 Flush Event Input Enable */ 136 uint8_t STARTEI:1; /*!< bit: 1 Start Conversion Event Input Enable */ 137 uint8_t FLUSHINV:1; /*!< bit: 2 Flush Event Invert Enable */ 138 uint8_t STARTINV:1; /*!< bit: 3 Satrt Event Invert Enable */ 139 uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */ 140 uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */ 141 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 142 } bit; /*!< Structure used for bit access */ 143 uint8_t reg; /*!< Type used for register access */ 144 } SDADC_EVCTRL_Type; 145 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 146 147 #define SDADC_EVCTRL_OFFSET 0x04 /**< \brief (SDADC_EVCTRL offset) Event Control */ 148 #define SDADC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (SDADC_EVCTRL reset_value) Event Control */ 149 150 #define SDADC_EVCTRL_FLUSHEI_Pos 0 /**< \brief (SDADC_EVCTRL) Flush Event Input Enable */ 151 #define SDADC_EVCTRL_FLUSHEI (_U_(0x1) << SDADC_EVCTRL_FLUSHEI_Pos) 152 #define SDADC_EVCTRL_STARTEI_Pos 1 /**< \brief (SDADC_EVCTRL) Start Conversion Event Input Enable */ 153 #define SDADC_EVCTRL_STARTEI (_U_(0x1) << SDADC_EVCTRL_STARTEI_Pos) 154 #define SDADC_EVCTRL_FLUSHINV_Pos 2 /**< \brief (SDADC_EVCTRL) Flush Event Invert Enable */ 155 #define SDADC_EVCTRL_FLUSHINV (_U_(0x1) << SDADC_EVCTRL_FLUSHINV_Pos) 156 #define SDADC_EVCTRL_STARTINV_Pos 3 /**< \brief (SDADC_EVCTRL) Satrt Event Invert Enable */ 157 #define SDADC_EVCTRL_STARTINV (_U_(0x1) << SDADC_EVCTRL_STARTINV_Pos) 158 #define SDADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (SDADC_EVCTRL) Result Ready Event Out */ 159 #define SDADC_EVCTRL_RESRDYEO (_U_(0x1) << SDADC_EVCTRL_RESRDYEO_Pos) 160 #define SDADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (SDADC_EVCTRL) Window Monitor Event Out */ 161 #define SDADC_EVCTRL_WINMONEO (_U_(0x1) << SDADC_EVCTRL_WINMONEO_Pos) 162 #define SDADC_EVCTRL_MASK _U_(0x3F) /**< \brief (SDADC_EVCTRL) MASK Register */ 163 164 /* -------- SDADC_INTENCLR : (SDADC Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */ 165 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 166 typedef union { 167 struct { 168 uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Disable */ 169 uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Disable */ 170 uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Disable */ 171 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 172 } bit; /*!< Structure used for bit access */ 173 uint8_t reg; /*!< Type used for register access */ 174 } SDADC_INTENCLR_Type; 175 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 176 177 #define SDADC_INTENCLR_OFFSET 0x05 /**< \brief (SDADC_INTENCLR offset) Interrupt Enable Clear */ 178 #define SDADC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (SDADC_INTENCLR reset_value) Interrupt Enable Clear */ 179 180 #define SDADC_INTENCLR_RESRDY_Pos 0 /**< \brief (SDADC_INTENCLR) Result Ready Interrupt Disable */ 181 #define SDADC_INTENCLR_RESRDY (_U_(0x1) << SDADC_INTENCLR_RESRDY_Pos) 182 #define SDADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (SDADC_INTENCLR) Overrun Interrupt Disable */ 183 #define SDADC_INTENCLR_OVERRUN (_U_(0x1) << SDADC_INTENCLR_OVERRUN_Pos) 184 #define SDADC_INTENCLR_WINMON_Pos 2 /**< \brief (SDADC_INTENCLR) Window Monitor Interrupt Disable */ 185 #define SDADC_INTENCLR_WINMON (_U_(0x1) << SDADC_INTENCLR_WINMON_Pos) 186 #define SDADC_INTENCLR_MASK _U_(0x07) /**< \brief (SDADC_INTENCLR) MASK Register */ 187 188 /* -------- SDADC_INTENSET : (SDADC Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */ 189 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 190 typedef union { 191 struct { 192 uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ 193 uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ 194 uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ 195 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 196 } bit; /*!< Structure used for bit access */ 197 uint8_t reg; /*!< Type used for register access */ 198 } SDADC_INTENSET_Type; 199 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 200 201 #define SDADC_INTENSET_OFFSET 0x06 /**< \brief (SDADC_INTENSET offset) Interrupt Enable Set */ 202 #define SDADC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (SDADC_INTENSET reset_value) Interrupt Enable Set */ 203 204 #define SDADC_INTENSET_RESRDY_Pos 0 /**< \brief (SDADC_INTENSET) Result Ready Interrupt Enable */ 205 #define SDADC_INTENSET_RESRDY (_U_(0x1) << SDADC_INTENSET_RESRDY_Pos) 206 #define SDADC_INTENSET_OVERRUN_Pos 1 /**< \brief (SDADC_INTENSET) Overrun Interrupt Enable */ 207 #define SDADC_INTENSET_OVERRUN (_U_(0x1) << SDADC_INTENSET_OVERRUN_Pos) 208 #define SDADC_INTENSET_WINMON_Pos 2 /**< \brief (SDADC_INTENSET) Window Monitor Interrupt Enable */ 209 #define SDADC_INTENSET_WINMON (_U_(0x1) << SDADC_INTENSET_WINMON_Pos) 210 #define SDADC_INTENSET_MASK _U_(0x07) /**< \brief (SDADC_INTENSET) MASK Register */ 211 212 /* -------- SDADC_INTFLAG : (SDADC Offset: 0x07) (R/W 8) Interrupt Flag Status and Clear -------- */ 213 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 214 typedef union { // __I to avoid read-modify-write on write-to-clear register 215 struct { 216 __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Flag */ 217 __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Flag */ 218 __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Flag */ 219 __I uint8_t Reserved1:5; /*!< bit: 3.. 7 Reserved */ 220 } bit; /*!< Structure used for bit access */ 221 uint8_t reg; /*!< Type used for register access */ 222 } SDADC_INTFLAG_Type; 223 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 224 225 #define SDADC_INTFLAG_OFFSET 0x07 /**< \brief (SDADC_INTFLAG offset) Interrupt Flag Status and Clear */ 226 #define SDADC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (SDADC_INTFLAG reset_value) Interrupt Flag Status and Clear */ 227 228 #define SDADC_INTFLAG_RESRDY_Pos 0 /**< \brief (SDADC_INTFLAG) Result Ready Interrupt Flag */ 229 #define SDADC_INTFLAG_RESRDY (_U_(0x1) << SDADC_INTFLAG_RESRDY_Pos) 230 #define SDADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (SDADC_INTFLAG) Overrun Interrupt Flag */ 231 #define SDADC_INTFLAG_OVERRUN (_U_(0x1) << SDADC_INTFLAG_OVERRUN_Pos) 232 #define SDADC_INTFLAG_WINMON_Pos 2 /**< \brief (SDADC_INTFLAG) Window Monitor Interrupt Flag */ 233 #define SDADC_INTFLAG_WINMON (_U_(0x1) << SDADC_INTFLAG_WINMON_Pos) 234 #define SDADC_INTFLAG_MASK _U_(0x07) /**< \brief (SDADC_INTFLAG) MASK Register */ 235 236 /* -------- SDADC_SEQSTATUS : (SDADC Offset: 0x08) (R/ 8) Sequence Status -------- */ 237 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 238 typedef union { 239 struct { 240 uint8_t SEQSTATE:4; /*!< bit: 0.. 3 Sequence State */ 241 uint8_t :3; /*!< bit: 4.. 6 Reserved */ 242 uint8_t SEQBUSY:1; /*!< bit: 7 Sequence Busy */ 243 } bit; /*!< Structure used for bit access */ 244 uint8_t reg; /*!< Type used for register access */ 245 } SDADC_SEQSTATUS_Type; 246 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 247 248 #define SDADC_SEQSTATUS_OFFSET 0x08 /**< \brief (SDADC_SEQSTATUS offset) Sequence Status */ 249 #define SDADC_SEQSTATUS_RESETVALUE _U_(0x00) /**< \brief (SDADC_SEQSTATUS reset_value) Sequence Status */ 250 251 #define SDADC_SEQSTATUS_SEQSTATE_Pos 0 /**< \brief (SDADC_SEQSTATUS) Sequence State */ 252 #define SDADC_SEQSTATUS_SEQSTATE_Msk (_U_(0xF) << SDADC_SEQSTATUS_SEQSTATE_Pos) 253 #define SDADC_SEQSTATUS_SEQSTATE(value) (SDADC_SEQSTATUS_SEQSTATE_Msk & ((value) << SDADC_SEQSTATUS_SEQSTATE_Pos)) 254 #define SDADC_SEQSTATUS_SEQBUSY_Pos 7 /**< \brief (SDADC_SEQSTATUS) Sequence Busy */ 255 #define SDADC_SEQSTATUS_SEQBUSY (_U_(0x1) << SDADC_SEQSTATUS_SEQBUSY_Pos) 256 #define SDADC_SEQSTATUS_MASK _U_(0x8F) /**< \brief (SDADC_SEQSTATUS) MASK Register */ 257 258 /* -------- SDADC_INPUTCTRL : (SDADC Offset: 0x09) (R/W 8) Input Control -------- */ 259 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 260 typedef union { 261 struct { 262 uint8_t MUXSEL:4; /*!< bit: 0.. 3 SDADC Input Selection */ 263 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 264 } bit; /*!< Structure used for bit access */ 265 uint8_t reg; /*!< Type used for register access */ 266 } SDADC_INPUTCTRL_Type; 267 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 268 269 #define SDADC_INPUTCTRL_OFFSET 0x09 /**< \brief (SDADC_INPUTCTRL offset) Input Control */ 270 #define SDADC_INPUTCTRL_RESETVALUE _U_(0x00) /**< \brief (SDADC_INPUTCTRL reset_value) Input Control */ 271 272 #define SDADC_INPUTCTRL_MUXSEL_Pos 0 /**< \brief (SDADC_INPUTCTRL) SDADC Input Selection */ 273 #define SDADC_INPUTCTRL_MUXSEL_Msk (_U_(0xF) << SDADC_INPUTCTRL_MUXSEL_Pos) 274 #define SDADC_INPUTCTRL_MUXSEL(value) (SDADC_INPUTCTRL_MUXSEL_Msk & ((value) << SDADC_INPUTCTRL_MUXSEL_Pos)) 275 #define SDADC_INPUTCTRL_MUXSEL_AIN0_Val _U_(0x0) /**< \brief (SDADC_INPUTCTRL) SDADC AIN0 Pin */ 276 #define SDADC_INPUTCTRL_MUXSEL_AIN1_Val _U_(0x1) /**< \brief (SDADC_INPUTCTRL) SDADC AIN1 Pin */ 277 #define SDADC_INPUTCTRL_MUXSEL_AIN2_Val _U_(0x2) /**< \brief (SDADC_INPUTCTRL) SDADC AIN2 Pin */ 278 #define SDADC_INPUTCTRL_MUXSEL_AIN0 (SDADC_INPUTCTRL_MUXSEL_AIN0_Val << SDADC_INPUTCTRL_MUXSEL_Pos) 279 #define SDADC_INPUTCTRL_MUXSEL_AIN1 (SDADC_INPUTCTRL_MUXSEL_AIN1_Val << SDADC_INPUTCTRL_MUXSEL_Pos) 280 #define SDADC_INPUTCTRL_MUXSEL_AIN2 (SDADC_INPUTCTRL_MUXSEL_AIN2_Val << SDADC_INPUTCTRL_MUXSEL_Pos) 281 #define SDADC_INPUTCTRL_MASK _U_(0x0F) /**< \brief (SDADC_INPUTCTRL) MASK Register */ 282 283 /* -------- SDADC_CTRLC : (SDADC Offset: 0x0A) (R/W 8) Control C -------- */ 284 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 285 typedef union { 286 struct { 287 uint8_t FREERUN:1; /*!< bit: 0 Free Running Mode */ 288 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 289 } bit; /*!< Structure used for bit access */ 290 uint8_t reg; /*!< Type used for register access */ 291 } SDADC_CTRLC_Type; 292 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 293 294 #define SDADC_CTRLC_OFFSET 0x0A /**< \brief (SDADC_CTRLC offset) Control C */ 295 #define SDADC_CTRLC_RESETVALUE _U_(0x00) /**< \brief (SDADC_CTRLC reset_value) Control C */ 296 297 #define SDADC_CTRLC_FREERUN_Pos 0 /**< \brief (SDADC_CTRLC) Free Running Mode */ 298 #define SDADC_CTRLC_FREERUN (_U_(0x1) << SDADC_CTRLC_FREERUN_Pos) 299 #define SDADC_CTRLC_MASK _U_(0x01) /**< \brief (SDADC_CTRLC) MASK Register */ 300 301 /* -------- SDADC_WINCTRL : (SDADC Offset: 0x0B) (R/W 8) Window Monitor Control -------- */ 302 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 303 typedef union { 304 struct { 305 uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */ 306 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 307 } bit; /*!< Structure used for bit access */ 308 uint8_t reg; /*!< Type used for register access */ 309 } SDADC_WINCTRL_Type; 310 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 311 312 #define SDADC_WINCTRL_OFFSET 0x0B /**< \brief (SDADC_WINCTRL offset) Window Monitor Control */ 313 #define SDADC_WINCTRL_RESETVALUE _U_(0x00) /**< \brief (SDADC_WINCTRL reset_value) Window Monitor Control */ 314 315 #define SDADC_WINCTRL_WINMODE_Pos 0 /**< \brief (SDADC_WINCTRL) Window Monitor Mode */ 316 #define SDADC_WINCTRL_WINMODE_Msk (_U_(0x7) << SDADC_WINCTRL_WINMODE_Pos) 317 #define SDADC_WINCTRL_WINMODE(value) (SDADC_WINCTRL_WINMODE_Msk & ((value) << SDADC_WINCTRL_WINMODE_Pos)) 318 #define SDADC_WINCTRL_MASK _U_(0x07) /**< \brief (SDADC_WINCTRL) MASK Register */ 319 320 /* -------- SDADC_WINLT : (SDADC Offset: 0x0C) (R/W 32) Window Monitor Lower Threshold -------- */ 321 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 322 typedef union { 323 struct { 324 uint32_t WINLT:24; /*!< bit: 0..23 Window Lower Threshold */ 325 uint32_t :8; /*!< bit: 24..31 Reserved */ 326 } bit; /*!< Structure used for bit access */ 327 uint32_t reg; /*!< Type used for register access */ 328 } SDADC_WINLT_Type; 329 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 330 331 #define SDADC_WINLT_OFFSET 0x0C /**< \brief (SDADC_WINLT offset) Window Monitor Lower Threshold */ 332 #define SDADC_WINLT_RESETVALUE _U_(0x00000000) /**< \brief (SDADC_WINLT reset_value) Window Monitor Lower Threshold */ 333 334 #define SDADC_WINLT_WINLT_Pos 0 /**< \brief (SDADC_WINLT) Window Lower Threshold */ 335 #define SDADC_WINLT_WINLT_Msk (_U_(0xFFFFFF) << SDADC_WINLT_WINLT_Pos) 336 #define SDADC_WINLT_WINLT(value) (SDADC_WINLT_WINLT_Msk & ((value) << SDADC_WINLT_WINLT_Pos)) 337 #define SDADC_WINLT_MASK _U_(0x00FFFFFF) /**< \brief (SDADC_WINLT) MASK Register */ 338 339 /* -------- SDADC_WINUT : (SDADC Offset: 0x10) (R/W 32) Window Monitor Upper Threshold -------- */ 340 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 341 typedef union { 342 struct { 343 uint32_t WINUT:24; /*!< bit: 0..23 Window Upper Threshold */ 344 uint32_t :8; /*!< bit: 24..31 Reserved */ 345 } bit; /*!< Structure used for bit access */ 346 uint32_t reg; /*!< Type used for register access */ 347 } SDADC_WINUT_Type; 348 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 349 350 #define SDADC_WINUT_OFFSET 0x10 /**< \brief (SDADC_WINUT offset) Window Monitor Upper Threshold */ 351 #define SDADC_WINUT_RESETVALUE _U_(0x00000000) /**< \brief (SDADC_WINUT reset_value) Window Monitor Upper Threshold */ 352 353 #define SDADC_WINUT_WINUT_Pos 0 /**< \brief (SDADC_WINUT) Window Upper Threshold */ 354 #define SDADC_WINUT_WINUT_Msk (_U_(0xFFFFFF) << SDADC_WINUT_WINUT_Pos) 355 #define SDADC_WINUT_WINUT(value) (SDADC_WINUT_WINUT_Msk & ((value) << SDADC_WINUT_WINUT_Pos)) 356 #define SDADC_WINUT_MASK _U_(0x00FFFFFF) /**< \brief (SDADC_WINUT) MASK Register */ 357 358 /* -------- SDADC_OFFSETCORR : (SDADC Offset: 0x14) (R/W 32) Offset Correction -------- */ 359 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 360 typedef union { 361 struct { 362 uint32_t OFFSETCORR:24; /*!< bit: 0..23 Offset Correction Value */ 363 uint32_t :8; /*!< bit: 24..31 Reserved */ 364 } bit; /*!< Structure used for bit access */ 365 uint32_t reg; /*!< Type used for register access */ 366 } SDADC_OFFSETCORR_Type; 367 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 368 369 #define SDADC_OFFSETCORR_OFFSET 0x14 /**< \brief (SDADC_OFFSETCORR offset) Offset Correction */ 370 #define SDADC_OFFSETCORR_RESETVALUE _U_(0x00000000) /**< \brief (SDADC_OFFSETCORR reset_value) Offset Correction */ 371 372 #define SDADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (SDADC_OFFSETCORR) Offset Correction Value */ 373 #define SDADC_OFFSETCORR_OFFSETCORR_Msk (_U_(0xFFFFFF) << SDADC_OFFSETCORR_OFFSETCORR_Pos) 374 #define SDADC_OFFSETCORR_OFFSETCORR(value) (SDADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << SDADC_OFFSETCORR_OFFSETCORR_Pos)) 375 #define SDADC_OFFSETCORR_MASK _U_(0x00FFFFFF) /**< \brief (SDADC_OFFSETCORR) MASK Register */ 376 377 /* -------- SDADC_GAINCORR : (SDADC Offset: 0x18) (R/W 16) Gain Correction -------- */ 378 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 379 typedef union { 380 struct { 381 uint16_t GAINCORR:14; /*!< bit: 0..13 Gain Correction Value */ 382 uint16_t :2; /*!< bit: 14..15 Reserved */ 383 } bit; /*!< Structure used for bit access */ 384 uint16_t reg; /*!< Type used for register access */ 385 } SDADC_GAINCORR_Type; 386 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 387 388 #define SDADC_GAINCORR_OFFSET 0x18 /**< \brief (SDADC_GAINCORR offset) Gain Correction */ 389 #define SDADC_GAINCORR_RESETVALUE _U_(0x0001) /**< \brief (SDADC_GAINCORR reset_value) Gain Correction */ 390 391 #define SDADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (SDADC_GAINCORR) Gain Correction Value */ 392 #define SDADC_GAINCORR_GAINCORR_Msk (_U_(0x3FFF) << SDADC_GAINCORR_GAINCORR_Pos) 393 #define SDADC_GAINCORR_GAINCORR(value) (SDADC_GAINCORR_GAINCORR_Msk & ((value) << SDADC_GAINCORR_GAINCORR_Pos)) 394 #define SDADC_GAINCORR_MASK _U_(0x3FFF) /**< \brief (SDADC_GAINCORR) MASK Register */ 395 396 /* -------- SDADC_SHIFTCORR : (SDADC Offset: 0x1A) (R/W 8) Shift Correction -------- */ 397 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 398 typedef union { 399 struct { 400 uint8_t SHIFTCORR:4; /*!< bit: 0.. 3 Shift Correction Value */ 401 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 402 } bit; /*!< Structure used for bit access */ 403 uint8_t reg; /*!< Type used for register access */ 404 } SDADC_SHIFTCORR_Type; 405 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 406 407 #define SDADC_SHIFTCORR_OFFSET 0x1A /**< \brief (SDADC_SHIFTCORR offset) Shift Correction */ 408 #define SDADC_SHIFTCORR_RESETVALUE _U_(0x00) /**< \brief (SDADC_SHIFTCORR reset_value) Shift Correction */ 409 410 #define SDADC_SHIFTCORR_SHIFTCORR_Pos 0 /**< \brief (SDADC_SHIFTCORR) Shift Correction Value */ 411 #define SDADC_SHIFTCORR_SHIFTCORR_Msk (_U_(0xF) << SDADC_SHIFTCORR_SHIFTCORR_Pos) 412 #define SDADC_SHIFTCORR_SHIFTCORR(value) (SDADC_SHIFTCORR_SHIFTCORR_Msk & ((value) << SDADC_SHIFTCORR_SHIFTCORR_Pos)) 413 #define SDADC_SHIFTCORR_MASK _U_(0x0F) /**< \brief (SDADC_SHIFTCORR) MASK Register */ 414 415 /* -------- SDADC_SWTRIG : (SDADC Offset: 0x1C) (R/W 8) Software Trigger -------- */ 416 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 417 typedef union { 418 struct { 419 uint8_t FLUSH:1; /*!< bit: 0 SDADC Flush */ 420 uint8_t START:1; /*!< bit: 1 Start SDADC Conversion */ 421 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 422 } bit; /*!< Structure used for bit access */ 423 uint8_t reg; /*!< Type used for register access */ 424 } SDADC_SWTRIG_Type; 425 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 426 427 #define SDADC_SWTRIG_OFFSET 0x1C /**< \brief (SDADC_SWTRIG offset) Software Trigger */ 428 #define SDADC_SWTRIG_RESETVALUE _U_(0x00) /**< \brief (SDADC_SWTRIG reset_value) Software Trigger */ 429 430 #define SDADC_SWTRIG_FLUSH_Pos 0 /**< \brief (SDADC_SWTRIG) SDADC Flush */ 431 #define SDADC_SWTRIG_FLUSH (_U_(0x1) << SDADC_SWTRIG_FLUSH_Pos) 432 #define SDADC_SWTRIG_START_Pos 1 /**< \brief (SDADC_SWTRIG) Start SDADC Conversion */ 433 #define SDADC_SWTRIG_START (_U_(0x1) << SDADC_SWTRIG_START_Pos) 434 #define SDADC_SWTRIG_MASK _U_(0x03) /**< \brief (SDADC_SWTRIG) MASK Register */ 435 436 /* -------- SDADC_SYNCBUSY : (SDADC Offset: 0x20) (R/ 32) Synchronization Busy -------- */ 437 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 438 typedef union { 439 struct { 440 uint32_t SWRST:1; /*!< bit: 0 SWRST Synchronization Busy */ 441 uint32_t ENABLE:1; /*!< bit: 1 ENABLE Synchronization Busy */ 442 uint32_t CTRLC:1; /*!< bit: 2 CTRLC Synchronization Busy */ 443 uint32_t INPUTCTRL:1; /*!< bit: 3 INPUTCTRL Synchronization Busy */ 444 uint32_t WINCTRL:1; /*!< bit: 4 WINCTRL Synchronization Busy */ 445 uint32_t WINLT:1; /*!< bit: 5 WINLT Synchronization Busy */ 446 uint32_t WINUT:1; /*!< bit: 6 WINUT Synchronization Busy */ 447 uint32_t OFFSETCORR:1; /*!< bit: 7 OFFSETCTRL Synchronization Busy */ 448 uint32_t GAINCORR:1; /*!< bit: 8 GAINCORR Synchronization Busy */ 449 uint32_t SHIFTCORR:1; /*!< bit: 9 SHIFTCORR Synchronization Busy */ 450 uint32_t SWTRIG:1; /*!< bit: 10 SWTRG Synchronization Busy */ 451 uint32_t ANACTRL:1; /*!< bit: 11 ANACTRL Synchronization Busy */ 452 uint32_t :20; /*!< bit: 12..31 Reserved */ 453 } bit; /*!< Structure used for bit access */ 454 uint32_t reg; /*!< Type used for register access */ 455 } SDADC_SYNCBUSY_Type; 456 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 457 458 #define SDADC_SYNCBUSY_OFFSET 0x20 /**< \brief (SDADC_SYNCBUSY offset) Synchronization Busy */ 459 #define SDADC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (SDADC_SYNCBUSY reset_value) Synchronization Busy */ 460 461 #define SDADC_SYNCBUSY_SWRST_Pos 0 /**< \brief (SDADC_SYNCBUSY) SWRST Synchronization Busy */ 462 #define SDADC_SYNCBUSY_SWRST (_U_(0x1) << SDADC_SYNCBUSY_SWRST_Pos) 463 #define SDADC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SDADC_SYNCBUSY) ENABLE Synchronization Busy */ 464 #define SDADC_SYNCBUSY_ENABLE (_U_(0x1) << SDADC_SYNCBUSY_ENABLE_Pos) 465 #define SDADC_SYNCBUSY_CTRLC_Pos 2 /**< \brief (SDADC_SYNCBUSY) CTRLC Synchronization Busy */ 466 #define SDADC_SYNCBUSY_CTRLC (_U_(0x1) << SDADC_SYNCBUSY_CTRLC_Pos) 467 #define SDADC_SYNCBUSY_INPUTCTRL_Pos 3 /**< \brief (SDADC_SYNCBUSY) INPUTCTRL Synchronization Busy */ 468 #define SDADC_SYNCBUSY_INPUTCTRL (_U_(0x1) << SDADC_SYNCBUSY_INPUTCTRL_Pos) 469 #define SDADC_SYNCBUSY_WINCTRL_Pos 4 /**< \brief (SDADC_SYNCBUSY) WINCTRL Synchronization Busy */ 470 #define SDADC_SYNCBUSY_WINCTRL (_U_(0x1) << SDADC_SYNCBUSY_WINCTRL_Pos) 471 #define SDADC_SYNCBUSY_WINLT_Pos 5 /**< \brief (SDADC_SYNCBUSY) WINLT Synchronization Busy */ 472 #define SDADC_SYNCBUSY_WINLT (_U_(0x1) << SDADC_SYNCBUSY_WINLT_Pos) 473 #define SDADC_SYNCBUSY_WINUT_Pos 6 /**< \brief (SDADC_SYNCBUSY) WINUT Synchronization Busy */ 474 #define SDADC_SYNCBUSY_WINUT (_U_(0x1) << SDADC_SYNCBUSY_WINUT_Pos) 475 #define SDADC_SYNCBUSY_OFFSETCORR_Pos 7 /**< \brief (SDADC_SYNCBUSY) OFFSETCTRL Synchronization Busy */ 476 #define SDADC_SYNCBUSY_OFFSETCORR (_U_(0x1) << SDADC_SYNCBUSY_OFFSETCORR_Pos) 477 #define SDADC_SYNCBUSY_GAINCORR_Pos 8 /**< \brief (SDADC_SYNCBUSY) GAINCORR Synchronization Busy */ 478 #define SDADC_SYNCBUSY_GAINCORR (_U_(0x1) << SDADC_SYNCBUSY_GAINCORR_Pos) 479 #define SDADC_SYNCBUSY_SHIFTCORR_Pos 9 /**< \brief (SDADC_SYNCBUSY) SHIFTCORR Synchronization Busy */ 480 #define SDADC_SYNCBUSY_SHIFTCORR (_U_(0x1) << SDADC_SYNCBUSY_SHIFTCORR_Pos) 481 #define SDADC_SYNCBUSY_SWTRIG_Pos 10 /**< \brief (SDADC_SYNCBUSY) SWTRG Synchronization Busy */ 482 #define SDADC_SYNCBUSY_SWTRIG (_U_(0x1) << SDADC_SYNCBUSY_SWTRIG_Pos) 483 #define SDADC_SYNCBUSY_ANACTRL_Pos 11 /**< \brief (SDADC_SYNCBUSY) ANACTRL Synchronization Busy */ 484 #define SDADC_SYNCBUSY_ANACTRL (_U_(0x1) << SDADC_SYNCBUSY_ANACTRL_Pos) 485 #define SDADC_SYNCBUSY_MASK _U_(0x00000FFF) /**< \brief (SDADC_SYNCBUSY) MASK Register */ 486 487 /* -------- SDADC_RESULT : (SDADC Offset: 0x24) (R/ 32) Result -------- */ 488 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 489 typedef union { 490 struct { 491 uint32_t RESULT:24; /*!< bit: 0..23 Result Value */ 492 uint32_t RESERVED:8; /*!< bit: 24..31 Reserved */ 493 } bit; /*!< Structure used for bit access */ 494 uint32_t reg; /*!< Type used for register access */ 495 } SDADC_RESULT_Type; 496 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 497 498 #define SDADC_RESULT_OFFSET 0x24 /**< \brief (SDADC_RESULT offset) Result */ 499 #define SDADC_RESULT_RESETVALUE _U_(0x00000000) /**< \brief (SDADC_RESULT reset_value) Result */ 500 501 #define SDADC_RESULT_RESULT_Pos 0 /**< \brief (SDADC_RESULT) Result Value */ 502 #define SDADC_RESULT_RESULT_Msk (_U_(0xFFFFFF) << SDADC_RESULT_RESULT_Pos) 503 #define SDADC_RESULT_RESULT(value) (SDADC_RESULT_RESULT_Msk & ((value) << SDADC_RESULT_RESULT_Pos)) 504 #define SDADC_RESULT_RESERVED_Pos 24 /**< \brief (SDADC_RESULT) Reserved */ 505 #define SDADC_RESULT_RESERVED_Msk (_U_(0xFF) << SDADC_RESULT_RESERVED_Pos) 506 #define SDADC_RESULT_RESERVED(value) (SDADC_RESULT_RESERVED_Msk & ((value) << SDADC_RESULT_RESERVED_Pos)) 507 #define SDADC_RESULT_MASK _U_(0xFFFFFFFF) /**< \brief (SDADC_RESULT) MASK Register */ 508 509 /* -------- SDADC_SEQCTRL : (SDADC Offset: 0x28) (R/W 8) Sequence Control -------- */ 510 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 511 typedef union { 512 struct { 513 uint8_t SEQEN:3; /*!< bit: 0.. 2 Enable Positive Input in the Sequence */ 514 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 515 } bit; /*!< Structure used for bit access */ 516 uint8_t reg; /*!< Type used for register access */ 517 } SDADC_SEQCTRL_Type; 518 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 519 520 #define SDADC_SEQCTRL_OFFSET 0x28 /**< \brief (SDADC_SEQCTRL offset) Sequence Control */ 521 #define SDADC_SEQCTRL_RESETVALUE _U_(0x00) /**< \brief (SDADC_SEQCTRL reset_value) Sequence Control */ 522 523 #define SDADC_SEQCTRL_SEQEN_Pos 0 /**< \brief (SDADC_SEQCTRL) Enable Positive Input in the Sequence */ 524 #define SDADC_SEQCTRL_SEQEN_Msk (_U_(0x7) << SDADC_SEQCTRL_SEQEN_Pos) 525 #define SDADC_SEQCTRL_SEQEN(value) (SDADC_SEQCTRL_SEQEN_Msk & ((value) << SDADC_SEQCTRL_SEQEN_Pos)) 526 #define SDADC_SEQCTRL_MASK _U_(0x07) /**< \brief (SDADC_SEQCTRL) MASK Register */ 527 528 /* -------- SDADC_ANACTRL : (SDADC Offset: 0x2C) (R/W 8) Analog Control -------- */ 529 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 530 typedef union { 531 struct { 532 uint8_t CTRSDADC:6; /*!< bit: 0.. 5 SDADC Control */ 533 uint8_t ONCHOP:1; /*!< bit: 6 Chopper */ 534 uint8_t BUFTEST:1; /*!< bit: 7 BUFTEST */ 535 } bit; /*!< Structure used for bit access */ 536 uint8_t reg; /*!< Type used for register access */ 537 } SDADC_ANACTRL_Type; 538 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 539 540 #define SDADC_ANACTRL_OFFSET 0x2C /**< \brief (SDADC_ANACTRL offset) Analog Control */ 541 #define SDADC_ANACTRL_RESETVALUE _U_(0x00) /**< \brief (SDADC_ANACTRL reset_value) Analog Control */ 542 543 #define SDADC_ANACTRL_CTRSDADC_Pos 0 /**< \brief (SDADC_ANACTRL) SDADC Control */ 544 #define SDADC_ANACTRL_CTRSDADC_Msk (_U_(0x3F) << SDADC_ANACTRL_CTRSDADC_Pos) 545 #define SDADC_ANACTRL_CTRSDADC(value) (SDADC_ANACTRL_CTRSDADC_Msk & ((value) << SDADC_ANACTRL_CTRSDADC_Pos)) 546 #define SDADC_ANACTRL_ONCHOP_Pos 6 /**< \brief (SDADC_ANACTRL) Chopper */ 547 #define SDADC_ANACTRL_ONCHOP (_U_(0x1) << SDADC_ANACTRL_ONCHOP_Pos) 548 #define SDADC_ANACTRL_BUFTEST_Pos 7 /**< \brief (SDADC_ANACTRL) BUFTEST */ 549 #define SDADC_ANACTRL_BUFTEST (_U_(0x1) << SDADC_ANACTRL_BUFTEST_Pos) 550 #define SDADC_ANACTRL_MASK _U_(0xFF) /**< \brief (SDADC_ANACTRL) MASK Register */ 551 552 /* -------- SDADC_DBGCTRL : (SDADC Offset: 0x2E) (R/W 8) Debug Control -------- */ 553 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 554 typedef union { 555 struct { 556 uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ 557 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 558 } bit; /*!< Structure used for bit access */ 559 uint8_t reg; /*!< Type used for register access */ 560 } SDADC_DBGCTRL_Type; 561 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 562 563 #define SDADC_DBGCTRL_OFFSET 0x2E /**< \brief (SDADC_DBGCTRL offset) Debug Control */ 564 #define SDADC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (SDADC_DBGCTRL reset_value) Debug Control */ 565 566 #define SDADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (SDADC_DBGCTRL) Debug Run */ 567 #define SDADC_DBGCTRL_DBGRUN (_U_(0x1) << SDADC_DBGCTRL_DBGRUN_Pos) 568 #define SDADC_DBGCTRL_MASK _U_(0x01) /**< \brief (SDADC_DBGCTRL) MASK Register */ 569 570 /** \brief SDADC hardware registers */ 571 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 572 typedef struct { 573 __IO SDADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ 574 __IO SDADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */ 575 __IO SDADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x02 (R/W 16) Control B */ 576 __IO SDADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 8) Event Control */ 577 __IO SDADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Clear */ 578 __IO SDADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x06 (R/W 8) Interrupt Enable Set */ 579 __IO SDADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x07 (R/W 8) Interrupt Flag Status and Clear */ 580 __I SDADC_SEQSTATUS_Type SEQSTATUS; /**< \brief Offset: 0x08 (R/ 8) Sequence Status */ 581 __IO SDADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x09 (R/W 8) Input Control */ 582 __IO SDADC_CTRLC_Type CTRLC; /**< \brief Offset: 0x0A (R/W 8) Control C */ 583 __IO SDADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0B (R/W 8) Window Monitor Control */ 584 __IO SDADC_WINLT_Type WINLT; /**< \brief Offset: 0x0C (R/W 32) Window Monitor Lower Threshold */ 585 __IO SDADC_WINUT_Type WINUT; /**< \brief Offset: 0x10 (R/W 32) Window Monitor Upper Threshold */ 586 __IO SDADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x14 (R/W 32) Offset Correction */ 587 __IO SDADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x18 (R/W 16) Gain Correction */ 588 __IO SDADC_SHIFTCORR_Type SHIFTCORR; /**< \brief Offset: 0x1A (R/W 8) Shift Correction */ 589 RoReg8 Reserved1[0x1]; 590 __IO SDADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x1C (R/W 8) Software Trigger */ 591 RoReg8 Reserved2[0x3]; 592 __I SDADC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 32) Synchronization Busy */ 593 __I SDADC_RESULT_Type RESULT; /**< \brief Offset: 0x24 (R/ 32) Result */ 594 __IO SDADC_SEQCTRL_Type SEQCTRL; /**< \brief Offset: 0x28 (R/W 8) Sequence Control */ 595 RoReg8 Reserved3[0x3]; 596 __IO SDADC_ANACTRL_Type ANACTRL; /**< \brief Offset: 0x2C (R/W 8) Analog Control */ 597 RoReg8 Reserved4[0x1]; 598 __IO SDADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2E (R/W 8) Debug Control */ 599 } Sdadc; 600 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 601 602 /*@}*/ 603 604 #endif /* _SAMC21_SDADC_COMPONENT_ */ 605
