1 /** 2 * \file 3 * 4 * \brief Component description for PORT 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMC21_PORT_COMPONENT_ 31 #define _SAMC21_PORT_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR PORT */ 35 /* ========================================================================== */ 36 /** \addtogroup SAMC21_PORT Port Module */ 37 /*@{*/ 38 39 #define PORT_U2210 40 #define REV_PORT 0x211 41 42 /* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 uint32_t reg; /*!< Type used for register access */ 46 } PORT_DIR_Type; 47 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 48 49 #define PORT_DIR_OFFSET 0x00 /**< \brief (PORT_DIR offset) Data Direction */ 50 #define PORT_DIR_RESETVALUE _U_(0x00000000) /**< \brief (PORT_DIR reset_value) Data Direction */ 51 #define PORT_DIR_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_DIR) MASK Register */ 52 53 /* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */ 54 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 55 typedef union { 56 uint32_t reg; /*!< Type used for register access */ 57 } PORT_DIRCLR_Type; 58 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 59 60 #define PORT_DIRCLR_OFFSET 0x04 /**< \brief (PORT_DIRCLR offset) Data Direction Clear */ 61 #define PORT_DIRCLR_RESETVALUE _U_(0x00000000) /**< \brief (PORT_DIRCLR reset_value) Data Direction Clear */ 62 #define PORT_DIRCLR_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_DIRCLR) MASK Register */ 63 64 /* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */ 65 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 66 typedef union { 67 uint32_t reg; /*!< Type used for register access */ 68 } PORT_DIRSET_Type; 69 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 70 71 #define PORT_DIRSET_OFFSET 0x08 /**< \brief (PORT_DIRSET offset) Data Direction Set */ 72 #define PORT_DIRSET_RESETVALUE _U_(0x00000000) /**< \brief (PORT_DIRSET reset_value) Data Direction Set */ 73 #define PORT_DIRSET_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_DIRSET) MASK Register */ 74 75 /* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */ 76 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 77 typedef union { 78 uint32_t reg; /*!< Type used for register access */ 79 } PORT_DIRTGL_Type; 80 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 81 82 #define PORT_DIRTGL_OFFSET 0x0C /**< \brief (PORT_DIRTGL offset) Data Direction Toggle */ 83 #define PORT_DIRTGL_RESETVALUE _U_(0x00000000) /**< \brief (PORT_DIRTGL reset_value) Data Direction Toggle */ 84 #define PORT_DIRTGL_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_DIRTGL) MASK Register */ 85 86 /* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */ 87 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 88 typedef union { 89 uint32_t reg; /*!< Type used for register access */ 90 } PORT_OUT_Type; 91 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 92 93 #define PORT_OUT_OFFSET 0x10 /**< \brief (PORT_OUT offset) Data Output Value */ 94 #define PORT_OUT_RESETVALUE _U_(0x00000000) /**< \brief (PORT_OUT reset_value) Data Output Value */ 95 #define PORT_OUT_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_OUT) MASK Register */ 96 97 /* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */ 98 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 99 typedef union { 100 uint32_t reg; /*!< Type used for register access */ 101 } PORT_OUTCLR_Type; 102 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 103 104 #define PORT_OUTCLR_OFFSET 0x14 /**< \brief (PORT_OUTCLR offset) Data Output Value Clear */ 105 #define PORT_OUTCLR_RESETVALUE _U_(0x00000000) /**< \brief (PORT_OUTCLR reset_value) Data Output Value Clear */ 106 #define PORT_OUTCLR_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_OUTCLR) MASK Register */ 107 108 /* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */ 109 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 110 typedef union { 111 uint32_t reg; /*!< Type used for register access */ 112 } PORT_OUTSET_Type; 113 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 114 115 #define PORT_OUTSET_OFFSET 0x18 /**< \brief (PORT_OUTSET offset) Data Output Value Set */ 116 #define PORT_OUTSET_RESETVALUE _U_(0x00000000) /**< \brief (PORT_OUTSET reset_value) Data Output Value Set */ 117 #define PORT_OUTSET_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_OUTSET) MASK Register */ 118 119 /* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */ 120 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 121 typedef union { 122 uint32_t reg; /*!< Type used for register access */ 123 } PORT_OUTTGL_Type; 124 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 125 126 #define PORT_OUTTGL_OFFSET 0x1C /**< \brief (PORT_OUTTGL offset) Data Output Value Toggle */ 127 #define PORT_OUTTGL_RESETVALUE _U_(0x00000000) /**< \brief (PORT_OUTTGL reset_value) Data Output Value Toggle */ 128 #define PORT_OUTTGL_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_OUTTGL) MASK Register */ 129 130 /* -------- PORT_IN : (PORT Offset: 0x20) (R/ 32) GROUP Data Input Value -------- */ 131 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 132 typedef union { 133 uint32_t reg; /*!< Type used for register access */ 134 } PORT_IN_Type; 135 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 136 137 #define PORT_IN_OFFSET 0x20 /**< \brief (PORT_IN offset) Data Input Value */ 138 #define PORT_IN_RESETVALUE _U_(0x00000000) /**< \brief (PORT_IN reset_value) Data Input Value */ 139 #define PORT_IN_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_IN) MASK Register */ 140 141 /* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */ 142 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 143 typedef union { 144 struct { 145 uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */ 146 } bit; /*!< Structure used for bit access */ 147 uint32_t reg; /*!< Type used for register access */ 148 } PORT_CTRL_Type; 149 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 150 151 #define PORT_CTRL_OFFSET 0x24 /**< \brief (PORT_CTRL offset) Control */ 152 #define PORT_CTRL_RESETVALUE _U_(0x00000000) /**< \brief (PORT_CTRL reset_value) Control */ 153 154 #define PORT_CTRL_SAMPLING_Pos 0 /**< \brief (PORT_CTRL) Input Sampling Mode */ 155 #define PORT_CTRL_SAMPLING_Msk (_U_(0xFFFFFFFF) << PORT_CTRL_SAMPLING_Pos) 156 #define PORT_CTRL_SAMPLING(value) (PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos)) 157 #define PORT_CTRL_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_CTRL) MASK Register */ 158 159 /* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */ 160 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 161 typedef union { 162 struct { 163 uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */ 164 uint32_t PMUXEN:1; /*!< bit: 16 Select Peripheral Multiplexer */ 165 uint32_t INEN:1; /*!< bit: 17 Input Enable */ 166 uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */ 167 uint32_t :3; /*!< bit: 19..21 Reserved */ 168 uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */ 169 uint32_t :1; /*!< bit: 23 Reserved */ 170 uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing Template */ 171 uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX Registers */ 172 uint32_t :1; /*!< bit: 29 Reserved */ 173 uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG Registers */ 174 uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */ 175 } bit; /*!< Structure used for bit access */ 176 uint32_t reg; /*!< Type used for register access */ 177 } PORT_WRCONFIG_Type; 178 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 179 180 #define PORT_WRCONFIG_OFFSET 0x28 /**< \brief (PORT_WRCONFIG offset) Write Configuration */ 181 #define PORT_WRCONFIG_RESETVALUE _U_(0x00000000) /**< \brief (PORT_WRCONFIG reset_value) Write Configuration */ 182 183 #define PORT_WRCONFIG_PINMASK_Pos 0 /**< \brief (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration */ 184 #define PORT_WRCONFIG_PINMASK_Msk (_U_(0xFFFF) << PORT_WRCONFIG_PINMASK_Pos) 185 #define PORT_WRCONFIG_PINMASK(value) (PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos)) 186 #define PORT_WRCONFIG_PMUXEN_Pos 16 /**< \brief (PORT_WRCONFIG) Select Peripheral Multiplexer */ 187 #define PORT_WRCONFIG_PMUXEN (_U_(0x1) << PORT_WRCONFIG_PMUXEN_Pos) 188 #define PORT_WRCONFIG_INEN_Pos 17 /**< \brief (PORT_WRCONFIG) Input Enable */ 189 #define PORT_WRCONFIG_INEN (_U_(0x1) << PORT_WRCONFIG_INEN_Pos) 190 #define PORT_WRCONFIG_PULLEN_Pos 18 /**< \brief (PORT_WRCONFIG) Pull Enable */ 191 #define PORT_WRCONFIG_PULLEN (_U_(0x1) << PORT_WRCONFIG_PULLEN_Pos) 192 #define PORT_WRCONFIG_DRVSTR_Pos 22 /**< \brief (PORT_WRCONFIG) Output Driver Strength Selection */ 193 #define PORT_WRCONFIG_DRVSTR (_U_(0x1) << PORT_WRCONFIG_DRVSTR_Pos) 194 #define PORT_WRCONFIG_PMUX_Pos 24 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexing Template */ 195 #define PORT_WRCONFIG_PMUX_Msk (_U_(0xF) << PORT_WRCONFIG_PMUX_Pos) 196 #define PORT_WRCONFIG_PMUX(value) (PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos)) 197 #define PORT_WRCONFIG_WRPMUX_Pos 28 /**< \brief (PORT_WRCONFIG) Write PMUX Registers */ 198 #define PORT_WRCONFIG_WRPMUX (_U_(0x1) << PORT_WRCONFIG_WRPMUX_Pos) 199 #define PORT_WRCONFIG_WRPINCFG_Pos 30 /**< \brief (PORT_WRCONFIG) Write PINCFG Registers */ 200 #define PORT_WRCONFIG_WRPINCFG (_U_(0x1) << PORT_WRCONFIG_WRPINCFG_Pos) 201 #define PORT_WRCONFIG_HWSEL_Pos 31 /**< \brief (PORT_WRCONFIG) Half-Word Select */ 202 #define PORT_WRCONFIG_HWSEL (_U_(0x1) << PORT_WRCONFIG_HWSEL_Pos) 203 #define PORT_WRCONFIG_MASK _U_(0xDF47FFFF) /**< \brief (PORT_WRCONFIG) MASK Register */ 204 205 /* -------- PORT_EVCTRL : (PORT Offset: 0x2C) (R/W 32) GROUP Event Input Control -------- */ 206 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 207 typedef union { 208 struct { 209 uint32_t PID0:5; /*!< bit: 0.. 4 Port Event Pin Identifier 0 */ 210 uint32_t EVACT0:2; /*!< bit: 5.. 6 Port Event Action 0 */ 211 uint32_t PORTEI0:1; /*!< bit: 7 Port Event Enable Input 0 */ 212 uint32_t PID1:5; /*!< bit: 8..12 Port Event Pin Identifier 1 */ 213 uint32_t EVACT1:2; /*!< bit: 13..14 Port Event Action 1 */ 214 uint32_t PORTEI1:1; /*!< bit: 15 Port Event Enable Input 1 */ 215 uint32_t PID2:5; /*!< bit: 16..20 Port Event Pin Identifier 2 */ 216 uint32_t EVACT2:2; /*!< bit: 21..22 Port Event Action 2 */ 217 uint32_t PORTEI2:1; /*!< bit: 23 Port Event Enable Input 2 */ 218 uint32_t PID3:5; /*!< bit: 24..28 Port Event Pin Identifier 3 */ 219 uint32_t EVACT3:2; /*!< bit: 29..30 Port Event Action 3 */ 220 uint32_t PORTEI3:1; /*!< bit: 31 Port Event Enable Input 3 */ 221 } bit; /*!< Structure used for bit access */ 222 uint32_t reg; /*!< Type used for register access */ 223 } PORT_EVCTRL_Type; 224 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 225 226 #define PORT_EVCTRL_OFFSET 0x2C /**< \brief (PORT_EVCTRL offset) Event Input Control */ 227 #define PORT_EVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (PORT_EVCTRL reset_value) Event Input Control */ 228 229 #define PORT_EVCTRL_PID0_Pos 0 /**< \brief (PORT_EVCTRL) Port Event Pin Identifier 0 */ 230 #define PORT_EVCTRL_PID0_Msk (_U_(0x1F) << PORT_EVCTRL_PID0_Pos) 231 #define PORT_EVCTRL_PID0(value) (PORT_EVCTRL_PID0_Msk & ((value) << PORT_EVCTRL_PID0_Pos)) 232 #define PORT_EVCTRL_EVACT0_Pos 5 /**< \brief (PORT_EVCTRL) Port Event Action 0 */ 233 #define PORT_EVCTRL_EVACT0_Msk (_U_(0x3) << PORT_EVCTRL_EVACT0_Pos) 234 #define PORT_EVCTRL_EVACT0(value) (PORT_EVCTRL_EVACT0_Msk & ((value) << PORT_EVCTRL_EVACT0_Pos)) 235 #define PORT_EVCTRL_EVACT0_OUT_Val _U_(0x0) /**< \brief (PORT_EVCTRL) Event output to pin */ 236 #define PORT_EVCTRL_EVACT0_SET_Val _U_(0x1) /**< \brief (PORT_EVCTRL) Set output register of pin on event */ 237 #define PORT_EVCTRL_EVACT0_CLR_Val _U_(0x2) /**< \brief (PORT_EVCTRL) Clear output register of pin on event */ 238 #define PORT_EVCTRL_EVACT0_TGL_Val _U_(0x3) /**< \brief (PORT_EVCTRL) Toggle output register of pin on event */ 239 #define PORT_EVCTRL_EVACT0_OUT (PORT_EVCTRL_EVACT0_OUT_Val << PORT_EVCTRL_EVACT0_Pos) 240 #define PORT_EVCTRL_EVACT0_SET (PORT_EVCTRL_EVACT0_SET_Val << PORT_EVCTRL_EVACT0_Pos) 241 #define PORT_EVCTRL_EVACT0_CLR (PORT_EVCTRL_EVACT0_CLR_Val << PORT_EVCTRL_EVACT0_Pos) 242 #define PORT_EVCTRL_EVACT0_TGL (PORT_EVCTRL_EVACT0_TGL_Val << PORT_EVCTRL_EVACT0_Pos) 243 #define PORT_EVCTRL_PORTEI0_Pos 7 /**< \brief (PORT_EVCTRL) Port Event Enable Input 0 */ 244 #define PORT_EVCTRL_PORTEI0 (_U_(0x1) << PORT_EVCTRL_PORTEI0_Pos) 245 #define PORT_EVCTRL_PID1_Pos 8 /**< \brief (PORT_EVCTRL) Port Event Pin Identifier 1 */ 246 #define PORT_EVCTRL_PID1_Msk (_U_(0x1F) << PORT_EVCTRL_PID1_Pos) 247 #define PORT_EVCTRL_PID1(value) (PORT_EVCTRL_PID1_Msk & ((value) << PORT_EVCTRL_PID1_Pos)) 248 #define PORT_EVCTRL_EVACT1_Pos 13 /**< \brief (PORT_EVCTRL) Port Event Action 1 */ 249 #define PORT_EVCTRL_EVACT1_Msk (_U_(0x3) << PORT_EVCTRL_EVACT1_Pos) 250 #define PORT_EVCTRL_EVACT1(value) (PORT_EVCTRL_EVACT1_Msk & ((value) << PORT_EVCTRL_EVACT1_Pos)) 251 #define PORT_EVCTRL_PORTEI1_Pos 15 /**< \brief (PORT_EVCTRL) Port Event Enable Input 1 */ 252 #define PORT_EVCTRL_PORTEI1 (_U_(0x1) << PORT_EVCTRL_PORTEI1_Pos) 253 #define PORT_EVCTRL_PID2_Pos 16 /**< \brief (PORT_EVCTRL) Port Event Pin Identifier 2 */ 254 #define PORT_EVCTRL_PID2_Msk (_U_(0x1F) << PORT_EVCTRL_PID2_Pos) 255 #define PORT_EVCTRL_PID2(value) (PORT_EVCTRL_PID2_Msk & ((value) << PORT_EVCTRL_PID2_Pos)) 256 #define PORT_EVCTRL_EVACT2_Pos 21 /**< \brief (PORT_EVCTRL) Port Event Action 2 */ 257 #define PORT_EVCTRL_EVACT2_Msk (_U_(0x3) << PORT_EVCTRL_EVACT2_Pos) 258 #define PORT_EVCTRL_EVACT2(value) (PORT_EVCTRL_EVACT2_Msk & ((value) << PORT_EVCTRL_EVACT2_Pos)) 259 #define PORT_EVCTRL_PORTEI2_Pos 23 /**< \brief (PORT_EVCTRL) Port Event Enable Input 2 */ 260 #define PORT_EVCTRL_PORTEI2 (_U_(0x1) << PORT_EVCTRL_PORTEI2_Pos) 261 #define PORT_EVCTRL_PID3_Pos 24 /**< \brief (PORT_EVCTRL) Port Event Pin Identifier 3 */ 262 #define PORT_EVCTRL_PID3_Msk (_U_(0x1F) << PORT_EVCTRL_PID3_Pos) 263 #define PORT_EVCTRL_PID3(value) (PORT_EVCTRL_PID3_Msk & ((value) << PORT_EVCTRL_PID3_Pos)) 264 #define PORT_EVCTRL_EVACT3_Pos 29 /**< \brief (PORT_EVCTRL) Port Event Action 3 */ 265 #define PORT_EVCTRL_EVACT3_Msk (_U_(0x3) << PORT_EVCTRL_EVACT3_Pos) 266 #define PORT_EVCTRL_EVACT3(value) (PORT_EVCTRL_EVACT3_Msk & ((value) << PORT_EVCTRL_EVACT3_Pos)) 267 #define PORT_EVCTRL_PORTEI3_Pos 31 /**< \brief (PORT_EVCTRL) Port Event Enable Input 3 */ 268 #define PORT_EVCTRL_PORTEI3 (_U_(0x1) << PORT_EVCTRL_PORTEI3_Pos) 269 #define PORT_EVCTRL_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_EVCTRL) MASK Register */ 270 271 /* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) GROUP Peripheral Multiplexing n -------- */ 272 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 273 typedef union { 274 struct { 275 uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing for Even-Numbered Pin */ 276 uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing for Odd-Numbered Pin */ 277 } bit; /*!< Structure used for bit access */ 278 uint8_t reg; /*!< Type used for register access */ 279 } PORT_PMUX_Type; 280 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 281 282 #define PORT_PMUX_OFFSET 0x30 /**< \brief (PORT_PMUX offset) Peripheral Multiplexing n */ 283 #define PORT_PMUX_RESETVALUE _U_(0x00) /**< \brief (PORT_PMUX reset_value) Peripheral Multiplexing n */ 284 285 #define PORT_PMUX_PMUXE_Pos 0 /**< \brief (PORT_PMUX) Peripheral Multiplexing for Even-Numbered Pin */ 286 #define PORT_PMUX_PMUXE_Msk (_U_(0xF) << PORT_PMUX_PMUXE_Pos) 287 #define PORT_PMUX_PMUXE(value) (PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos)) 288 #define PORT_PMUX_PMUXO_Pos 4 /**< \brief (PORT_PMUX) Peripheral Multiplexing for Odd-Numbered Pin */ 289 #define PORT_PMUX_PMUXO_Msk (_U_(0xF) << PORT_PMUX_PMUXO_Pos) 290 #define PORT_PMUX_PMUXO(value) (PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos)) 291 #define PORT_PMUX_MASK _U_(0xFF) /**< \brief (PORT_PMUX) MASK Register */ 292 293 /* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) GROUP Pin Configuration n -------- */ 294 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 295 typedef union { 296 struct { 297 uint8_t PMUXEN:1; /*!< bit: 0 Select Peripheral Multiplexer */ 298 uint8_t INEN:1; /*!< bit: 1 Input Enable */ 299 uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */ 300 uint8_t :3; /*!< bit: 3.. 5 Reserved */ 301 uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */ 302 uint8_t :1; /*!< bit: 7 Reserved */ 303 } bit; /*!< Structure used for bit access */ 304 uint8_t reg; /*!< Type used for register access */ 305 } PORT_PINCFG_Type; 306 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 307 308 #define PORT_PINCFG_OFFSET 0x40 /**< \brief (PORT_PINCFG offset) Pin Configuration n */ 309 #define PORT_PINCFG_RESETVALUE _U_(0x00) /**< \brief (PORT_PINCFG reset_value) Pin Configuration n */ 310 311 #define PORT_PINCFG_PMUXEN_Pos 0 /**< \brief (PORT_PINCFG) Select Peripheral Multiplexer */ 312 #define PORT_PINCFG_PMUXEN (_U_(0x1) << PORT_PINCFG_PMUXEN_Pos) 313 #define PORT_PINCFG_INEN_Pos 1 /**< \brief (PORT_PINCFG) Input Enable */ 314 #define PORT_PINCFG_INEN (_U_(0x1) << PORT_PINCFG_INEN_Pos) 315 #define PORT_PINCFG_PULLEN_Pos 2 /**< \brief (PORT_PINCFG) Pull Enable */ 316 #define PORT_PINCFG_PULLEN (_U_(0x1) << PORT_PINCFG_PULLEN_Pos) 317 #define PORT_PINCFG_DRVSTR_Pos 6 /**< \brief (PORT_PINCFG) Output Driver Strength Selection */ 318 #define PORT_PINCFG_DRVSTR (_U_(0x1) << PORT_PINCFG_DRVSTR_Pos) 319 #define PORT_PINCFG_MASK _U_(0x47) /**< \brief (PORT_PINCFG) MASK Register */ 320 321 /** \brief PortGroup hardware registers */ 322 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 323 typedef struct { 324 __IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */ 325 __IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */ 326 __IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */ 327 __IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */ 328 __IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */ 329 __IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */ 330 __IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */ 331 __IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */ 332 __I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */ 333 __IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */ 334 __O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */ 335 __IO PORT_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2C (R/W 32) Event Input Control */ 336 __IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing n */ 337 __IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration n */ 338 RoReg8 Reserved1[0x20]; 339 } PortGroup; 340 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 341 342 /** \brief PORT hardware registers */ 343 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 344 typedef struct { 345 PortGroup Group[2]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */ 346 } Port; 347 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 348 349 /*@}*/ 350 351 #endif /* _SAMC21_PORT_COMPONENT_ */ 352
