1 /** 2 * \file 3 * 4 * \brief Component description for PAC 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMC21_PAC_COMPONENT_ 31 #define _SAMC21_PAC_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR PAC */ 35 /* ========================================================================== */ 36 /** \addtogroup SAMC21_PAC Peripheral Access Controller */ 37 /*@{*/ 38 39 #define PAC_U2120 40 #define REV_PAC 0x110 41 42 /* -------- PAC_WRCTRL : (PAC Offset: 0x00) (R/W 32) Write control -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint32_t PERID:16; /*!< bit: 0..15 Peripheral identifier */ 47 uint32_t KEY:8; /*!< bit: 16..23 Peripheral access control key */ 48 uint32_t :8; /*!< bit: 24..31 Reserved */ 49 } bit; /*!< Structure used for bit access */ 50 uint32_t reg; /*!< Type used for register access */ 51 } PAC_WRCTRL_Type; 52 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 53 54 #define PAC_WRCTRL_OFFSET 0x00 /**< \brief (PAC_WRCTRL offset) Write control */ 55 #define PAC_WRCTRL_RESETVALUE _U_(0x00000000) /**< \brief (PAC_WRCTRL reset_value) Write control */ 56 57 #define PAC_WRCTRL_PERID_Pos 0 /**< \brief (PAC_WRCTRL) Peripheral identifier */ 58 #define PAC_WRCTRL_PERID_Msk (_U_(0xFFFF) << PAC_WRCTRL_PERID_Pos) 59 #define PAC_WRCTRL_PERID(value) (PAC_WRCTRL_PERID_Msk & ((value) << PAC_WRCTRL_PERID_Pos)) 60 #define PAC_WRCTRL_KEY_Pos 16 /**< \brief (PAC_WRCTRL) Peripheral access control key */ 61 #define PAC_WRCTRL_KEY_Msk (_U_(0xFF) << PAC_WRCTRL_KEY_Pos) 62 #define PAC_WRCTRL_KEY(value) (PAC_WRCTRL_KEY_Msk & ((value) << PAC_WRCTRL_KEY_Pos)) 63 #define PAC_WRCTRL_KEY_OFF_Val _U_(0x0) /**< \brief (PAC_WRCTRL) No action */ 64 #define PAC_WRCTRL_KEY_CLR_Val _U_(0x1) /**< \brief (PAC_WRCTRL) Clear protection */ 65 #define PAC_WRCTRL_KEY_SET_Val _U_(0x2) /**< \brief (PAC_WRCTRL) Set protection */ 66 #define PAC_WRCTRL_KEY_SETLCK_Val _U_(0x3) /**< \brief (PAC_WRCTRL) Set and lock protection */ 67 #define PAC_WRCTRL_KEY_OFF (PAC_WRCTRL_KEY_OFF_Val << PAC_WRCTRL_KEY_Pos) 68 #define PAC_WRCTRL_KEY_CLR (PAC_WRCTRL_KEY_CLR_Val << PAC_WRCTRL_KEY_Pos) 69 #define PAC_WRCTRL_KEY_SET (PAC_WRCTRL_KEY_SET_Val << PAC_WRCTRL_KEY_Pos) 70 #define PAC_WRCTRL_KEY_SETLCK (PAC_WRCTRL_KEY_SETLCK_Val << PAC_WRCTRL_KEY_Pos) 71 #define PAC_WRCTRL_MASK _U_(0x00FFFFFF) /**< \brief (PAC_WRCTRL) MASK Register */ 72 73 /* -------- PAC_EVCTRL : (PAC Offset: 0x04) (R/W 8) Event control -------- */ 74 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 75 typedef union { 76 struct { 77 uint8_t ERREO:1; /*!< bit: 0 Peripheral acess error event output */ 78 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 79 } bit; /*!< Structure used for bit access */ 80 uint8_t reg; /*!< Type used for register access */ 81 } PAC_EVCTRL_Type; 82 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 83 84 #define PAC_EVCTRL_OFFSET 0x04 /**< \brief (PAC_EVCTRL offset) Event control */ 85 #define PAC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (PAC_EVCTRL reset_value) Event control */ 86 87 #define PAC_EVCTRL_ERREO_Pos 0 /**< \brief (PAC_EVCTRL) Peripheral acess error event output */ 88 #define PAC_EVCTRL_ERREO (_U_(0x1) << PAC_EVCTRL_ERREO_Pos) 89 #define PAC_EVCTRL_MASK _U_(0x01) /**< \brief (PAC_EVCTRL) MASK Register */ 90 91 /* -------- PAC_INTENCLR : (PAC Offset: 0x08) (R/W 8) Interrupt enable clear -------- */ 92 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 93 typedef union { 94 struct { 95 uint8_t ERR:1; /*!< bit: 0 Peripheral access error interrupt disable */ 96 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 97 } bit; /*!< Structure used for bit access */ 98 uint8_t reg; /*!< Type used for register access */ 99 } PAC_INTENCLR_Type; 100 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 101 102 #define PAC_INTENCLR_OFFSET 0x08 /**< \brief (PAC_INTENCLR offset) Interrupt enable clear */ 103 #define PAC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (PAC_INTENCLR reset_value) Interrupt enable clear */ 104 105 #define PAC_INTENCLR_ERR_Pos 0 /**< \brief (PAC_INTENCLR) Peripheral access error interrupt disable */ 106 #define PAC_INTENCLR_ERR (_U_(0x1) << PAC_INTENCLR_ERR_Pos) 107 #define PAC_INTENCLR_MASK _U_(0x01) /**< \brief (PAC_INTENCLR) MASK Register */ 108 109 /* -------- PAC_INTENSET : (PAC Offset: 0x09) (R/W 8) Interrupt enable set -------- */ 110 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 111 typedef union { 112 struct { 113 uint8_t ERR:1; /*!< bit: 0 Peripheral access error interrupt enable */ 114 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 115 } bit; /*!< Structure used for bit access */ 116 uint8_t reg; /*!< Type used for register access */ 117 } PAC_INTENSET_Type; 118 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 119 120 #define PAC_INTENSET_OFFSET 0x09 /**< \brief (PAC_INTENSET offset) Interrupt enable set */ 121 #define PAC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (PAC_INTENSET reset_value) Interrupt enable set */ 122 123 #define PAC_INTENSET_ERR_Pos 0 /**< \brief (PAC_INTENSET) Peripheral access error interrupt enable */ 124 #define PAC_INTENSET_ERR (_U_(0x1) << PAC_INTENSET_ERR_Pos) 125 #define PAC_INTENSET_MASK _U_(0x01) /**< \brief (PAC_INTENSET) MASK Register */ 126 127 /* -------- PAC_INTFLAGAHB : (PAC Offset: 0x10) (R/W 32) Bridge interrupt flag status -------- */ 128 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 129 typedef union { // __I to avoid read-modify-write on write-to-clear register 130 struct { 131 __I uint32_t FLASH_:1; /*!< bit: 0 FLASH */ 132 __I uint32_t HSRAMCM0P_:1; /*!< bit: 1 HSRAMCM0P */ 133 __I uint32_t HSRAMDSU_:1; /*!< bit: 2 HSRAMDSU */ 134 __I uint32_t HPB1_:1; /*!< bit: 3 HPB1 */ 135 __I uint32_t HPB0_:1; /*!< bit: 4 HPB0 */ 136 __I uint32_t HPB2_:1; /*!< bit: 5 HPB2 */ 137 __I uint32_t LPRAMDMAC_:1; /*!< bit: 6 LPRAMDMAC */ 138 __I uint32_t DIVAS_:1; /*!< bit: 7 DIVAS */ 139 __I uint32_t Reserved1:24; /*!< bit: 8..31 Reserved */ 140 } bit; /*!< Structure used for bit access */ 141 uint32_t reg; /*!< Type used for register access */ 142 } PAC_INTFLAGAHB_Type; 143 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 144 145 #define PAC_INTFLAGAHB_OFFSET 0x10 /**< \brief (PAC_INTFLAGAHB offset) Bridge interrupt flag status */ 146 #define PAC_INTFLAGAHB_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGAHB reset_value) Bridge interrupt flag status */ 147 148 #define PAC_INTFLAGAHB_FLASH_Pos 0 /**< \brief (PAC_INTFLAGAHB) FLASH */ 149 #define PAC_INTFLAGAHB_FLASH (_U_(0x1) << PAC_INTFLAGAHB_FLASH_Pos) 150 #define PAC_INTFLAGAHB_HSRAMCM0P_Pos 1 /**< \brief (PAC_INTFLAGAHB) HSRAMCM0P */ 151 #define PAC_INTFLAGAHB_HSRAMCM0P (_U_(0x1) << PAC_INTFLAGAHB_HSRAMCM0P_Pos) 152 #define PAC_INTFLAGAHB_HSRAMDSU_Pos 2 /**< \brief (PAC_INTFLAGAHB) HSRAMDSU */ 153 #define PAC_INTFLAGAHB_HSRAMDSU (_U_(0x1) << PAC_INTFLAGAHB_HSRAMDSU_Pos) 154 #define PAC_INTFLAGAHB_HPB1_Pos 3 /**< \brief (PAC_INTFLAGAHB) HPB1 */ 155 #define PAC_INTFLAGAHB_HPB1 (_U_(0x1) << PAC_INTFLAGAHB_HPB1_Pos) 156 #define PAC_INTFLAGAHB_HPB0_Pos 4 /**< \brief (PAC_INTFLAGAHB) HPB0 */ 157 #define PAC_INTFLAGAHB_HPB0 (_U_(0x1) << PAC_INTFLAGAHB_HPB0_Pos) 158 #define PAC_INTFLAGAHB_HPB2_Pos 5 /**< \brief (PAC_INTFLAGAHB) HPB2 */ 159 #define PAC_INTFLAGAHB_HPB2 (_U_(0x1) << PAC_INTFLAGAHB_HPB2_Pos) 160 #define PAC_INTFLAGAHB_LPRAMDMAC_Pos 6 /**< \brief (PAC_INTFLAGAHB) LPRAMDMAC */ 161 #define PAC_INTFLAGAHB_LPRAMDMAC (_U_(0x1) << PAC_INTFLAGAHB_LPRAMDMAC_Pos) 162 #define PAC_INTFLAGAHB_DIVAS_Pos 7 /**< \brief (PAC_INTFLAGAHB) DIVAS */ 163 #define PAC_INTFLAGAHB_DIVAS (_U_(0x1) << PAC_INTFLAGAHB_DIVAS_Pos) 164 #define PAC_INTFLAGAHB_MASK _U_(0x000000FF) /**< \brief (PAC_INTFLAGAHB) MASK Register */ 165 166 /* -------- PAC_INTFLAGA : (PAC Offset: 0x14) (R/W 32) Peripheral interrupt flag status - Bridge A -------- */ 167 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 168 typedef union { // __I to avoid read-modify-write on write-to-clear register 169 struct { 170 __I uint32_t PAC_:1; /*!< bit: 0 PAC */ 171 __I uint32_t PM_:1; /*!< bit: 1 PM */ 172 __I uint32_t MCLK_:1; /*!< bit: 2 MCLK */ 173 __I uint32_t RSTC_:1; /*!< bit: 3 RSTC */ 174 __I uint32_t OSCCTRL_:1; /*!< bit: 4 OSCCTRL */ 175 __I uint32_t OSC32KCTRL_:1; /*!< bit: 5 OSC32KCTRL */ 176 __I uint32_t SUPC_:1; /*!< bit: 6 SUPC */ 177 __I uint32_t GCLK_:1; /*!< bit: 7 GCLK */ 178 __I uint32_t WDT_:1; /*!< bit: 8 WDT */ 179 __I uint32_t RTC_:1; /*!< bit: 9 RTC */ 180 __I uint32_t EIC_:1; /*!< bit: 10 EIC */ 181 __I uint32_t FREQM_:1; /*!< bit: 11 FREQM */ 182 __I uint32_t TSENS_:1; /*!< bit: 12 TSENS */ 183 __I uint32_t Reserved1:19; /*!< bit: 13..31 Reserved */ 184 } bit; /*!< Structure used for bit access */ 185 uint32_t reg; /*!< Type used for register access */ 186 } PAC_INTFLAGA_Type; 187 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 188 189 #define PAC_INTFLAGA_OFFSET 0x14 /**< \brief (PAC_INTFLAGA offset) Peripheral interrupt flag status - Bridge A */ 190 #define PAC_INTFLAGA_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGA reset_value) Peripheral interrupt flag status - Bridge A */ 191 192 #define PAC_INTFLAGA_PAC_Pos 0 /**< \brief (PAC_INTFLAGA) PAC */ 193 #define PAC_INTFLAGA_PAC (_U_(0x1) << PAC_INTFLAGA_PAC_Pos) 194 #define PAC_INTFLAGA_PM_Pos 1 /**< \brief (PAC_INTFLAGA) PM */ 195 #define PAC_INTFLAGA_PM (_U_(0x1) << PAC_INTFLAGA_PM_Pos) 196 #define PAC_INTFLAGA_MCLK_Pos 2 /**< \brief (PAC_INTFLAGA) MCLK */ 197 #define PAC_INTFLAGA_MCLK (_U_(0x1) << PAC_INTFLAGA_MCLK_Pos) 198 #define PAC_INTFLAGA_RSTC_Pos 3 /**< \brief (PAC_INTFLAGA) RSTC */ 199 #define PAC_INTFLAGA_RSTC (_U_(0x1) << PAC_INTFLAGA_RSTC_Pos) 200 #define PAC_INTFLAGA_OSCCTRL_Pos 4 /**< \brief (PAC_INTFLAGA) OSCCTRL */ 201 #define PAC_INTFLAGA_OSCCTRL (_U_(0x1) << PAC_INTFLAGA_OSCCTRL_Pos) 202 #define PAC_INTFLAGA_OSC32KCTRL_Pos 5 /**< \brief (PAC_INTFLAGA) OSC32KCTRL */ 203 #define PAC_INTFLAGA_OSC32KCTRL (_U_(0x1) << PAC_INTFLAGA_OSC32KCTRL_Pos) 204 #define PAC_INTFLAGA_SUPC_Pos 6 /**< \brief (PAC_INTFLAGA) SUPC */ 205 #define PAC_INTFLAGA_SUPC (_U_(0x1) << PAC_INTFLAGA_SUPC_Pos) 206 #define PAC_INTFLAGA_GCLK_Pos 7 /**< \brief (PAC_INTFLAGA) GCLK */ 207 #define PAC_INTFLAGA_GCLK (_U_(0x1) << PAC_INTFLAGA_GCLK_Pos) 208 #define PAC_INTFLAGA_WDT_Pos 8 /**< \brief (PAC_INTFLAGA) WDT */ 209 #define PAC_INTFLAGA_WDT (_U_(0x1) << PAC_INTFLAGA_WDT_Pos) 210 #define PAC_INTFLAGA_RTC_Pos 9 /**< \brief (PAC_INTFLAGA) RTC */ 211 #define PAC_INTFLAGA_RTC (_U_(0x1) << PAC_INTFLAGA_RTC_Pos) 212 #define PAC_INTFLAGA_EIC_Pos 10 /**< \brief (PAC_INTFLAGA) EIC */ 213 #define PAC_INTFLAGA_EIC (_U_(0x1) << PAC_INTFLAGA_EIC_Pos) 214 #define PAC_INTFLAGA_FREQM_Pos 11 /**< \brief (PAC_INTFLAGA) FREQM */ 215 #define PAC_INTFLAGA_FREQM (_U_(0x1) << PAC_INTFLAGA_FREQM_Pos) 216 #define PAC_INTFLAGA_TSENS_Pos 12 /**< \brief (PAC_INTFLAGA) TSENS */ 217 #define PAC_INTFLAGA_TSENS (_U_(0x1) << PAC_INTFLAGA_TSENS_Pos) 218 #define PAC_INTFLAGA_MASK _U_(0x00001FFF) /**< \brief (PAC_INTFLAGA) MASK Register */ 219 220 /* -------- PAC_INTFLAGB : (PAC Offset: 0x18) (R/W 32) Peripheral interrupt flag status - Bridge B -------- */ 221 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 222 typedef union { // __I to avoid read-modify-write on write-to-clear register 223 struct { 224 __I uint32_t PORT_:1; /*!< bit: 0 PORT */ 225 __I uint32_t DSU_:1; /*!< bit: 1 DSU */ 226 __I uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL */ 227 __I uint32_t DMAC_:1; /*!< bit: 3 DMAC */ 228 __I uint32_t MTB_:1; /*!< bit: 4 MTB */ 229 __I uint32_t HMATRIXHS_:1; /*!< bit: 5 HMATRIXHS */ 230 __I uint32_t Reserved1:26; /*!< bit: 6..31 Reserved */ 231 } bit; /*!< Structure used for bit access */ 232 uint32_t reg; /*!< Type used for register access */ 233 } PAC_INTFLAGB_Type; 234 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 235 236 #define PAC_INTFLAGB_OFFSET 0x18 /**< \brief (PAC_INTFLAGB offset) Peripheral interrupt flag status - Bridge B */ 237 #define PAC_INTFLAGB_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGB reset_value) Peripheral interrupt flag status - Bridge B */ 238 239 #define PAC_INTFLAGB_PORT_Pos 0 /**< \brief (PAC_INTFLAGB) PORT */ 240 #define PAC_INTFLAGB_PORT (_U_(0x1) << PAC_INTFLAGB_PORT_Pos) 241 #define PAC_INTFLAGB_DSU_Pos 1 /**< \brief (PAC_INTFLAGB) DSU */ 242 #define PAC_INTFLAGB_DSU (_U_(0x1) << PAC_INTFLAGB_DSU_Pos) 243 #define PAC_INTFLAGB_NVMCTRL_Pos 2 /**< \brief (PAC_INTFLAGB) NVMCTRL */ 244 #define PAC_INTFLAGB_NVMCTRL (_U_(0x1) << PAC_INTFLAGB_NVMCTRL_Pos) 245 #define PAC_INTFLAGB_DMAC_Pos 3 /**< \brief (PAC_INTFLAGB) DMAC */ 246 #define PAC_INTFLAGB_DMAC (_U_(0x1) << PAC_INTFLAGB_DMAC_Pos) 247 #define PAC_INTFLAGB_MTB_Pos 4 /**< \brief (PAC_INTFLAGB) MTB */ 248 #define PAC_INTFLAGB_MTB (_U_(0x1) << PAC_INTFLAGB_MTB_Pos) 249 #define PAC_INTFLAGB_HMATRIXHS_Pos 5 /**< \brief (PAC_INTFLAGB) HMATRIXHS */ 250 #define PAC_INTFLAGB_HMATRIXHS (_U_(0x1) << PAC_INTFLAGB_HMATRIXHS_Pos) 251 #define PAC_INTFLAGB_MASK _U_(0x0000003F) /**< \brief (PAC_INTFLAGB) MASK Register */ 252 253 /* -------- PAC_INTFLAGC : (PAC Offset: 0x1C) (R/W 32) Peripheral interrupt flag status - Bridge C -------- */ 254 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 255 typedef union { // __I to avoid read-modify-write on write-to-clear register 256 struct { 257 __I uint32_t EVSYS_:1; /*!< bit: 0 EVSYS */ 258 __I uint32_t SERCOM0_:1; /*!< bit: 1 SERCOM0 */ 259 __I uint32_t SERCOM1_:1; /*!< bit: 2 SERCOM1 */ 260 __I uint32_t SERCOM2_:1; /*!< bit: 3 SERCOM2 */ 261 __I uint32_t SERCOM3_:1; /*!< bit: 4 SERCOM3 */ 262 __I uint32_t SERCOM4_:1; /*!< bit: 5 SERCOM4 */ 263 __I uint32_t SERCOM5_:1; /*!< bit: 6 SERCOM5 */ 264 __I uint32_t CAN0_:1; /*!< bit: 7 CAN0 */ 265 __I uint32_t CAN1_:1; /*!< bit: 8 CAN1 */ 266 __I uint32_t TCC0_:1; /*!< bit: 9 TCC0 */ 267 __I uint32_t TCC1_:1; /*!< bit: 10 TCC1 */ 268 __I uint32_t TCC2_:1; /*!< bit: 11 TCC2 */ 269 __I uint32_t TC0_:1; /*!< bit: 12 TC0 */ 270 __I uint32_t TC1_:1; /*!< bit: 13 TC1 */ 271 __I uint32_t TC2_:1; /*!< bit: 14 TC2 */ 272 __I uint32_t TC3_:1; /*!< bit: 15 TC3 */ 273 __I uint32_t TC4_:1; /*!< bit: 16 TC4 */ 274 __I uint32_t ADC0_:1; /*!< bit: 17 ADC0 */ 275 __I uint32_t ADC1_:1; /*!< bit: 18 ADC1 */ 276 __I uint32_t SDADC_:1; /*!< bit: 19 SDADC */ 277 __I uint32_t AC_:1; /*!< bit: 20 AC */ 278 __I uint32_t DAC_:1; /*!< bit: 21 DAC */ 279 __I uint32_t PTC_:1; /*!< bit: 22 PTC */ 280 __I uint32_t CCL_:1; /*!< bit: 23 CCL */ 281 __I uint32_t Reserved1:8; /*!< bit: 24..31 Reserved */ 282 } bit; /*!< Structure used for bit access */ 283 uint32_t reg; /*!< Type used for register access */ 284 } PAC_INTFLAGC_Type; 285 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 286 287 #define PAC_INTFLAGC_OFFSET 0x1C /**< \brief (PAC_INTFLAGC offset) Peripheral interrupt flag status - Bridge C */ 288 #define PAC_INTFLAGC_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGC reset_value) Peripheral interrupt flag status - Bridge C */ 289 290 #define PAC_INTFLAGC_EVSYS_Pos 0 /**< \brief (PAC_INTFLAGC) EVSYS */ 291 #define PAC_INTFLAGC_EVSYS (_U_(0x1) << PAC_INTFLAGC_EVSYS_Pos) 292 #define PAC_INTFLAGC_SERCOM0_Pos 1 /**< \brief (PAC_INTFLAGC) SERCOM0 */ 293 #define PAC_INTFLAGC_SERCOM0 (_U_(0x1) << PAC_INTFLAGC_SERCOM0_Pos) 294 #define PAC_INTFLAGC_SERCOM1_Pos 2 /**< \brief (PAC_INTFLAGC) SERCOM1 */ 295 #define PAC_INTFLAGC_SERCOM1 (_U_(0x1) << PAC_INTFLAGC_SERCOM1_Pos) 296 #define PAC_INTFLAGC_SERCOM2_Pos 3 /**< \brief (PAC_INTFLAGC) SERCOM2 */ 297 #define PAC_INTFLAGC_SERCOM2 (_U_(0x1) << PAC_INTFLAGC_SERCOM2_Pos) 298 #define PAC_INTFLAGC_SERCOM3_Pos 4 /**< \brief (PAC_INTFLAGC) SERCOM3 */ 299 #define PAC_INTFLAGC_SERCOM3 (_U_(0x1) << PAC_INTFLAGC_SERCOM3_Pos) 300 #define PAC_INTFLAGC_SERCOM4_Pos 5 /**< \brief (PAC_INTFLAGC) SERCOM4 */ 301 #define PAC_INTFLAGC_SERCOM4 (_U_(0x1) << PAC_INTFLAGC_SERCOM4_Pos) 302 #define PAC_INTFLAGC_SERCOM5_Pos 6 /**< \brief (PAC_INTFLAGC) SERCOM5 */ 303 #define PAC_INTFLAGC_SERCOM5 (_U_(0x1) << PAC_INTFLAGC_SERCOM5_Pos) 304 #define PAC_INTFLAGC_CAN0_Pos 7 /**< \brief (PAC_INTFLAGC) CAN0 */ 305 #define PAC_INTFLAGC_CAN0 (_U_(0x1) << PAC_INTFLAGC_CAN0_Pos) 306 #define PAC_INTFLAGC_CAN1_Pos 8 /**< \brief (PAC_INTFLAGC) CAN1 */ 307 #define PAC_INTFLAGC_CAN1 (_U_(0x1) << PAC_INTFLAGC_CAN1_Pos) 308 #define PAC_INTFLAGC_TCC0_Pos 9 /**< \brief (PAC_INTFLAGC) TCC0 */ 309 #define PAC_INTFLAGC_TCC0 (_U_(0x1) << PAC_INTFLAGC_TCC0_Pos) 310 #define PAC_INTFLAGC_TCC1_Pos 10 /**< \brief (PAC_INTFLAGC) TCC1 */ 311 #define PAC_INTFLAGC_TCC1 (_U_(0x1) << PAC_INTFLAGC_TCC1_Pos) 312 #define PAC_INTFLAGC_TCC2_Pos 11 /**< \brief (PAC_INTFLAGC) TCC2 */ 313 #define PAC_INTFLAGC_TCC2 (_U_(0x1) << PAC_INTFLAGC_TCC2_Pos) 314 #define PAC_INTFLAGC_TC0_Pos 12 /**< \brief (PAC_INTFLAGC) TC0 */ 315 #define PAC_INTFLAGC_TC0 (_U_(0x1) << PAC_INTFLAGC_TC0_Pos) 316 #define PAC_INTFLAGC_TC1_Pos 13 /**< \brief (PAC_INTFLAGC) TC1 */ 317 #define PAC_INTFLAGC_TC1 (_U_(0x1) << PAC_INTFLAGC_TC1_Pos) 318 #define PAC_INTFLAGC_TC2_Pos 14 /**< \brief (PAC_INTFLAGC) TC2 */ 319 #define PAC_INTFLAGC_TC2 (_U_(0x1) << PAC_INTFLAGC_TC2_Pos) 320 #define PAC_INTFLAGC_TC3_Pos 15 /**< \brief (PAC_INTFLAGC) TC3 */ 321 #define PAC_INTFLAGC_TC3 (_U_(0x1) << PAC_INTFLAGC_TC3_Pos) 322 #define PAC_INTFLAGC_TC4_Pos 16 /**< \brief (PAC_INTFLAGC) TC4 */ 323 #define PAC_INTFLAGC_TC4 (_U_(0x1) << PAC_INTFLAGC_TC4_Pos) 324 #define PAC_INTFLAGC_ADC0_Pos 17 /**< \brief (PAC_INTFLAGC) ADC0 */ 325 #define PAC_INTFLAGC_ADC0 (_U_(0x1) << PAC_INTFLAGC_ADC0_Pos) 326 #define PAC_INTFLAGC_ADC1_Pos 18 /**< \brief (PAC_INTFLAGC) ADC1 */ 327 #define PAC_INTFLAGC_ADC1 (_U_(0x1) << PAC_INTFLAGC_ADC1_Pos) 328 #define PAC_INTFLAGC_SDADC_Pos 19 /**< \brief (PAC_INTFLAGC) SDADC */ 329 #define PAC_INTFLAGC_SDADC (_U_(0x1) << PAC_INTFLAGC_SDADC_Pos) 330 #define PAC_INTFLAGC_AC_Pos 20 /**< \brief (PAC_INTFLAGC) AC */ 331 #define PAC_INTFLAGC_AC (_U_(0x1) << PAC_INTFLAGC_AC_Pos) 332 #define PAC_INTFLAGC_DAC_Pos 21 /**< \brief (PAC_INTFLAGC) DAC */ 333 #define PAC_INTFLAGC_DAC (_U_(0x1) << PAC_INTFLAGC_DAC_Pos) 334 #define PAC_INTFLAGC_PTC_Pos 22 /**< \brief (PAC_INTFLAGC) PTC */ 335 #define PAC_INTFLAGC_PTC (_U_(0x1) << PAC_INTFLAGC_PTC_Pos) 336 #define PAC_INTFLAGC_CCL_Pos 23 /**< \brief (PAC_INTFLAGC) CCL */ 337 #define PAC_INTFLAGC_CCL (_U_(0x1) << PAC_INTFLAGC_CCL_Pos) 338 #define PAC_INTFLAGC_MASK _U_(0x00FFFFFF) /**< \brief (PAC_INTFLAGC) MASK Register */ 339 340 /* -------- PAC_STATUSA : (PAC Offset: 0x34) (R/ 32) Peripheral write protection status - Bridge A -------- */ 341 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 342 typedef union { 343 struct { 344 uint32_t PAC_:1; /*!< bit: 0 PAC APB Protect Enable */ 345 uint32_t PM_:1; /*!< bit: 1 PM APB Protect Enable */ 346 uint32_t MCLK_:1; /*!< bit: 2 MCLK APB Protect Enable */ 347 uint32_t RSTC_:1; /*!< bit: 3 RSTC APB Protect Enable */ 348 uint32_t OSCCTRL_:1; /*!< bit: 4 OSCCTRL APB Protect Enable */ 349 uint32_t OSC32KCTRL_:1; /*!< bit: 5 OSC32KCTRL APB Protect Enable */ 350 uint32_t SUPC_:1; /*!< bit: 6 SUPC APB Protect Enable */ 351 uint32_t GCLK_:1; /*!< bit: 7 GCLK APB Protect Enable */ 352 uint32_t WDT_:1; /*!< bit: 8 WDT APB Protect Enable */ 353 uint32_t RTC_:1; /*!< bit: 9 RTC APB Protect Enable */ 354 uint32_t EIC_:1; /*!< bit: 10 EIC APB Protect Enable */ 355 uint32_t FREQM_:1; /*!< bit: 11 FREQM APB Protect Enable */ 356 uint32_t TSENS_:1; /*!< bit: 12 TSENS APB Protect Enable */ 357 uint32_t :19; /*!< bit: 13..31 Reserved */ 358 } bit; /*!< Structure used for bit access */ 359 uint32_t reg; /*!< Type used for register access */ 360 } PAC_STATUSA_Type; 361 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 362 363 #define PAC_STATUSA_OFFSET 0x34 /**< \brief (PAC_STATUSA offset) Peripheral write protection status - Bridge A */ 364 #define PAC_STATUSA_RESETVALUE _U_(0x00000000) /**< \brief (PAC_STATUSA reset_value) Peripheral write protection status - Bridge A */ 365 366 #define PAC_STATUSA_PAC_Pos 0 /**< \brief (PAC_STATUSA) PAC APB Protect Enable */ 367 #define PAC_STATUSA_PAC (_U_(0x1) << PAC_STATUSA_PAC_Pos) 368 #define PAC_STATUSA_PM_Pos 1 /**< \brief (PAC_STATUSA) PM APB Protect Enable */ 369 #define PAC_STATUSA_PM (_U_(0x1) << PAC_STATUSA_PM_Pos) 370 #define PAC_STATUSA_MCLK_Pos 2 /**< \brief (PAC_STATUSA) MCLK APB Protect Enable */ 371 #define PAC_STATUSA_MCLK (_U_(0x1) << PAC_STATUSA_MCLK_Pos) 372 #define PAC_STATUSA_RSTC_Pos 3 /**< \brief (PAC_STATUSA) RSTC APB Protect Enable */ 373 #define PAC_STATUSA_RSTC (_U_(0x1) << PAC_STATUSA_RSTC_Pos) 374 #define PAC_STATUSA_OSCCTRL_Pos 4 /**< \brief (PAC_STATUSA) OSCCTRL APB Protect Enable */ 375 #define PAC_STATUSA_OSCCTRL (_U_(0x1) << PAC_STATUSA_OSCCTRL_Pos) 376 #define PAC_STATUSA_OSC32KCTRL_Pos 5 /**< \brief (PAC_STATUSA) OSC32KCTRL APB Protect Enable */ 377 #define PAC_STATUSA_OSC32KCTRL (_U_(0x1) << PAC_STATUSA_OSC32KCTRL_Pos) 378 #define PAC_STATUSA_SUPC_Pos 6 /**< \brief (PAC_STATUSA) SUPC APB Protect Enable */ 379 #define PAC_STATUSA_SUPC (_U_(0x1) << PAC_STATUSA_SUPC_Pos) 380 #define PAC_STATUSA_GCLK_Pos 7 /**< \brief (PAC_STATUSA) GCLK APB Protect Enable */ 381 #define PAC_STATUSA_GCLK (_U_(0x1) << PAC_STATUSA_GCLK_Pos) 382 #define PAC_STATUSA_WDT_Pos 8 /**< \brief (PAC_STATUSA) WDT APB Protect Enable */ 383 #define PAC_STATUSA_WDT (_U_(0x1) << PAC_STATUSA_WDT_Pos) 384 #define PAC_STATUSA_RTC_Pos 9 /**< \brief (PAC_STATUSA) RTC APB Protect Enable */ 385 #define PAC_STATUSA_RTC (_U_(0x1) << PAC_STATUSA_RTC_Pos) 386 #define PAC_STATUSA_EIC_Pos 10 /**< \brief (PAC_STATUSA) EIC APB Protect Enable */ 387 #define PAC_STATUSA_EIC (_U_(0x1) << PAC_STATUSA_EIC_Pos) 388 #define PAC_STATUSA_FREQM_Pos 11 /**< \brief (PAC_STATUSA) FREQM APB Protect Enable */ 389 #define PAC_STATUSA_FREQM (_U_(0x1) << PAC_STATUSA_FREQM_Pos) 390 #define PAC_STATUSA_TSENS_Pos 12 /**< \brief (PAC_STATUSA) TSENS APB Protect Enable */ 391 #define PAC_STATUSA_TSENS (_U_(0x1) << PAC_STATUSA_TSENS_Pos) 392 #define PAC_STATUSA_MASK _U_(0x00001FFF) /**< \brief (PAC_STATUSA) MASK Register */ 393 394 /* -------- PAC_STATUSB : (PAC Offset: 0x38) (R/ 32) Peripheral write protection status - Bridge B -------- */ 395 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 396 typedef union { 397 struct { 398 uint32_t PORT_:1; /*!< bit: 0 PORT APB Protect Enable */ 399 uint32_t DSU_:1; /*!< bit: 1 DSU APB Protect Enable */ 400 uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Protect Enable */ 401 uint32_t DMAC_:1; /*!< bit: 3 DMAC APB Protect Enable */ 402 uint32_t MTB_:1; /*!< bit: 4 MTB APB Protect Enable */ 403 uint32_t HMATRIXHS_:1; /*!< bit: 5 HMATRIXHS APB Protect Enable */ 404 uint32_t :26; /*!< bit: 6..31 Reserved */ 405 } bit; /*!< Structure used for bit access */ 406 uint32_t reg; /*!< Type used for register access */ 407 } PAC_STATUSB_Type; 408 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 409 410 #define PAC_STATUSB_OFFSET 0x38 /**< \brief (PAC_STATUSB offset) Peripheral write protection status - Bridge B */ 411 #define PAC_STATUSB_RESETVALUE _U_(0x00000002) /**< \brief (PAC_STATUSB reset_value) Peripheral write protection status - Bridge B */ 412 413 #define PAC_STATUSB_PORT_Pos 0 /**< \brief (PAC_STATUSB) PORT APB Protect Enable */ 414 #define PAC_STATUSB_PORT (_U_(0x1) << PAC_STATUSB_PORT_Pos) 415 #define PAC_STATUSB_DSU_Pos 1 /**< \brief (PAC_STATUSB) DSU APB Protect Enable */ 416 #define PAC_STATUSB_DSU (_U_(0x1) << PAC_STATUSB_DSU_Pos) 417 #define PAC_STATUSB_NVMCTRL_Pos 2 /**< \brief (PAC_STATUSB) NVMCTRL APB Protect Enable */ 418 #define PAC_STATUSB_NVMCTRL (_U_(0x1) << PAC_STATUSB_NVMCTRL_Pos) 419 #define PAC_STATUSB_DMAC_Pos 3 /**< \brief (PAC_STATUSB) DMAC APB Protect Enable */ 420 #define PAC_STATUSB_DMAC (_U_(0x1) << PAC_STATUSB_DMAC_Pos) 421 #define PAC_STATUSB_MTB_Pos 4 /**< \brief (PAC_STATUSB) MTB APB Protect Enable */ 422 #define PAC_STATUSB_MTB (_U_(0x1) << PAC_STATUSB_MTB_Pos) 423 #define PAC_STATUSB_HMATRIXHS_Pos 5 /**< \brief (PAC_STATUSB) HMATRIXHS APB Protect Enable */ 424 #define PAC_STATUSB_HMATRIXHS (_U_(0x1) << PAC_STATUSB_HMATRIXHS_Pos) 425 #define PAC_STATUSB_MASK _U_(0x0000003F) /**< \brief (PAC_STATUSB) MASK Register */ 426 427 /* -------- PAC_STATUSC : (PAC Offset: 0x3C) (R/ 32) Peripheral write protection status - Bridge C -------- */ 428 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 429 typedef union { 430 struct { 431 uint32_t EVSYS_:1; /*!< bit: 0 EVSYS APB Protect Enable */ 432 uint32_t SERCOM0_:1; /*!< bit: 1 SERCOM0 APB Protect Enable */ 433 uint32_t SERCOM1_:1; /*!< bit: 2 SERCOM1 APB Protect Enable */ 434 uint32_t SERCOM2_:1; /*!< bit: 3 SERCOM2 APB Protect Enable */ 435 uint32_t SERCOM3_:1; /*!< bit: 4 SERCOM3 APB Protect Enable */ 436 uint32_t SERCOM4_:1; /*!< bit: 5 SERCOM4 APB Protect Enable */ 437 uint32_t SERCOM5_:1; /*!< bit: 6 SERCOM5 APB Protect Enable */ 438 uint32_t CAN0_:1; /*!< bit: 7 CAN0 APB Protect Enable */ 439 uint32_t CAN1_:1; /*!< bit: 8 CAN1 APB Protect Enable */ 440 uint32_t TCC0_:1; /*!< bit: 9 TCC0 APB Protect Enable */ 441 uint32_t TCC1_:1; /*!< bit: 10 TCC1 APB Protect Enable */ 442 uint32_t TCC2_:1; /*!< bit: 11 TCC2 APB Protect Enable */ 443 uint32_t TC0_:1; /*!< bit: 12 TC0 APB Protect Enable */ 444 uint32_t TC1_:1; /*!< bit: 13 TC1 APB Protect Enable */ 445 uint32_t TC2_:1; /*!< bit: 14 TC2 APB Protect Enable */ 446 uint32_t TC3_:1; /*!< bit: 15 TC3 APB Protect Enable */ 447 uint32_t TC4_:1; /*!< bit: 16 TC4 APB Protect Enable */ 448 uint32_t ADC0_:1; /*!< bit: 17 ADC0 APB Protect Enable */ 449 uint32_t ADC1_:1; /*!< bit: 18 ADC1 APB Protect Enable */ 450 uint32_t SDADC_:1; /*!< bit: 19 SDADC APB Protect Enable */ 451 uint32_t AC_:1; /*!< bit: 20 AC APB Protect Enable */ 452 uint32_t DAC_:1; /*!< bit: 21 DAC APB Protect Enable */ 453 uint32_t PTC_:1; /*!< bit: 22 PTC APB Protect Enable */ 454 uint32_t CCL_:1; /*!< bit: 23 CCL APB Protect Enable */ 455 uint32_t :8; /*!< bit: 24..31 Reserved */ 456 } bit; /*!< Structure used for bit access */ 457 uint32_t reg; /*!< Type used for register access */ 458 } PAC_STATUSC_Type; 459 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 460 461 #define PAC_STATUSC_OFFSET 0x3C /**< \brief (PAC_STATUSC offset) Peripheral write protection status - Bridge C */ 462 #define PAC_STATUSC_RESETVALUE _U_(0x02000000) /**< \brief (PAC_STATUSC reset_value) Peripheral write protection status - Bridge C */ 463 464 #define PAC_STATUSC_EVSYS_Pos 0 /**< \brief (PAC_STATUSC) EVSYS APB Protect Enable */ 465 #define PAC_STATUSC_EVSYS (_U_(0x1) << PAC_STATUSC_EVSYS_Pos) 466 #define PAC_STATUSC_SERCOM0_Pos 1 /**< \brief (PAC_STATUSC) SERCOM0 APB Protect Enable */ 467 #define PAC_STATUSC_SERCOM0 (_U_(0x1) << PAC_STATUSC_SERCOM0_Pos) 468 #define PAC_STATUSC_SERCOM1_Pos 2 /**< \brief (PAC_STATUSC) SERCOM1 APB Protect Enable */ 469 #define PAC_STATUSC_SERCOM1 (_U_(0x1) << PAC_STATUSC_SERCOM1_Pos) 470 #define PAC_STATUSC_SERCOM2_Pos 3 /**< \brief (PAC_STATUSC) SERCOM2 APB Protect Enable */ 471 #define PAC_STATUSC_SERCOM2 (_U_(0x1) << PAC_STATUSC_SERCOM2_Pos) 472 #define PAC_STATUSC_SERCOM3_Pos 4 /**< \brief (PAC_STATUSC) SERCOM3 APB Protect Enable */ 473 #define PAC_STATUSC_SERCOM3 (_U_(0x1) << PAC_STATUSC_SERCOM3_Pos) 474 #define PAC_STATUSC_SERCOM4_Pos 5 /**< \brief (PAC_STATUSC) SERCOM4 APB Protect Enable */ 475 #define PAC_STATUSC_SERCOM4 (_U_(0x1) << PAC_STATUSC_SERCOM4_Pos) 476 #define PAC_STATUSC_SERCOM5_Pos 6 /**< \brief (PAC_STATUSC) SERCOM5 APB Protect Enable */ 477 #define PAC_STATUSC_SERCOM5 (_U_(0x1) << PAC_STATUSC_SERCOM5_Pos) 478 #define PAC_STATUSC_CAN0_Pos 7 /**< \brief (PAC_STATUSC) CAN0 APB Protect Enable */ 479 #define PAC_STATUSC_CAN0 (_U_(0x1) << PAC_STATUSC_CAN0_Pos) 480 #define PAC_STATUSC_CAN1_Pos 8 /**< \brief (PAC_STATUSC) CAN1 APB Protect Enable */ 481 #define PAC_STATUSC_CAN1 (_U_(0x1) << PAC_STATUSC_CAN1_Pos) 482 #define PAC_STATUSC_TCC0_Pos 9 /**< \brief (PAC_STATUSC) TCC0 APB Protect Enable */ 483 #define PAC_STATUSC_TCC0 (_U_(0x1) << PAC_STATUSC_TCC0_Pos) 484 #define PAC_STATUSC_TCC1_Pos 10 /**< \brief (PAC_STATUSC) TCC1 APB Protect Enable */ 485 #define PAC_STATUSC_TCC1 (_U_(0x1) << PAC_STATUSC_TCC1_Pos) 486 #define PAC_STATUSC_TCC2_Pos 11 /**< \brief (PAC_STATUSC) TCC2 APB Protect Enable */ 487 #define PAC_STATUSC_TCC2 (_U_(0x1) << PAC_STATUSC_TCC2_Pos) 488 #define PAC_STATUSC_TC0_Pos 12 /**< \brief (PAC_STATUSC) TC0 APB Protect Enable */ 489 #define PAC_STATUSC_TC0 (_U_(0x1) << PAC_STATUSC_TC0_Pos) 490 #define PAC_STATUSC_TC1_Pos 13 /**< \brief (PAC_STATUSC) TC1 APB Protect Enable */ 491 #define PAC_STATUSC_TC1 (_U_(0x1) << PAC_STATUSC_TC1_Pos) 492 #define PAC_STATUSC_TC2_Pos 14 /**< \brief (PAC_STATUSC) TC2 APB Protect Enable */ 493 #define PAC_STATUSC_TC2 (_U_(0x1) << PAC_STATUSC_TC2_Pos) 494 #define PAC_STATUSC_TC3_Pos 15 /**< \brief (PAC_STATUSC) TC3 APB Protect Enable */ 495 #define PAC_STATUSC_TC3 (_U_(0x1) << PAC_STATUSC_TC3_Pos) 496 #define PAC_STATUSC_TC4_Pos 16 /**< \brief (PAC_STATUSC) TC4 APB Protect Enable */ 497 #define PAC_STATUSC_TC4 (_U_(0x1) << PAC_STATUSC_TC4_Pos) 498 #define PAC_STATUSC_ADC0_Pos 17 /**< \brief (PAC_STATUSC) ADC0 APB Protect Enable */ 499 #define PAC_STATUSC_ADC0 (_U_(0x1) << PAC_STATUSC_ADC0_Pos) 500 #define PAC_STATUSC_ADC1_Pos 18 /**< \brief (PAC_STATUSC) ADC1 APB Protect Enable */ 501 #define PAC_STATUSC_ADC1 (_U_(0x1) << PAC_STATUSC_ADC1_Pos) 502 #define PAC_STATUSC_SDADC_Pos 19 /**< \brief (PAC_STATUSC) SDADC APB Protect Enable */ 503 #define PAC_STATUSC_SDADC (_U_(0x1) << PAC_STATUSC_SDADC_Pos) 504 #define PAC_STATUSC_AC_Pos 20 /**< \brief (PAC_STATUSC) AC APB Protect Enable */ 505 #define PAC_STATUSC_AC (_U_(0x1) << PAC_STATUSC_AC_Pos) 506 #define PAC_STATUSC_DAC_Pos 21 /**< \brief (PAC_STATUSC) DAC APB Protect Enable */ 507 #define PAC_STATUSC_DAC (_U_(0x1) << PAC_STATUSC_DAC_Pos) 508 #define PAC_STATUSC_PTC_Pos 22 /**< \brief (PAC_STATUSC) PTC APB Protect Enable */ 509 #define PAC_STATUSC_PTC (_U_(0x1) << PAC_STATUSC_PTC_Pos) 510 #define PAC_STATUSC_CCL_Pos 23 /**< \brief (PAC_STATUSC) CCL APB Protect Enable */ 511 #define PAC_STATUSC_CCL (_U_(0x1) << PAC_STATUSC_CCL_Pos) 512 #define PAC_STATUSC_MASK _U_(0x00FFFFFF) /**< \brief (PAC_STATUSC) MASK Register */ 513 514 /** \brief PAC hardware registers */ 515 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 516 typedef struct { 517 __IO PAC_WRCTRL_Type WRCTRL; /**< \brief Offset: 0x00 (R/W 32) Write control */ 518 __IO PAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 8) Event control */ 519 RoReg8 Reserved1[0x3]; 520 __IO PAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt enable clear */ 521 __IO PAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt enable set */ 522 RoReg8 Reserved2[0x6]; 523 __IO PAC_INTFLAGAHB_Type INTFLAGAHB; /**< \brief Offset: 0x10 (R/W 32) Bridge interrupt flag status */ 524 __IO PAC_INTFLAGA_Type INTFLAGA; /**< \brief Offset: 0x14 (R/W 32) Peripheral interrupt flag status - Bridge A */ 525 __IO PAC_INTFLAGB_Type INTFLAGB; /**< \brief Offset: 0x18 (R/W 32) Peripheral interrupt flag status - Bridge B */ 526 __IO PAC_INTFLAGC_Type INTFLAGC; /**< \brief Offset: 0x1C (R/W 32) Peripheral interrupt flag status - Bridge C */ 527 RoReg8 Reserved3[0x14]; 528 __I PAC_STATUSA_Type STATUSA; /**< \brief Offset: 0x34 (R/ 32) Peripheral write protection status - Bridge A */ 529 __I PAC_STATUSB_Type STATUSB; /**< \brief Offset: 0x38 (R/ 32) Peripheral write protection status - Bridge B */ 530 __I PAC_STATUSC_Type STATUSC; /**< \brief Offset: 0x3C (R/ 32) Peripheral write protection status - Bridge C */ 531 } Pac; 532 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 533 534 /*@}*/ 535 536 #endif /* _SAMC21_PAC_COMPONENT_ */ 537
