1 /** 2 * \file 3 * 4 * \brief Component description for NVMCTRL 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMC21_NVMCTRL_COMPONENT_ 31 #define _SAMC21_NVMCTRL_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR NVMCTRL */ 35 /* ========================================================================== */ 36 /** \addtogroup SAMC21_NVMCTRL Non-Volatile Memory Controller */ 37 /*@{*/ 38 39 #define NVMCTRL_U2207 40 #define REV_NVMCTRL 0x401 41 42 /* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint16_t CMD:7; /*!< bit: 0.. 6 Command */ 47 uint16_t :1; /*!< bit: 7 Reserved */ 48 uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */ 49 } bit; /*!< Structure used for bit access */ 50 uint16_t reg; /*!< Type used for register access */ 51 } NVMCTRL_CTRLA_Type; 52 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 53 54 #define NVMCTRL_CTRLA_OFFSET 0x00 /**< \brief (NVMCTRL_CTRLA offset) Control A */ 55 #define NVMCTRL_CTRLA_RESETVALUE _U_(0x0000) /**< \brief (NVMCTRL_CTRLA reset_value) Control A */ 56 57 #define NVMCTRL_CTRLA_CMD_Pos 0 /**< \brief (NVMCTRL_CTRLA) Command */ 58 #define NVMCTRL_CTRLA_CMD_Msk (_U_(0x7F) << NVMCTRL_CTRLA_CMD_Pos) 59 #define NVMCTRL_CTRLA_CMD(value) (NVMCTRL_CTRLA_CMD_Msk & ((value) << NVMCTRL_CTRLA_CMD_Pos)) 60 #define NVMCTRL_CTRLA_CMD_ER_Val _U_(0x2) /**< \brief (NVMCTRL_CTRLA) Erase Row - Erases the row addressed by the ADDR register. */ 61 #define NVMCTRL_CTRLA_CMD_WP_Val _U_(0x4) /**< \brief (NVMCTRL_CTRLA) Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */ 62 #define NVMCTRL_CTRLA_CMD_EAR_Val _U_(0x5) /**< \brief (NVMCTRL_CTRLA) Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */ 63 #define NVMCTRL_CTRLA_CMD_WAP_Val _U_(0x6) /**< \brief (NVMCTRL_CTRLA) Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */ 64 #define NVMCTRL_CTRLA_CMD_SF_Val _U_(0xA) /**< \brief (NVMCTRL_CTRLA) Security Flow Command */ 65 #define NVMCTRL_CTRLA_CMD_WL_Val _U_(0xF) /**< \brief (NVMCTRL_CTRLA) Write lockbits */ 66 #define NVMCTRL_CTRLA_CMD_RWWEEER_Val _U_(0x1A) /**< \brief (NVMCTRL_CTRLA) RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. */ 67 #define NVMCTRL_CTRLA_CMD_RWWEEWP_Val _U_(0x1C) /**< \brief (NVMCTRL_CTRLA) RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */ 68 #define NVMCTRL_CTRLA_CMD_LR_Val _U_(0x40) /**< \brief (NVMCTRL_CTRLA) Lock Region - Locks the region containing the address location in the ADDR register. */ 69 #define NVMCTRL_CTRLA_CMD_UR_Val _U_(0x41) /**< \brief (NVMCTRL_CTRLA) Unlock Region - Unlocks the region containing the address location in the ADDR register. */ 70 #define NVMCTRL_CTRLA_CMD_SPRM_Val _U_(0x42) /**< \brief (NVMCTRL_CTRLA) Sets the power reduction mode. */ 71 #define NVMCTRL_CTRLA_CMD_CPRM_Val _U_(0x43) /**< \brief (NVMCTRL_CTRLA) Clears the power reduction mode. */ 72 #define NVMCTRL_CTRLA_CMD_PBC_Val _U_(0x44) /**< \brief (NVMCTRL_CTRLA) Page Buffer Clear - Clears the page buffer. */ 73 #define NVMCTRL_CTRLA_CMD_SSB_Val _U_(0x45) /**< \brief (NVMCTRL_CTRLA) Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. */ 74 #define NVMCTRL_CTRLA_CMD_INVALL_Val _U_(0x46) /**< \brief (NVMCTRL_CTRLA) Invalidate all cache lines. */ 75 #define NVMCTRL_CTRLA_CMD_ER (NVMCTRL_CTRLA_CMD_ER_Val << NVMCTRL_CTRLA_CMD_Pos) 76 #define NVMCTRL_CTRLA_CMD_WP (NVMCTRL_CTRLA_CMD_WP_Val << NVMCTRL_CTRLA_CMD_Pos) 77 #define NVMCTRL_CTRLA_CMD_EAR (NVMCTRL_CTRLA_CMD_EAR_Val << NVMCTRL_CTRLA_CMD_Pos) 78 #define NVMCTRL_CTRLA_CMD_WAP (NVMCTRL_CTRLA_CMD_WAP_Val << NVMCTRL_CTRLA_CMD_Pos) 79 #define NVMCTRL_CTRLA_CMD_SF (NVMCTRL_CTRLA_CMD_SF_Val << NVMCTRL_CTRLA_CMD_Pos) 80 #define NVMCTRL_CTRLA_CMD_WL (NVMCTRL_CTRLA_CMD_WL_Val << NVMCTRL_CTRLA_CMD_Pos) 81 #define NVMCTRL_CTRLA_CMD_RWWEEER (NVMCTRL_CTRLA_CMD_RWWEEER_Val << NVMCTRL_CTRLA_CMD_Pos) 82 #define NVMCTRL_CTRLA_CMD_RWWEEWP (NVMCTRL_CTRLA_CMD_RWWEEWP_Val << NVMCTRL_CTRLA_CMD_Pos) 83 #define NVMCTRL_CTRLA_CMD_LR (NVMCTRL_CTRLA_CMD_LR_Val << NVMCTRL_CTRLA_CMD_Pos) 84 #define NVMCTRL_CTRLA_CMD_UR (NVMCTRL_CTRLA_CMD_UR_Val << NVMCTRL_CTRLA_CMD_Pos) 85 #define NVMCTRL_CTRLA_CMD_SPRM (NVMCTRL_CTRLA_CMD_SPRM_Val << NVMCTRL_CTRLA_CMD_Pos) 86 #define NVMCTRL_CTRLA_CMD_CPRM (NVMCTRL_CTRLA_CMD_CPRM_Val << NVMCTRL_CTRLA_CMD_Pos) 87 #define NVMCTRL_CTRLA_CMD_PBC (NVMCTRL_CTRLA_CMD_PBC_Val << NVMCTRL_CTRLA_CMD_Pos) 88 #define NVMCTRL_CTRLA_CMD_SSB (NVMCTRL_CTRLA_CMD_SSB_Val << NVMCTRL_CTRLA_CMD_Pos) 89 #define NVMCTRL_CTRLA_CMD_INVALL (NVMCTRL_CTRLA_CMD_INVALL_Val << NVMCTRL_CTRLA_CMD_Pos) 90 #define NVMCTRL_CTRLA_CMDEX_Pos 8 /**< \brief (NVMCTRL_CTRLA) Command Execution */ 91 #define NVMCTRL_CTRLA_CMDEX_Msk (_U_(0xFF) << NVMCTRL_CTRLA_CMDEX_Pos) 92 #define NVMCTRL_CTRLA_CMDEX(value) (NVMCTRL_CTRLA_CMDEX_Msk & ((value) << NVMCTRL_CTRLA_CMDEX_Pos)) 93 #define NVMCTRL_CTRLA_CMDEX_KEY_Val _U_(0xA5) /**< \brief (NVMCTRL_CTRLA) Execution Key */ 94 #define NVMCTRL_CTRLA_CMDEX_KEY (NVMCTRL_CTRLA_CMDEX_KEY_Val << NVMCTRL_CTRLA_CMDEX_Pos) 95 #define NVMCTRL_CTRLA_MASK _U_(0xFF7F) /**< \brief (NVMCTRL_CTRLA) MASK Register */ 96 97 /* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) (R/W 32) Control B -------- */ 98 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 99 typedef union { 100 struct { 101 uint32_t :1; /*!< bit: 0 Reserved */ 102 uint32_t RWS:4; /*!< bit: 1.. 4 NVM Read Wait States */ 103 uint32_t :2; /*!< bit: 5.. 6 Reserved */ 104 uint32_t MANW:1; /*!< bit: 7 Manual Write */ 105 uint32_t SLEEPPRM:2; /*!< bit: 8.. 9 Power Reduction Mode during Sleep */ 106 uint32_t :6; /*!< bit: 10..15 Reserved */ 107 uint32_t READMODE:2; /*!< bit: 16..17 NVMCTRL Read Mode */ 108 uint32_t CACHEDIS:2; /*!< bit: 18..19 Cache Disable */ 109 uint32_t :12; /*!< bit: 20..31 Reserved */ 110 } bit; /*!< Structure used for bit access */ 111 uint32_t reg; /*!< Type used for register access */ 112 } NVMCTRL_CTRLB_Type; 113 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 114 115 #define NVMCTRL_CTRLB_OFFSET 0x04 /**< \brief (NVMCTRL_CTRLB offset) Control B */ 116 #define NVMCTRL_CTRLB_RESETVALUE _U_(0x00000080) /**< \brief (NVMCTRL_CTRLB reset_value) Control B */ 117 118 #define NVMCTRL_CTRLB_RWS_Pos 1 /**< \brief (NVMCTRL_CTRLB) NVM Read Wait States */ 119 #define NVMCTRL_CTRLB_RWS_Msk (_U_(0xF) << NVMCTRL_CTRLB_RWS_Pos) 120 #define NVMCTRL_CTRLB_RWS(value) (NVMCTRL_CTRLB_RWS_Msk & ((value) << NVMCTRL_CTRLB_RWS_Pos)) 121 #define NVMCTRL_CTRLB_RWS_SINGLE_Val _U_(0x0) /**< \brief (NVMCTRL_CTRLB) Single Auto Wait State */ 122 #define NVMCTRL_CTRLB_RWS_HALF_Val _U_(0x1) /**< \brief (NVMCTRL_CTRLB) Half Auto Wait State */ 123 #define NVMCTRL_CTRLB_RWS_DUAL_Val _U_(0x2) /**< \brief (NVMCTRL_CTRLB) Dual Auto Wait State */ 124 #define NVMCTRL_CTRLB_RWS_SINGLE (NVMCTRL_CTRLB_RWS_SINGLE_Val << NVMCTRL_CTRLB_RWS_Pos) 125 #define NVMCTRL_CTRLB_RWS_HALF (NVMCTRL_CTRLB_RWS_HALF_Val << NVMCTRL_CTRLB_RWS_Pos) 126 #define NVMCTRL_CTRLB_RWS_DUAL (NVMCTRL_CTRLB_RWS_DUAL_Val << NVMCTRL_CTRLB_RWS_Pos) 127 #define NVMCTRL_CTRLB_MANW_Pos 7 /**< \brief (NVMCTRL_CTRLB) Manual Write */ 128 #define NVMCTRL_CTRLB_MANW (_U_(0x1) << NVMCTRL_CTRLB_MANW_Pos) 129 #define NVMCTRL_CTRLB_SLEEPPRM_Pos 8 /**< \brief (NVMCTRL_CTRLB) Power Reduction Mode during Sleep */ 130 #define NVMCTRL_CTRLB_SLEEPPRM_Msk (_U_(0x3) << NVMCTRL_CTRLB_SLEEPPRM_Pos) 131 #define NVMCTRL_CTRLB_SLEEPPRM(value) (NVMCTRL_CTRLB_SLEEPPRM_Msk & ((value) << NVMCTRL_CTRLB_SLEEPPRM_Pos)) 132 #define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val _U_(0x0) /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. */ 133 #define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val _U_(0x1) /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. */ 134 #define NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val _U_(0x3) /**< \brief (NVMCTRL_CTRLB) Auto power reduction disabled. */ 135 #define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS (NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos) 136 #define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT (NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos) 137 #define NVMCTRL_CTRLB_SLEEPPRM_DISABLED (NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos) 138 #define NVMCTRL_CTRLB_READMODE_Pos 16 /**< \brief (NVMCTRL_CTRLB) NVMCTRL Read Mode */ 139 #define NVMCTRL_CTRLB_READMODE_Msk (_U_(0x3) << NVMCTRL_CTRLB_READMODE_Pos) 140 #define NVMCTRL_CTRLB_READMODE(value) (NVMCTRL_CTRLB_READMODE_Msk & ((value) << NVMCTRL_CTRLB_READMODE_Pos)) 141 #define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val _U_(0x0) /**< \brief (NVMCTRL_CTRLB) The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. */ 142 #define NVMCTRL_CTRLB_READMODE_LOW_POWER_Val _U_(0x1) /**< \brief (NVMCTRL_CTRLB) Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. */ 143 #define NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val _U_(0x2) /**< \brief (NVMCTRL_CTRLB) The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. */ 144 #define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY (NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val << NVMCTRL_CTRLB_READMODE_Pos) 145 #define NVMCTRL_CTRLB_READMODE_LOW_POWER (NVMCTRL_CTRLB_READMODE_LOW_POWER_Val << NVMCTRL_CTRLB_READMODE_Pos) 146 #define NVMCTRL_CTRLB_READMODE_DETERMINISTIC (NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val << NVMCTRL_CTRLB_READMODE_Pos) 147 #define NVMCTRL_CTRLB_CACHEDIS_Pos 18 /**< \brief (NVMCTRL_CTRLB) Cache Disable */ 148 #define NVMCTRL_CTRLB_CACHEDIS_Msk (_U_(0x3) << NVMCTRL_CTRLB_CACHEDIS_Pos) 149 #define NVMCTRL_CTRLB_CACHEDIS(value) (NVMCTRL_CTRLB_CACHEDIS_Msk & ((value) << NVMCTRL_CTRLB_CACHEDIS_Pos)) 150 #define NVMCTRL_CTRLB_MASK _U_(0x000F039E) /**< \brief (NVMCTRL_CTRLB) MASK Register */ 151 152 /* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/W 32) NVM Parameter -------- */ 153 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 154 typedef union { 155 struct { 156 uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */ 157 uint32_t PSZ:3; /*!< bit: 16..18 Page Size */ 158 uint32_t :1; /*!< bit: 19 Reserved */ 159 uint32_t RWWEEP:12; /*!< bit: 20..31 RWW EEPROM Pages */ 160 } bit; /*!< Structure used for bit access */ 161 uint32_t reg; /*!< Type used for register access */ 162 } NVMCTRL_PARAM_Type; 163 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 164 165 #define NVMCTRL_PARAM_OFFSET 0x08 /**< \brief (NVMCTRL_PARAM offset) NVM Parameter */ 166 #define NVMCTRL_PARAM_RESETVALUE _U_(0x00000000) /**< \brief (NVMCTRL_PARAM reset_value) NVM Parameter */ 167 168 #define NVMCTRL_PARAM_NVMP_Pos 0 /**< \brief (NVMCTRL_PARAM) NVM Pages */ 169 #define NVMCTRL_PARAM_NVMP_Msk (_U_(0xFFFF) << NVMCTRL_PARAM_NVMP_Pos) 170 #define NVMCTRL_PARAM_NVMP(value) (NVMCTRL_PARAM_NVMP_Msk & ((value) << NVMCTRL_PARAM_NVMP_Pos)) 171 #define NVMCTRL_PARAM_PSZ_Pos 16 /**< \brief (NVMCTRL_PARAM) Page Size */ 172 #define NVMCTRL_PARAM_PSZ_Msk (_U_(0x7) << NVMCTRL_PARAM_PSZ_Pos) 173 #define NVMCTRL_PARAM_PSZ(value) (NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos)) 174 #define NVMCTRL_PARAM_PSZ_8_Val _U_(0x0) /**< \brief (NVMCTRL_PARAM) 8 bytes */ 175 #define NVMCTRL_PARAM_PSZ_16_Val _U_(0x1) /**< \brief (NVMCTRL_PARAM) 16 bytes */ 176 #define NVMCTRL_PARAM_PSZ_32_Val _U_(0x2) /**< \brief (NVMCTRL_PARAM) 32 bytes */ 177 #define NVMCTRL_PARAM_PSZ_64_Val _U_(0x3) /**< \brief (NVMCTRL_PARAM) 64 bytes */ 178 #define NVMCTRL_PARAM_PSZ_128_Val _U_(0x4) /**< \brief (NVMCTRL_PARAM) 128 bytes */ 179 #define NVMCTRL_PARAM_PSZ_256_Val _U_(0x5) /**< \brief (NVMCTRL_PARAM) 256 bytes */ 180 #define NVMCTRL_PARAM_PSZ_512_Val _U_(0x6) /**< \brief (NVMCTRL_PARAM) 512 bytes */ 181 #define NVMCTRL_PARAM_PSZ_1024_Val _U_(0x7) /**< \brief (NVMCTRL_PARAM) 1024 bytes */ 182 #define NVMCTRL_PARAM_PSZ_8 (NVMCTRL_PARAM_PSZ_8_Val << NVMCTRL_PARAM_PSZ_Pos) 183 #define NVMCTRL_PARAM_PSZ_16 (NVMCTRL_PARAM_PSZ_16_Val << NVMCTRL_PARAM_PSZ_Pos) 184 #define NVMCTRL_PARAM_PSZ_32 (NVMCTRL_PARAM_PSZ_32_Val << NVMCTRL_PARAM_PSZ_Pos) 185 #define NVMCTRL_PARAM_PSZ_64 (NVMCTRL_PARAM_PSZ_64_Val << NVMCTRL_PARAM_PSZ_Pos) 186 #define NVMCTRL_PARAM_PSZ_128 (NVMCTRL_PARAM_PSZ_128_Val << NVMCTRL_PARAM_PSZ_Pos) 187 #define NVMCTRL_PARAM_PSZ_256 (NVMCTRL_PARAM_PSZ_256_Val << NVMCTRL_PARAM_PSZ_Pos) 188 #define NVMCTRL_PARAM_PSZ_512 (NVMCTRL_PARAM_PSZ_512_Val << NVMCTRL_PARAM_PSZ_Pos) 189 #define NVMCTRL_PARAM_PSZ_1024 (NVMCTRL_PARAM_PSZ_1024_Val << NVMCTRL_PARAM_PSZ_Pos) 190 #define NVMCTRL_PARAM_RWWEEP_Pos 20 /**< \brief (NVMCTRL_PARAM) RWW EEPROM Pages */ 191 #define NVMCTRL_PARAM_RWWEEP_Msk (_U_(0xFFF) << NVMCTRL_PARAM_RWWEEP_Pos) 192 #define NVMCTRL_PARAM_RWWEEP(value) (NVMCTRL_PARAM_RWWEEP_Msk & ((value) << NVMCTRL_PARAM_RWWEEP_Pos)) 193 #define NVMCTRL_PARAM_MASK _U_(0xFFF7FFFF) /**< \brief (NVMCTRL_PARAM) MASK Register */ 194 195 /* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */ 196 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 197 typedef union { 198 struct { 199 uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */ 200 uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */ 201 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 202 } bit; /*!< Structure used for bit access */ 203 uint8_t reg; /*!< Type used for register access */ 204 } NVMCTRL_INTENCLR_Type; 205 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 206 207 #define NVMCTRL_INTENCLR_OFFSET 0x0C /**< \brief (NVMCTRL_INTENCLR offset) Interrupt Enable Clear */ 208 #define NVMCTRL_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (NVMCTRL_INTENCLR reset_value) Interrupt Enable Clear */ 209 210 #define NVMCTRL_INTENCLR_READY_Pos 0 /**< \brief (NVMCTRL_INTENCLR) NVM Ready Interrupt Enable */ 211 #define NVMCTRL_INTENCLR_READY (_U_(0x1) << NVMCTRL_INTENCLR_READY_Pos) 212 #define NVMCTRL_INTENCLR_ERROR_Pos 1 /**< \brief (NVMCTRL_INTENCLR) Error Interrupt Enable */ 213 #define NVMCTRL_INTENCLR_ERROR (_U_(0x1) << NVMCTRL_INTENCLR_ERROR_Pos) 214 #define NVMCTRL_INTENCLR_MASK _U_(0x03) /**< \brief (NVMCTRL_INTENCLR) MASK Register */ 215 216 /* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x10) (R/W 8) Interrupt Enable Set -------- */ 217 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 218 typedef union { 219 struct { 220 uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */ 221 uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */ 222 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 223 } bit; /*!< Structure used for bit access */ 224 uint8_t reg; /*!< Type used for register access */ 225 } NVMCTRL_INTENSET_Type; 226 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 227 228 #define NVMCTRL_INTENSET_OFFSET 0x10 /**< \brief (NVMCTRL_INTENSET offset) Interrupt Enable Set */ 229 #define NVMCTRL_INTENSET_RESETVALUE _U_(0x00) /**< \brief (NVMCTRL_INTENSET reset_value) Interrupt Enable Set */ 230 231 #define NVMCTRL_INTENSET_READY_Pos 0 /**< \brief (NVMCTRL_INTENSET) NVM Ready Interrupt Enable */ 232 #define NVMCTRL_INTENSET_READY (_U_(0x1) << NVMCTRL_INTENSET_READY_Pos) 233 #define NVMCTRL_INTENSET_ERROR_Pos 1 /**< \brief (NVMCTRL_INTENSET) Error Interrupt Enable */ 234 #define NVMCTRL_INTENSET_ERROR (_U_(0x1) << NVMCTRL_INTENSET_ERROR_Pos) 235 #define NVMCTRL_INTENSET_MASK _U_(0x03) /**< \brief (NVMCTRL_INTENSET) MASK Register */ 236 237 /* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x14) (R/W 8) Interrupt Flag Status and Clear -------- */ 238 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 239 typedef union { // __I to avoid read-modify-write on write-to-clear register 240 struct { 241 __I uint8_t READY:1; /*!< bit: 0 NVM Ready */ 242 __I uint8_t ERROR:1; /*!< bit: 1 Error */ 243 __I uint8_t :6; /*!< bit: 2.. 7 Reserved */ 244 } bit; /*!< Structure used for bit access */ 245 uint8_t reg; /*!< Type used for register access */ 246 } NVMCTRL_INTFLAG_Type; 247 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 248 249 #define NVMCTRL_INTFLAG_OFFSET 0x14 /**< \brief (NVMCTRL_INTFLAG offset) Interrupt Flag Status and Clear */ 250 #define NVMCTRL_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (NVMCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */ 251 252 #define NVMCTRL_INTFLAG_READY_Pos 0 /**< \brief (NVMCTRL_INTFLAG) NVM Ready */ 253 #define NVMCTRL_INTFLAG_READY (_U_(0x1) << NVMCTRL_INTFLAG_READY_Pos) 254 #define NVMCTRL_INTFLAG_ERROR_Pos 1 /**< \brief (NVMCTRL_INTFLAG) Error */ 255 #define NVMCTRL_INTFLAG_ERROR (_U_(0x1) << NVMCTRL_INTFLAG_ERROR_Pos) 256 #define NVMCTRL_INTFLAG_MASK _U_(0x03) /**< \brief (NVMCTRL_INTFLAG) MASK Register */ 257 258 /* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x18) (R/W 16) Status -------- */ 259 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 260 typedef union { 261 struct { 262 uint16_t PRM:1; /*!< bit: 0 Power Reduction Mode */ 263 uint16_t LOAD:1; /*!< bit: 1 NVM Page Buffer Active Loading */ 264 uint16_t PROGE:1; /*!< bit: 2 Programming Error Status */ 265 uint16_t LOCKE:1; /*!< bit: 3 Lock Error Status */ 266 uint16_t NVME:1; /*!< bit: 4 NVM Error */ 267 uint16_t :3; /*!< bit: 5.. 7 Reserved */ 268 uint16_t SB:1; /*!< bit: 8 Security Bit Status */ 269 uint16_t :7; /*!< bit: 9..15 Reserved */ 270 } bit; /*!< Structure used for bit access */ 271 uint16_t reg; /*!< Type used for register access */ 272 } NVMCTRL_STATUS_Type; 273 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 274 275 #define NVMCTRL_STATUS_OFFSET 0x18 /**< \brief (NVMCTRL_STATUS offset) Status */ 276 #define NVMCTRL_STATUS_RESETVALUE _U_(0x0000) /**< \brief (NVMCTRL_STATUS reset_value) Status */ 277 278 #define NVMCTRL_STATUS_PRM_Pos 0 /**< \brief (NVMCTRL_STATUS) Power Reduction Mode */ 279 #define NVMCTRL_STATUS_PRM (_U_(0x1) << NVMCTRL_STATUS_PRM_Pos) 280 #define NVMCTRL_STATUS_LOAD_Pos 1 /**< \brief (NVMCTRL_STATUS) NVM Page Buffer Active Loading */ 281 #define NVMCTRL_STATUS_LOAD (_U_(0x1) << NVMCTRL_STATUS_LOAD_Pos) 282 #define NVMCTRL_STATUS_PROGE_Pos 2 /**< \brief (NVMCTRL_STATUS) Programming Error Status */ 283 #define NVMCTRL_STATUS_PROGE (_U_(0x1) << NVMCTRL_STATUS_PROGE_Pos) 284 #define NVMCTRL_STATUS_LOCKE_Pos 3 /**< \brief (NVMCTRL_STATUS) Lock Error Status */ 285 #define NVMCTRL_STATUS_LOCKE (_U_(0x1) << NVMCTRL_STATUS_LOCKE_Pos) 286 #define NVMCTRL_STATUS_NVME_Pos 4 /**< \brief (NVMCTRL_STATUS) NVM Error */ 287 #define NVMCTRL_STATUS_NVME (_U_(0x1) << NVMCTRL_STATUS_NVME_Pos) 288 #define NVMCTRL_STATUS_SB_Pos 8 /**< \brief (NVMCTRL_STATUS) Security Bit Status */ 289 #define NVMCTRL_STATUS_SB (_U_(0x1) << NVMCTRL_STATUS_SB_Pos) 290 #define NVMCTRL_STATUS_MASK _U_(0x011F) /**< \brief (NVMCTRL_STATUS) MASK Register */ 291 292 /* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x1C) (R/W 32) Address -------- */ 293 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 294 typedef union { 295 struct { 296 uint32_t ADDR:22; /*!< bit: 0..21 NVM Address */ 297 uint32_t :10; /*!< bit: 22..31 Reserved */ 298 } bit; /*!< Structure used for bit access */ 299 uint32_t reg; /*!< Type used for register access */ 300 } NVMCTRL_ADDR_Type; 301 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 302 303 #define NVMCTRL_ADDR_OFFSET 0x1C /**< \brief (NVMCTRL_ADDR offset) Address */ 304 #define NVMCTRL_ADDR_RESETVALUE _U_(0x00000000) /**< \brief (NVMCTRL_ADDR reset_value) Address */ 305 306 #define NVMCTRL_ADDR_ADDR_Pos 0 /**< \brief (NVMCTRL_ADDR) NVM Address */ 307 #define NVMCTRL_ADDR_ADDR_Msk (_U_(0x3FFFFF) << NVMCTRL_ADDR_ADDR_Pos) 308 #define NVMCTRL_ADDR_ADDR(value) (NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos)) 309 #define NVMCTRL_ADDR_MASK _U_(0x003FFFFF) /**< \brief (NVMCTRL_ADDR) MASK Register */ 310 311 /* -------- NVMCTRL_LOCK : (NVMCTRL Offset: 0x20) (R/W 16) Lock Section -------- */ 312 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 313 typedef union { 314 struct { 315 uint16_t LOCK:16; /*!< bit: 0..15 Region Lock Bits */ 316 } bit; /*!< Structure used for bit access */ 317 uint16_t reg; /*!< Type used for register access */ 318 } NVMCTRL_LOCK_Type; 319 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 320 321 #define NVMCTRL_LOCK_OFFSET 0x20 /**< \brief (NVMCTRL_LOCK offset) Lock Section */ 322 #define NVMCTRL_LOCK_RESETVALUE _U_(0x0000) /**< \brief (NVMCTRL_LOCK reset_value) Lock Section */ 323 324 #define NVMCTRL_LOCK_LOCK_Pos 0 /**< \brief (NVMCTRL_LOCK) Region Lock Bits */ 325 #define NVMCTRL_LOCK_LOCK_Msk (_U_(0xFFFF) << NVMCTRL_LOCK_LOCK_Pos) 326 #define NVMCTRL_LOCK_LOCK(value) (NVMCTRL_LOCK_LOCK_Msk & ((value) << NVMCTRL_LOCK_LOCK_Pos)) 327 #define NVMCTRL_LOCK_MASK _U_(0xFFFF) /**< \brief (NVMCTRL_LOCK) MASK Register */ 328 329 /* -------- NVMCTRL_PBLDATA0 : (NVMCTRL Offset: 0x28) (R/ 32) Page Buffer Load Data 0 -------- */ 330 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 331 typedef union { 332 uint32_t reg; /*!< Type used for register access */ 333 } NVMCTRL_PBLDATA0_Type; 334 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 335 336 #define NVMCTRL_PBLDATA0_OFFSET 0x28 /**< \brief (NVMCTRL_PBLDATA0 offset) Page Buffer Load Data 0 */ 337 #define NVMCTRL_PBLDATA0_RESETVALUE _U_(0x00000000) /**< \brief (NVMCTRL_PBLDATA0 reset_value) Page Buffer Load Data 0 */ 338 #define NVMCTRL_PBLDATA0_MASK _U_(0xFFFFFFFF) /**< \brief (NVMCTRL_PBLDATA0) MASK Register */ 339 340 /* -------- NVMCTRL_PBLDATA1 : (NVMCTRL Offset: 0x2C) (R/ 32) Page Buffer Load Data 1 -------- */ 341 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 342 typedef union { 343 uint32_t reg; /*!< Type used for register access */ 344 } NVMCTRL_PBLDATA1_Type; 345 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 346 347 #define NVMCTRL_PBLDATA1_OFFSET 0x2C /**< \brief (NVMCTRL_PBLDATA1 offset) Page Buffer Load Data 1 */ 348 #define NVMCTRL_PBLDATA1_RESETVALUE _U_(0x00000000) /**< \brief (NVMCTRL_PBLDATA1 reset_value) Page Buffer Load Data 1 */ 349 #define NVMCTRL_PBLDATA1_MASK _U_(0xFFFFFFFF) /**< \brief (NVMCTRL_PBLDATA1) MASK Register */ 350 351 /** \brief NVMCTRL APB hardware registers */ 352 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 353 typedef struct { 354 __IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ 355 RoReg8 Reserved1[0x2]; 356 __IO NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */ 357 __IO NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */ 358 __IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */ 359 RoReg8 Reserved2[0x3]; 360 __IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 8) Interrupt Enable Set */ 361 RoReg8 Reserved3[0x3]; 362 __IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 8) Interrupt Flag Status and Clear */ 363 RoReg8 Reserved4[0x3]; 364 __IO NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x18 (R/W 16) Status */ 365 RoReg8 Reserved5[0x2]; 366 __IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x1C (R/W 32) Address */ 367 __IO NVMCTRL_LOCK_Type LOCK; /**< \brief Offset: 0x20 (R/W 16) Lock Section */ 368 RoReg8 Reserved6[0x6]; 369 __I NVMCTRL_PBLDATA0_Type PBLDATA0; /**< \brief Offset: 0x28 (R/ 32) Page Buffer Load Data 0 */ 370 __I NVMCTRL_PBLDATA1_Type PBLDATA1; /**< \brief Offset: 0x2C (R/ 32) Page Buffer Load Data 1 */ 371 } Nvmctrl; 372 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 373 374 #ifdef __GNUC__ 375 #define SECTION_NVMCTRL_CAL __attribute__ ((section(".flash"))) 376 #define SECTION_NVMCTRL_LOCKBIT __attribute__ ((section(".flash"))) 377 #define SECTION_NVMCTRL_OTP1 __attribute__ ((section(".flash"))) 378 #define SECTION_NVMCTRL_OTP2 __attribute__ ((section(".flash"))) 379 #define SECTION_NVMCTRL_OTP3 __attribute__ ((section(".flash"))) 380 #define SECTION_NVMCTRL_OTP4 __attribute__ ((section(".flash"))) 381 #define SECTION_NVMCTRL_OTP5 __attribute__ ((section(".flash"))) 382 #define SECTION_NVMCTRL_TEMP_LOG __attribute__ ((section(".flash"))) 383 #define SECTION_NVMCTRL_USER __attribute__ ((section(".flash"))) 384 #elif defined(__ICCARM__) 385 #define SECTION_NVMCTRL_CAL @".flash" 386 #define SECTION_NVMCTRL_LOCKBIT @".flash" 387 #define SECTION_NVMCTRL_OTP1 @".flash" 388 #define SECTION_NVMCTRL_OTP2 @".flash" 389 #define SECTION_NVMCTRL_OTP3 @".flash" 390 #define SECTION_NVMCTRL_OTP4 @".flash" 391 #define SECTION_NVMCTRL_OTP5 @".flash" 392 #define SECTION_NVMCTRL_TEMP_LOG @".flash" 393 #define SECTION_NVMCTRL_USER @".flash" 394 #endif 395 396 /*@}*/ 397 398 /* ************************************************************************** */ 399 /** SOFTWARE PERIPHERAL API DEFINITION FOR NON-VOLATILE FUSES */ 400 /* ************************************************************************** */ 401 /** \addtogroup fuses_api Peripheral Software API */ 402 /*@{*/ 403 404 405 #define ADC0_FUSES_BIASCOMP_ADDR NVMCTRL_OTP5 406 #define ADC0_FUSES_BIASCOMP_Pos 3 /**< \brief (NVMCTRL_OTP5) ADC Comparator Scaling */ 407 #define ADC0_FUSES_BIASCOMP_Msk (_U_(0x7) << ADC0_FUSES_BIASCOMP_Pos) 408 #define ADC0_FUSES_BIASCOMP(value) (ADC0_FUSES_BIASCOMP_Msk & ((value) << ADC0_FUSES_BIASCOMP_Pos)) 409 410 #define ADC0_FUSES_BIASREFBUF_ADDR NVMCTRL_OTP5 411 #define ADC0_FUSES_BIASREFBUF_Pos 0 /**< \brief (NVMCTRL_OTP5) ADC Bias Reference Buffer Scaling */ 412 #define ADC0_FUSES_BIASREFBUF_Msk (_U_(0x7) << ADC0_FUSES_BIASREFBUF_Pos) 413 #define ADC0_FUSES_BIASREFBUF(value) (ADC0_FUSES_BIASREFBUF_Msk & ((value) << ADC0_FUSES_BIASREFBUF_Pos)) 414 415 #define ADC1_FUSES_BIASCOMP_ADDR NVMCTRL_OTP5 416 #define ADC1_FUSES_BIASCOMP_Pos 9 /**< \brief (NVMCTRL_OTP5) ADC Comparator Scaling */ 417 #define ADC1_FUSES_BIASCOMP_Msk (_U_(0x7) << ADC1_FUSES_BIASCOMP_Pos) 418 #define ADC1_FUSES_BIASCOMP(value) (ADC1_FUSES_BIASCOMP_Msk & ((value) << ADC1_FUSES_BIASCOMP_Pos)) 419 420 #define ADC1_FUSES_BIASREFBUF_ADDR NVMCTRL_OTP5 421 #define ADC1_FUSES_BIASREFBUF_Pos 6 /**< \brief (NVMCTRL_OTP5) ADC Bias Reference Buffer Scaling */ 422 #define ADC1_FUSES_BIASREFBUF_Msk (_U_(0x7) << ADC1_FUSES_BIASREFBUF_Pos) 423 #define ADC1_FUSES_BIASREFBUF(value) (ADC1_FUSES_BIASREFBUF_Msk & ((value) << ADC1_FUSES_BIASREFBUF_Pos)) 424 425 #define FUSES_BODCOREUSERLEVEL_ADDR NVMCTRL_USER 426 #define FUSES_BODCOREUSERLEVEL_Pos 17 /**< \brief (NVMCTRL_USER) BODCORE User Level */ 427 #define FUSES_BODCOREUSERLEVEL_Msk (_U_(0x3F) << FUSES_BODCOREUSERLEVEL_Pos) 428 #define FUSES_BODCOREUSERLEVEL(value) (FUSES_BODCOREUSERLEVEL_Msk & ((value) << FUSES_BODCOREUSERLEVEL_Pos)) 429 430 #define FUSES_BODCORE_ACTION_ADDR NVMCTRL_USER 431 #define FUSES_BODCORE_ACTION_Pos 24 /**< \brief (NVMCTRL_USER) BODCORE Action */ 432 #define FUSES_BODCORE_ACTION_Msk (_U_(0x3) << FUSES_BODCORE_ACTION_Pos) 433 #define FUSES_BODCORE_ACTION(value) (FUSES_BODCORE_ACTION_Msk & ((value) << FUSES_BODCORE_ACTION_Pos)) 434 435 #define FUSES_BODCORE_DIS_ADDR NVMCTRL_USER 436 #define FUSES_BODCORE_DIS_Pos 23 /**< \brief (NVMCTRL_USER) BODCORE Disable */ 437 #define FUSES_BODCORE_DIS_Msk (_U_(0x1) << FUSES_BODCORE_DIS_Pos) 438 439 #define FUSES_BODCORE_HYST_ADDR (NVMCTRL_USER + 4) 440 #define FUSES_BODCORE_HYST_Pos 10 /**< \brief (NVMCTRL_USER) BODCORE Hysterisis */ 441 #define FUSES_BODCORE_HYST_Msk (_U_(0x1) << FUSES_BODCORE_HYST_Pos) 442 443 #define FUSES_BODVDDUSERLEVEL_ADDR NVMCTRL_USER 444 #define FUSES_BODVDDUSERLEVEL_Pos 8 /**< \brief (NVMCTRL_USER) BODVDD User Level */ 445 #define FUSES_BODVDDUSERLEVEL_Msk (_U_(0x3F) << FUSES_BODVDDUSERLEVEL_Pos) 446 #define FUSES_BODVDDUSERLEVEL(value) (FUSES_BODVDDUSERLEVEL_Msk & ((value) << FUSES_BODVDDUSERLEVEL_Pos)) 447 448 #define FUSES_BODVDD_ACTION_ADDR NVMCTRL_USER 449 #define FUSES_BODVDD_ACTION_Pos 15 /**< \brief (NVMCTRL_USER) BODVDD Action */ 450 #define FUSES_BODVDD_ACTION_Msk (_U_(0x3) << FUSES_BODVDD_ACTION_Pos) 451 #define FUSES_BODVDD_ACTION(value) (FUSES_BODVDD_ACTION_Msk & ((value) << FUSES_BODVDD_ACTION_Pos)) 452 453 #define FUSES_BODVDD_DIS_ADDR NVMCTRL_USER 454 #define FUSES_BODVDD_DIS_Pos 14 /**< \brief (NVMCTRL_USER) BODVDD Disable */ 455 #define FUSES_BODVDD_DIS_Msk (_U_(0x1) << FUSES_BODVDD_DIS_Pos) 456 457 #define FUSES_BODVDD_HYST_ADDR (NVMCTRL_USER + 4) 458 #define FUSES_BODVDD_HYST_Pos 9 /**< \brief (NVMCTRL_USER) BODVDD Hysterisis */ 459 #define FUSES_BODVDD_HYST_Msk (_U_(0x1) << FUSES_BODVDD_HYST_Pos) 460 461 #define NVMCTRL_FUSES_BOOTPROT_ADDR NVMCTRL_USER 462 #define NVMCTRL_FUSES_BOOTPROT_Pos 0 /**< \brief (NVMCTRL_USER) Bootloader Size */ 463 #define NVMCTRL_FUSES_BOOTPROT_Msk (_U_(0x7) << NVMCTRL_FUSES_BOOTPROT_Pos) 464 #define NVMCTRL_FUSES_BOOTPROT(value) (NVMCTRL_FUSES_BOOTPROT_Msk & ((value) << NVMCTRL_FUSES_BOOTPROT_Pos)) 465 466 #define NVMCTRL_FUSES_EEPROM_SIZE_ADDR NVMCTRL_USER 467 #define NVMCTRL_FUSES_EEPROM_SIZE_Pos 4 /**< \brief (NVMCTRL_USER) EEPROM Size */ 468 #define NVMCTRL_FUSES_EEPROM_SIZE_Msk (_U_(0x7) << NVMCTRL_FUSES_EEPROM_SIZE_Pos) 469 #define NVMCTRL_FUSES_EEPROM_SIZE(value) (NVMCTRL_FUSES_EEPROM_SIZE_Msk & ((value) << NVMCTRL_FUSES_EEPROM_SIZE_Pos)) 470 471 #define NVMCTRL_FUSES_REGION_LOCKS_ADDR (NVMCTRL_USER + 4) 472 #define NVMCTRL_FUSES_REGION_LOCKS_Pos 16 /**< \brief (NVMCTRL_USER) NVM Region Locks */ 473 #define NVMCTRL_FUSES_REGION_LOCKS_Msk (_U_(0xFFFF) << NVMCTRL_FUSES_REGION_LOCKS_Pos) 474 #define NVMCTRL_FUSES_REGION_LOCKS(value) (NVMCTRL_FUSES_REGION_LOCKS_Msk & ((value) << NVMCTRL_FUSES_REGION_LOCKS_Pos)) 475 476 #define TSENS_FUSES_FCAL_ADDR NVMCTRL_TEMP_LOG 477 #define TSENS_FUSES_FCAL_Pos 6 /**< \brief (NVMCTRL_TEMP_LOG) Frequency Calibration */ 478 #define TSENS_FUSES_FCAL_Msk (_U_(0x3F) << TSENS_FUSES_FCAL_Pos) 479 #define TSENS_FUSES_FCAL(value) (TSENS_FUSES_FCAL_Msk & ((value) << TSENS_FUSES_FCAL_Pos)) 480 481 #define TSENS_FUSES_GAIN_0_ADDR NVMCTRL_TEMP_LOG 482 #define TSENS_FUSES_GAIN_0_Pos 12 /**< \brief (NVMCTRL_TEMP_LOG) Gain Calibration bits 19:0 */ 483 #define TSENS_FUSES_GAIN_0_Msk (_U_(0xFFFFF) << TSENS_FUSES_GAIN_0_Pos) 484 #define TSENS_FUSES_GAIN_0(value) (TSENS_FUSES_GAIN_0_Msk & ((value) << TSENS_FUSES_GAIN_0_Pos)) 485 486 #define TSENS_FUSES_GAIN_1_ADDR (NVMCTRL_TEMP_LOG + 4) 487 #define TSENS_FUSES_GAIN_1_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) Gain Calibration bits 23:20 */ 488 #define TSENS_FUSES_GAIN_1_Msk (_U_(0xF) << TSENS_FUSES_GAIN_1_Pos) 489 #define TSENS_FUSES_GAIN_1(value) (TSENS_FUSES_GAIN_1_Msk & ((value) << TSENS_FUSES_GAIN_1_Pos)) 490 491 #define TSENS_FUSES_OFFSET_ADDR (NVMCTRL_TEMP_LOG + 4) 492 #define TSENS_FUSES_OFFSET_Pos 4 /**< \brief (NVMCTRL_TEMP_LOG) Offse Calibration */ 493 #define TSENS_FUSES_OFFSET_Msk (_U_(0xFFFFFF) << TSENS_FUSES_OFFSET_Pos) 494 #define TSENS_FUSES_OFFSET(value) (TSENS_FUSES_OFFSET_Msk & ((value) << TSENS_FUSES_OFFSET_Pos)) 495 496 #define TSENS_FUSES_TCAL_ADDR NVMCTRL_TEMP_LOG 497 #define TSENS_FUSES_TCAL_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) Temperature Calibration */ 498 #define TSENS_FUSES_TCAL_Msk (_U_(0x3F) << TSENS_FUSES_TCAL_Pos) 499 #define TSENS_FUSES_TCAL(value) (TSENS_FUSES_TCAL_Msk & ((value) << TSENS_FUSES_TCAL_Pos)) 500 501 #define WDT_FUSES_ALWAYSON_ADDR NVMCTRL_USER 502 #define WDT_FUSES_ALWAYSON_Pos 27 /**< \brief (NVMCTRL_USER) WDT Always On */ 503 #define WDT_FUSES_ALWAYSON_Msk (_U_(0x1) << WDT_FUSES_ALWAYSON_Pos) 504 505 #define WDT_FUSES_ENABLE_ADDR NVMCTRL_USER 506 #define WDT_FUSES_ENABLE_Pos 26 /**< \brief (NVMCTRL_USER) WDT Enable */ 507 #define WDT_FUSES_ENABLE_Msk (_U_(0x1) << WDT_FUSES_ENABLE_Pos) 508 509 #define WDT_FUSES_EWOFFSET_ADDR (NVMCTRL_USER + 4) 510 #define WDT_FUSES_EWOFFSET_Pos 4 /**< \brief (NVMCTRL_USER) WDT Early Warning Offset */ 511 #define WDT_FUSES_EWOFFSET_Msk (_U_(0xF) << WDT_FUSES_EWOFFSET_Pos) 512 #define WDT_FUSES_EWOFFSET(value) (WDT_FUSES_EWOFFSET_Msk & ((value) << WDT_FUSES_EWOFFSET_Pos)) 513 514 #define WDT_FUSES_PER_ADDR NVMCTRL_USER 515 #define WDT_FUSES_PER_Pos 28 /**< \brief (NVMCTRL_USER) WDT Period */ 516 #define WDT_FUSES_PER_Msk (_U_(0xF) << WDT_FUSES_PER_Pos) 517 #define WDT_FUSES_PER(value) (WDT_FUSES_PER_Msk & ((value) << WDT_FUSES_PER_Pos)) 518 519 #define WDT_FUSES_WEN_ADDR (NVMCTRL_USER + 4) 520 #define WDT_FUSES_WEN_Pos 8 /**< \brief (NVMCTRL_USER) WDT Window Mode Enable */ 521 #define WDT_FUSES_WEN_Msk (_U_(0x1) << WDT_FUSES_WEN_Pos) 522 523 #define WDT_FUSES_WINDOW_ADDR (NVMCTRL_USER + 4) 524 #define WDT_FUSES_WINDOW_Pos 0 /**< \brief (NVMCTRL_USER) WDT Window */ 525 #define WDT_FUSES_WINDOW_Msk (_U_(0xF) << WDT_FUSES_WINDOW_Pos) 526 #define WDT_FUSES_WINDOW(value) (WDT_FUSES_WINDOW_Msk & ((value) << WDT_FUSES_WINDOW_Pos)) 527 528 /*@}*/ 529 530 #endif /* _SAMC21_NVMCTRL_COMPONENT_ */ 531
