1 /** 2 * \file 3 * 4 * \brief Component description for DSU 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMC21_DSU_COMPONENT_ 31 #define _SAMC21_DSU_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR DSU */ 35 /* ========================================================================== */ 36 /** \addtogroup SAMC21_DSU Device Service Unit */ 37 /*@{*/ 38 39 #define DSU_U2209 40 #define REV_DSU 0x250 41 42 /* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W 8) Control -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint8_t SWRST:1; /*!< bit: 0 Software Reset */ 47 uint8_t :1; /*!< bit: 1 Reserved */ 48 uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Code */ 49 uint8_t MBIST:1; /*!< bit: 3 Memory built-in self-test */ 50 uint8_t CE:1; /*!< bit: 4 Chip-Erase */ 51 uint8_t :1; /*!< bit: 5 Reserved */ 52 uint8_t ARR:1; /*!< bit: 6 Auxiliary Row Read */ 53 uint8_t SMSA:1; /*!< bit: 7 Start Memory Stream Access */ 54 } bit; /*!< Structure used for bit access */ 55 uint8_t reg; /*!< Type used for register access */ 56 } DSU_CTRL_Type; 57 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 58 59 #define DSU_CTRL_OFFSET 0x0000 /**< \brief (DSU_CTRL offset) Control */ 60 #define DSU_CTRL_RESETVALUE _U_(0x00) /**< \brief (DSU_CTRL reset_value) Control */ 61 62 #define DSU_CTRL_SWRST_Pos 0 /**< \brief (DSU_CTRL) Software Reset */ 63 #define DSU_CTRL_SWRST (_U_(0x1) << DSU_CTRL_SWRST_Pos) 64 #define DSU_CTRL_CRC_Pos 2 /**< \brief (DSU_CTRL) 32-bit Cyclic Redundancy Code */ 65 #define DSU_CTRL_CRC (_U_(0x1) << DSU_CTRL_CRC_Pos) 66 #define DSU_CTRL_MBIST_Pos 3 /**< \brief (DSU_CTRL) Memory built-in self-test */ 67 #define DSU_CTRL_MBIST (_U_(0x1) << DSU_CTRL_MBIST_Pos) 68 #define DSU_CTRL_CE_Pos 4 /**< \brief (DSU_CTRL) Chip-Erase */ 69 #define DSU_CTRL_CE (_U_(0x1) << DSU_CTRL_CE_Pos) 70 #define DSU_CTRL_ARR_Pos 6 /**< \brief (DSU_CTRL) Auxiliary Row Read */ 71 #define DSU_CTRL_ARR (_U_(0x1) << DSU_CTRL_ARR_Pos) 72 #define DSU_CTRL_SMSA_Pos 7 /**< \brief (DSU_CTRL) Start Memory Stream Access */ 73 #define DSU_CTRL_SMSA (_U_(0x1) << DSU_CTRL_SMSA_Pos) 74 #define DSU_CTRL_MASK _U_(0xDD) /**< \brief (DSU_CTRL) MASK Register */ 75 76 /* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W 8) Status A -------- */ 77 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 78 typedef union { 79 struct { 80 uint8_t DONE:1; /*!< bit: 0 Done */ 81 uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */ 82 uint8_t BERR:1; /*!< bit: 2 Bus Error */ 83 uint8_t FAIL:1; /*!< bit: 3 Failure */ 84 uint8_t PERR:1; /*!< bit: 4 Protection Error */ 85 uint8_t :3; /*!< bit: 5.. 7 Reserved */ 86 } bit; /*!< Structure used for bit access */ 87 uint8_t reg; /*!< Type used for register access */ 88 } DSU_STATUSA_Type; 89 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 90 91 #define DSU_STATUSA_OFFSET 0x0001 /**< \brief (DSU_STATUSA offset) Status A */ 92 #define DSU_STATUSA_RESETVALUE _U_(0x00) /**< \brief (DSU_STATUSA reset_value) Status A */ 93 94 #define DSU_STATUSA_DONE_Pos 0 /**< \brief (DSU_STATUSA) Done */ 95 #define DSU_STATUSA_DONE (_U_(0x1) << DSU_STATUSA_DONE_Pos) 96 #define DSU_STATUSA_CRSTEXT_Pos 1 /**< \brief (DSU_STATUSA) CPU Reset Phase Extension */ 97 #define DSU_STATUSA_CRSTEXT (_U_(0x1) << DSU_STATUSA_CRSTEXT_Pos) 98 #define DSU_STATUSA_BERR_Pos 2 /**< \brief (DSU_STATUSA) Bus Error */ 99 #define DSU_STATUSA_BERR (_U_(0x1) << DSU_STATUSA_BERR_Pos) 100 #define DSU_STATUSA_FAIL_Pos 3 /**< \brief (DSU_STATUSA) Failure */ 101 #define DSU_STATUSA_FAIL (_U_(0x1) << DSU_STATUSA_FAIL_Pos) 102 #define DSU_STATUSA_PERR_Pos 4 /**< \brief (DSU_STATUSA) Protection Error */ 103 #define DSU_STATUSA_PERR (_U_(0x1) << DSU_STATUSA_PERR_Pos) 104 #define DSU_STATUSA_MASK _U_(0x1F) /**< \brief (DSU_STATUSA) MASK Register */ 105 106 /* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/ 8) Status B -------- */ 107 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 108 typedef union { 109 struct { 110 uint8_t PROT:1; /*!< bit: 0 Protected */ 111 uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */ 112 uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */ 113 uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */ 114 uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */ 115 uint8_t :3; /*!< bit: 5.. 7 Reserved */ 116 } bit; /*!< Structure used for bit access */ 117 struct { 118 uint8_t :2; /*!< bit: 0.. 1 Reserved */ 119 uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */ 120 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 121 } vec; /*!< Structure used for vec access */ 122 uint8_t reg; /*!< Type used for register access */ 123 } DSU_STATUSB_Type; 124 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 125 126 #define DSU_STATUSB_OFFSET 0x0002 /**< \brief (DSU_STATUSB offset) Status B */ 127 #define DSU_STATUSB_RESETVALUE _U_(0x00) /**< \brief (DSU_STATUSB reset_value) Status B */ 128 129 #define DSU_STATUSB_PROT_Pos 0 /**< \brief (DSU_STATUSB) Protected */ 130 #define DSU_STATUSB_PROT (_U_(0x1) << DSU_STATUSB_PROT_Pos) 131 #define DSU_STATUSB_DBGPRES_Pos 1 /**< \brief (DSU_STATUSB) Debugger Present */ 132 #define DSU_STATUSB_DBGPRES (_U_(0x1) << DSU_STATUSB_DBGPRES_Pos) 133 #define DSU_STATUSB_DCCD0_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel 0 Dirty */ 134 #define DSU_STATUSB_DCCD0 (_U_(1) << DSU_STATUSB_DCCD0_Pos) 135 #define DSU_STATUSB_DCCD1_Pos 3 /**< \brief (DSU_STATUSB) Debug Communication Channel 1 Dirty */ 136 #define DSU_STATUSB_DCCD1 (_U_(1) << DSU_STATUSB_DCCD1_Pos) 137 #define DSU_STATUSB_DCCD_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel x Dirty */ 138 #define DSU_STATUSB_DCCD_Msk (_U_(0x3) << DSU_STATUSB_DCCD_Pos) 139 #define DSU_STATUSB_DCCD(value) (DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos)) 140 #define DSU_STATUSB_HPE_Pos 4 /**< \brief (DSU_STATUSB) Hot-Plugging Enable */ 141 #define DSU_STATUSB_HPE (_U_(0x1) << DSU_STATUSB_HPE_Pos) 142 #define DSU_STATUSB_MASK _U_(0x1F) /**< \brief (DSU_STATUSB) MASK Register */ 143 144 /* -------- DSU_STATUSC : (DSU Offset: 0x0003) (R/ 8) Status C -------- */ 145 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 146 typedef union { 147 struct { 148 uint8_t STATE:3; /*!< bit: 0.. 2 State */ 149 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 150 } bit; /*!< Structure used for bit access */ 151 uint8_t reg; /*!< Type used for register access */ 152 } DSU_STATUSC_Type; 153 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 154 155 #define DSU_STATUSC_OFFSET 0x0003 /**< \brief (DSU_STATUSC offset) Status C */ 156 #define DSU_STATUSC_RESETVALUE _U_(0x00) /**< \brief (DSU_STATUSC reset_value) Status C */ 157 158 #define DSU_STATUSC_STATE_Pos 0 /**< \brief (DSU_STATUSC) State */ 159 #define DSU_STATUSC_STATE_Msk (_U_(0x7) << DSU_STATUSC_STATE_Pos) 160 #define DSU_STATUSC_STATE(value) (DSU_STATUSC_STATE_Msk & ((value) << DSU_STATUSC_STATE_Pos)) 161 #define DSU_STATUSC_MASK _U_(0x07) /**< \brief (DSU_STATUSC) MASK Register */ 162 163 /* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */ 164 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 165 typedef union { 166 struct { 167 uint32_t AMOD:2; /*!< bit: 0.. 1 Access Mode */ 168 uint32_t ADDR:30; /*!< bit: 2..31 Address */ 169 } bit; /*!< Structure used for bit access */ 170 uint32_t reg; /*!< Type used for register access */ 171 } DSU_ADDR_Type; 172 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 173 174 #define DSU_ADDR_OFFSET 0x0004 /**< \brief (DSU_ADDR offset) Address */ 175 #define DSU_ADDR_RESETVALUE _U_(0x00000000) /**< \brief (DSU_ADDR reset_value) Address */ 176 177 #define DSU_ADDR_AMOD_Pos 0 /**< \brief (DSU_ADDR) Access Mode */ 178 #define DSU_ADDR_AMOD_Msk (_U_(0x3) << DSU_ADDR_AMOD_Pos) 179 #define DSU_ADDR_AMOD(value) (DSU_ADDR_AMOD_Msk & ((value) << DSU_ADDR_AMOD_Pos)) 180 #define DSU_ADDR_ADDR_Pos 2 /**< \brief (DSU_ADDR) Address */ 181 #define DSU_ADDR_ADDR_Msk (_U_(0x3FFFFFFF) << DSU_ADDR_ADDR_Pos) 182 #define DSU_ADDR_ADDR(value) (DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos)) 183 #define DSU_ADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_ADDR) MASK Register */ 184 185 /* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */ 186 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 187 typedef union { 188 struct { 189 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 190 uint32_t LENGTH:30; /*!< bit: 2..31 Length */ 191 } bit; /*!< Structure used for bit access */ 192 uint32_t reg; /*!< Type used for register access */ 193 } DSU_LENGTH_Type; 194 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 195 196 #define DSU_LENGTH_OFFSET 0x0008 /**< \brief (DSU_LENGTH offset) Length */ 197 #define DSU_LENGTH_RESETVALUE _U_(0x00000000) /**< \brief (DSU_LENGTH reset_value) Length */ 198 199 #define DSU_LENGTH_LENGTH_Pos 2 /**< \brief (DSU_LENGTH) Length */ 200 #define DSU_LENGTH_LENGTH_Msk (_U_(0x3FFFFFFF) << DSU_LENGTH_LENGTH_Pos) 201 #define DSU_LENGTH_LENGTH(value) (DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos)) 202 #define DSU_LENGTH_MASK _U_(0xFFFFFFFC) /**< \brief (DSU_LENGTH) MASK Register */ 203 204 /* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */ 205 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 206 typedef union { 207 struct { 208 uint32_t DATA:32; /*!< bit: 0..31 Data */ 209 } bit; /*!< Structure used for bit access */ 210 uint32_t reg; /*!< Type used for register access */ 211 } DSU_DATA_Type; 212 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 213 214 #define DSU_DATA_OFFSET 0x000C /**< \brief (DSU_DATA offset) Data */ 215 #define DSU_DATA_RESETVALUE _U_(0x00000000) /**< \brief (DSU_DATA reset_value) Data */ 216 217 #define DSU_DATA_DATA_Pos 0 /**< \brief (DSU_DATA) Data */ 218 #define DSU_DATA_DATA_Msk (_U_(0xFFFFFFFF) << DSU_DATA_DATA_Pos) 219 #define DSU_DATA_DATA(value) (DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos)) 220 #define DSU_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_DATA) MASK Register */ 221 222 /* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */ 223 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 224 typedef union { 225 struct { 226 uint32_t DATA:32; /*!< bit: 0..31 Data */ 227 } bit; /*!< Structure used for bit access */ 228 uint32_t reg; /*!< Type used for register access */ 229 } DSU_DCC_Type; 230 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 231 232 #define DSU_DCC_OFFSET 0x0010 /**< \brief (DSU_DCC offset) Debug Communication Channel n */ 233 #define DSU_DCC_RESETVALUE _U_(0x00000000) /**< \brief (DSU_DCC reset_value) Debug Communication Channel n */ 234 235 #define DSU_DCC_DATA_Pos 0 /**< \brief (DSU_DCC) Data */ 236 #define DSU_DCC_DATA_Msk (_U_(0xFFFFFFFF) << DSU_DCC_DATA_Pos) 237 #define DSU_DCC_DATA(value) (DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos)) 238 #define DSU_DCC_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_DCC) MASK Register */ 239 240 /* -------- DSU_DID : (DSU Offset: 0x0018) (R/ 32) Device Identification -------- */ 241 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 242 typedef union { 243 struct { 244 uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */ 245 uint32_t REVISION:4; /*!< bit: 8..11 Revision Number */ 246 uint32_t DIE:4; /*!< bit: 12..15 Die Number */ 247 uint32_t SERIES:6; /*!< bit: 16..21 Series */ 248 uint32_t :1; /*!< bit: 22 Reserved */ 249 uint32_t FAMILY:5; /*!< bit: 23..27 Family */ 250 uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */ 251 } bit; /*!< Structure used for bit access */ 252 uint32_t reg; /*!< Type used for register access */ 253 } DSU_DID_Type; 254 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 255 256 #define DSU_DID_OFFSET 0x0018 /**< \brief (DSU_DID offset) Device Identification */ 257 258 #define DSU_DID_DEVSEL_Pos 0 /**< \brief (DSU_DID) Device Select */ 259 #define DSU_DID_DEVSEL_Msk (_U_(0xFF) << DSU_DID_DEVSEL_Pos) 260 #define DSU_DID_DEVSEL(value) (DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos)) 261 #define DSU_DID_REVISION_Pos 8 /**< \brief (DSU_DID) Revision Number */ 262 #define DSU_DID_REVISION_Msk (_U_(0xF) << DSU_DID_REVISION_Pos) 263 #define DSU_DID_REVISION(value) (DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos)) 264 #define DSU_DID_DIE_Pos 12 /**< \brief (DSU_DID) Die Number */ 265 #define DSU_DID_DIE_Msk (_U_(0xF) << DSU_DID_DIE_Pos) 266 #define DSU_DID_DIE(value) (DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos)) 267 #define DSU_DID_SERIES_Pos 16 /**< \brief (DSU_DID) Series */ 268 #define DSU_DID_SERIES_Msk (_U_(0x3F) << DSU_DID_SERIES_Pos) 269 #define DSU_DID_SERIES(value) (DSU_DID_SERIES_Msk & ((value) << DSU_DID_SERIES_Pos)) 270 #define DSU_DID_SERIES_0_Val _U_(0x0) /**< \brief (DSU_DID) Cortex-M0+ processor, basic feature set */ 271 #define DSU_DID_SERIES_1_Val _U_(0x1) /**< \brief (DSU_DID) Cortex-M0+ processor, CAN */ 272 #define DSU_DID_SERIES_0 (DSU_DID_SERIES_0_Val << DSU_DID_SERIES_Pos) 273 #define DSU_DID_SERIES_1 (DSU_DID_SERIES_1_Val << DSU_DID_SERIES_Pos) 274 #define DSU_DID_FAMILY_Pos 23 /**< \brief (DSU_DID) Family */ 275 #define DSU_DID_FAMILY_Msk (_U_(0x1F) << DSU_DID_FAMILY_Pos) 276 #define DSU_DID_FAMILY(value) (DSU_DID_FAMILY_Msk & ((value) << DSU_DID_FAMILY_Pos)) 277 #define DSU_DID_FAMILY_0_Val _U_(0x0) /**< \brief (DSU_DID) General purpose microcontroller */ 278 #define DSU_DID_FAMILY_1_Val _U_(0x1) /**< \brief (DSU_DID) PicoPower */ 279 #define DSU_DID_FAMILY_2_Val _U_(0x2) /**< \brief (DSU_DID) 5V Industrial */ 280 #define DSU_DID_FAMILY_0 (DSU_DID_FAMILY_0_Val << DSU_DID_FAMILY_Pos) 281 #define DSU_DID_FAMILY_1 (DSU_DID_FAMILY_1_Val << DSU_DID_FAMILY_Pos) 282 #define DSU_DID_FAMILY_2 (DSU_DID_FAMILY_2_Val << DSU_DID_FAMILY_Pos) 283 #define DSU_DID_PROCESSOR_Pos 28 /**< \brief (DSU_DID) Processor */ 284 #define DSU_DID_PROCESSOR_Msk (_U_(0xF) << DSU_DID_PROCESSOR_Pos) 285 #define DSU_DID_PROCESSOR(value) (DSU_DID_PROCESSOR_Msk & ((value) << DSU_DID_PROCESSOR_Pos)) 286 #define DSU_DID_PROCESSOR_0_Val _U_(0x0) /**< \brief (DSU_DID) Cortex-M0 */ 287 #define DSU_DID_PROCESSOR_1_Val _U_(0x1) /**< \brief (DSU_DID) Cortex-M0+ */ 288 #define DSU_DID_PROCESSOR_2_Val _U_(0x2) /**< \brief (DSU_DID) Cortex-M3 */ 289 #define DSU_DID_PROCESSOR_3_Val _U_(0x3) /**< \brief (DSU_DID) Cortex-M4 */ 290 #define DSU_DID_PROCESSOR_0 (DSU_DID_PROCESSOR_0_Val << DSU_DID_PROCESSOR_Pos) 291 #define DSU_DID_PROCESSOR_1 (DSU_DID_PROCESSOR_1_Val << DSU_DID_PROCESSOR_Pos) 292 #define DSU_DID_PROCESSOR_2 (DSU_DID_PROCESSOR_2_Val << DSU_DID_PROCESSOR_Pos) 293 #define DSU_DID_PROCESSOR_3 (DSU_DID_PROCESSOR_3_Val << DSU_DID_PROCESSOR_Pos) 294 #define DSU_DID_MASK _U_(0xFFBFFFFF) /**< \brief (DSU_DID) MASK Register */ 295 296 /* -------- DSU_DCFG : (DSU Offset: 0x00F0) (R/W 32) Device Configuration -------- */ 297 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 298 typedef union { 299 struct { 300 uint32_t DCFG:32; /*!< bit: 0..31 Device Configuration */ 301 } bit; /*!< Structure used for bit access */ 302 uint32_t reg; /*!< Type used for register access */ 303 } DSU_DCFG_Type; 304 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 305 306 #define DSU_DCFG_OFFSET 0x00F0 /**< \brief (DSU_DCFG offset) Device Configuration */ 307 #define DSU_DCFG_RESETVALUE _U_(0x00000000) /**< \brief (DSU_DCFG reset_value) Device Configuration */ 308 309 #define DSU_DCFG_DCFG_Pos 0 /**< \brief (DSU_DCFG) Device Configuration */ 310 #define DSU_DCFG_DCFG_Msk (_U_(0xFFFFFFFF) << DSU_DCFG_DCFG_Pos) 311 #define DSU_DCFG_DCFG(value) (DSU_DCFG_DCFG_Msk & ((value) << DSU_DCFG_DCFG_Pos)) 312 #define DSU_DCFG_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_DCFG) MASK Register */ 313 314 /* -------- DSU_ENTRY0 : (DSU Offset: 0x1000) (R/ 32) CoreSight ROM Table Entry 0 -------- */ 315 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 316 typedef union { 317 struct { 318 uint32_t EPRES:1; /*!< bit: 0 Entry Present */ 319 uint32_t FMT:1; /*!< bit: 1 Format */ 320 uint32_t :10; /*!< bit: 2..11 Reserved */ 321 uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */ 322 } bit; /*!< Structure used for bit access */ 323 uint32_t reg; /*!< Type used for register access */ 324 } DSU_ENTRY0_Type; 325 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 326 327 #define DSU_ENTRY0_OFFSET 0x1000 /**< \brief (DSU_ENTRY0 offset) CoreSight ROM Table Entry 0 */ 328 #define DSU_ENTRY0_RESETVALUE _U_(0x9F0FC002) /**< \brief (DSU_ENTRY0 reset_value) CoreSight ROM Table Entry 0 */ 329 330 #define DSU_ENTRY0_EPRES_Pos 0 /**< \brief (DSU_ENTRY0) Entry Present */ 331 #define DSU_ENTRY0_EPRES (_U_(0x1) << DSU_ENTRY0_EPRES_Pos) 332 #define DSU_ENTRY0_FMT_Pos 1 /**< \brief (DSU_ENTRY0) Format */ 333 #define DSU_ENTRY0_FMT (_U_(0x1) << DSU_ENTRY0_FMT_Pos) 334 #define DSU_ENTRY0_ADDOFF_Pos 12 /**< \brief (DSU_ENTRY0) Address Offset */ 335 #define DSU_ENTRY0_ADDOFF_Msk (_U_(0xFFFFF) << DSU_ENTRY0_ADDOFF_Pos) 336 #define DSU_ENTRY0_ADDOFF(value) (DSU_ENTRY0_ADDOFF_Msk & ((value) << DSU_ENTRY0_ADDOFF_Pos)) 337 #define DSU_ENTRY0_MASK _U_(0xFFFFF003) /**< \brief (DSU_ENTRY0) MASK Register */ 338 339 /* -------- DSU_ENTRY1 : (DSU Offset: 0x1004) (R/ 32) CoreSight ROM Table Entry 1 -------- */ 340 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 341 typedef union { 342 uint32_t reg; /*!< Type used for register access */ 343 } DSU_ENTRY1_Type; 344 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 345 346 #define DSU_ENTRY1_OFFSET 0x1004 /**< \brief (DSU_ENTRY1 offset) CoreSight ROM Table Entry 1 */ 347 #define DSU_ENTRY1_RESETVALUE _U_(0x00005002) /**< \brief (DSU_ENTRY1 reset_value) CoreSight ROM Table Entry 1 */ 348 #define DSU_ENTRY1_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_ENTRY1) MASK Register */ 349 350 /* -------- DSU_END : (DSU Offset: 0x1008) (R/ 32) CoreSight ROM Table End -------- */ 351 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 352 typedef union { 353 struct { 354 uint32_t END:32; /*!< bit: 0..31 End Marker */ 355 } bit; /*!< Structure used for bit access */ 356 uint32_t reg; /*!< Type used for register access */ 357 } DSU_END_Type; 358 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 359 360 #define DSU_END_OFFSET 0x1008 /**< \brief (DSU_END offset) CoreSight ROM Table End */ 361 #define DSU_END_RESETVALUE _U_(0x00000000) /**< \brief (DSU_END reset_value) CoreSight ROM Table End */ 362 363 #define DSU_END_END_Pos 0 /**< \brief (DSU_END) End Marker */ 364 #define DSU_END_END_Msk (_U_(0xFFFFFFFF) << DSU_END_END_Pos) 365 #define DSU_END_END(value) (DSU_END_END_Msk & ((value) << DSU_END_END_Pos)) 366 #define DSU_END_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_END) MASK Register */ 367 368 /* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/ 32) CoreSight ROM Table Memory Type -------- */ 369 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 370 typedef union { 371 struct { 372 uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */ 373 uint32_t :31; /*!< bit: 1..31 Reserved */ 374 } bit; /*!< Structure used for bit access */ 375 uint32_t reg; /*!< Type used for register access */ 376 } DSU_MEMTYPE_Type; 377 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 378 379 #define DSU_MEMTYPE_OFFSET 0x1FCC /**< \brief (DSU_MEMTYPE offset) CoreSight ROM Table Memory Type */ 380 #define DSU_MEMTYPE_RESETVALUE _U_(0x00000000) /**< \brief (DSU_MEMTYPE reset_value) CoreSight ROM Table Memory Type */ 381 382 #define DSU_MEMTYPE_SMEMP_Pos 0 /**< \brief (DSU_MEMTYPE) System Memory Present */ 383 #define DSU_MEMTYPE_SMEMP (_U_(0x1) << DSU_MEMTYPE_SMEMP_Pos) 384 #define DSU_MEMTYPE_MASK _U_(0x00000001) /**< \brief (DSU_MEMTYPE) MASK Register */ 385 386 /* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/ 32) Peripheral Identification 4 -------- */ 387 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 388 typedef union { 389 struct { 390 uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */ 391 uint32_t FKBC:4; /*!< bit: 4.. 7 4KB count */ 392 uint32_t :24; /*!< bit: 8..31 Reserved */ 393 } bit; /*!< Structure used for bit access */ 394 uint32_t reg; /*!< Type used for register access */ 395 } DSU_PID4_Type; 396 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 397 398 #define DSU_PID4_OFFSET 0x1FD0 /**< \brief (DSU_PID4 offset) Peripheral Identification 4 */ 399 #define DSU_PID4_RESETVALUE _U_(0x00000000) /**< \brief (DSU_PID4 reset_value) Peripheral Identification 4 */ 400 401 #define DSU_PID4_JEPCC_Pos 0 /**< \brief (DSU_PID4) JEP-106 Continuation Code */ 402 #define DSU_PID4_JEPCC_Msk (_U_(0xF) << DSU_PID4_JEPCC_Pos) 403 #define DSU_PID4_JEPCC(value) (DSU_PID4_JEPCC_Msk & ((value) << DSU_PID4_JEPCC_Pos)) 404 #define DSU_PID4_FKBC_Pos 4 /**< \brief (DSU_PID4) 4KB count */ 405 #define DSU_PID4_FKBC_Msk (_U_(0xF) << DSU_PID4_FKBC_Pos) 406 #define DSU_PID4_FKBC(value) (DSU_PID4_FKBC_Msk & ((value) << DSU_PID4_FKBC_Pos)) 407 #define DSU_PID4_MASK _U_(0x000000FF) /**< \brief (DSU_PID4) MASK Register */ 408 409 /* -------- DSU_PID5 : (DSU Offset: 0x1FD4) (R/ 32) Peripheral Identification 5 -------- */ 410 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 411 typedef union { 412 uint32_t reg; /*!< Type used for register access */ 413 } DSU_PID5_Type; 414 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 415 416 #define DSU_PID5_OFFSET 0x1FD4 /**< \brief (DSU_PID5 offset) Peripheral Identification 5 */ 417 #define DSU_PID5_RESETVALUE _U_(0x00000000) /**< \brief (DSU_PID5 reset_value) Peripheral Identification 5 */ 418 #define DSU_PID5_MASK _U_(0x00000000) /**< \brief (DSU_PID5) MASK Register */ 419 420 /* -------- DSU_PID6 : (DSU Offset: 0x1FD8) (R/ 32) Peripheral Identification 6 -------- */ 421 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 422 typedef union { 423 uint32_t reg; /*!< Type used for register access */ 424 } DSU_PID6_Type; 425 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 426 427 #define DSU_PID6_OFFSET 0x1FD8 /**< \brief (DSU_PID6 offset) Peripheral Identification 6 */ 428 #define DSU_PID6_RESETVALUE _U_(0x00000000) /**< \brief (DSU_PID6 reset_value) Peripheral Identification 6 */ 429 #define DSU_PID6_MASK _U_(0x00000000) /**< \brief (DSU_PID6) MASK Register */ 430 431 /* -------- DSU_PID7 : (DSU Offset: 0x1FDC) (R/ 32) Peripheral Identification 7 -------- */ 432 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 433 typedef union { 434 uint32_t reg; /*!< Type used for register access */ 435 } DSU_PID7_Type; 436 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 437 438 #define DSU_PID7_OFFSET 0x1FDC /**< \brief (DSU_PID7 offset) Peripheral Identification 7 */ 439 #define DSU_PID7_RESETVALUE _U_(0x00000000) /**< \brief (DSU_PID7 reset_value) Peripheral Identification 7 */ 440 #define DSU_PID7_MASK _U_(0x00000000) /**< \brief (DSU_PID7) MASK Register */ 441 442 /* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/ 32) Peripheral Identification 0 -------- */ 443 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 444 typedef union { 445 struct { 446 uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */ 447 uint32_t :24; /*!< bit: 8..31 Reserved */ 448 } bit; /*!< Structure used for bit access */ 449 uint32_t reg; /*!< Type used for register access */ 450 } DSU_PID0_Type; 451 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 452 453 #define DSU_PID0_OFFSET 0x1FE0 /**< \brief (DSU_PID0 offset) Peripheral Identification 0 */ 454 #define DSU_PID0_RESETVALUE _U_(0x000000D0) /**< \brief (DSU_PID0 reset_value) Peripheral Identification 0 */ 455 456 #define DSU_PID0_PARTNBL_Pos 0 /**< \brief (DSU_PID0) Part Number Low */ 457 #define DSU_PID0_PARTNBL_Msk (_U_(0xFF) << DSU_PID0_PARTNBL_Pos) 458 #define DSU_PID0_PARTNBL(value) (DSU_PID0_PARTNBL_Msk & ((value) << DSU_PID0_PARTNBL_Pos)) 459 #define DSU_PID0_MASK _U_(0x000000FF) /**< \brief (DSU_PID0) MASK Register */ 460 461 /* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/ 32) Peripheral Identification 1 -------- */ 462 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 463 typedef union { 464 struct { 465 uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */ 466 uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */ 467 uint32_t :24; /*!< bit: 8..31 Reserved */ 468 } bit; /*!< Structure used for bit access */ 469 uint32_t reg; /*!< Type used for register access */ 470 } DSU_PID1_Type; 471 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 472 473 #define DSU_PID1_OFFSET 0x1FE4 /**< \brief (DSU_PID1 offset) Peripheral Identification 1 */ 474 #define DSU_PID1_RESETVALUE _U_(0x000000FC) /**< \brief (DSU_PID1 reset_value) Peripheral Identification 1 */ 475 476 #define DSU_PID1_PARTNBH_Pos 0 /**< \brief (DSU_PID1) Part Number High */ 477 #define DSU_PID1_PARTNBH_Msk (_U_(0xF) << DSU_PID1_PARTNBH_Pos) 478 #define DSU_PID1_PARTNBH(value) (DSU_PID1_PARTNBH_Msk & ((value) << DSU_PID1_PARTNBH_Pos)) 479 #define DSU_PID1_JEPIDCL_Pos 4 /**< \brief (DSU_PID1) Low part of the JEP-106 Identity Code */ 480 #define DSU_PID1_JEPIDCL_Msk (_U_(0xF) << DSU_PID1_JEPIDCL_Pos) 481 #define DSU_PID1_JEPIDCL(value) (DSU_PID1_JEPIDCL_Msk & ((value) << DSU_PID1_JEPIDCL_Pos)) 482 #define DSU_PID1_MASK _U_(0x000000FF) /**< \brief (DSU_PID1) MASK Register */ 483 484 /* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/ 32) Peripheral Identification 2 -------- */ 485 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 486 typedef union { 487 struct { 488 uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */ 489 uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */ 490 uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */ 491 uint32_t :24; /*!< bit: 8..31 Reserved */ 492 } bit; /*!< Structure used for bit access */ 493 uint32_t reg; /*!< Type used for register access */ 494 } DSU_PID2_Type; 495 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 496 497 #define DSU_PID2_OFFSET 0x1FE8 /**< \brief (DSU_PID2 offset) Peripheral Identification 2 */ 498 #define DSU_PID2_RESETVALUE _U_(0x00000009) /**< \brief (DSU_PID2 reset_value) Peripheral Identification 2 */ 499 500 #define DSU_PID2_JEPIDCH_Pos 0 /**< \brief (DSU_PID2) JEP-106 Identity Code High */ 501 #define DSU_PID2_JEPIDCH_Msk (_U_(0x7) << DSU_PID2_JEPIDCH_Pos) 502 #define DSU_PID2_JEPIDCH(value) (DSU_PID2_JEPIDCH_Msk & ((value) << DSU_PID2_JEPIDCH_Pos)) 503 #define DSU_PID2_JEPU_Pos 3 /**< \brief (DSU_PID2) JEP-106 Identity Code is used */ 504 #define DSU_PID2_JEPU (_U_(0x1) << DSU_PID2_JEPU_Pos) 505 #define DSU_PID2_REVISION_Pos 4 /**< \brief (DSU_PID2) Revision Number */ 506 #define DSU_PID2_REVISION_Msk (_U_(0xF) << DSU_PID2_REVISION_Pos) 507 #define DSU_PID2_REVISION(value) (DSU_PID2_REVISION_Msk & ((value) << DSU_PID2_REVISION_Pos)) 508 #define DSU_PID2_MASK _U_(0x000000FF) /**< \brief (DSU_PID2) MASK Register */ 509 510 /* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/ 32) Peripheral Identification 3 -------- */ 511 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 512 typedef union { 513 struct { 514 uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */ 515 uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */ 516 uint32_t :24; /*!< bit: 8..31 Reserved */ 517 } bit; /*!< Structure used for bit access */ 518 uint32_t reg; /*!< Type used for register access */ 519 } DSU_PID3_Type; 520 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 521 522 #define DSU_PID3_OFFSET 0x1FEC /**< \brief (DSU_PID3 offset) Peripheral Identification 3 */ 523 #define DSU_PID3_RESETVALUE _U_(0x00000000) /**< \brief (DSU_PID3 reset_value) Peripheral Identification 3 */ 524 525 #define DSU_PID3_CUSMOD_Pos 0 /**< \brief (DSU_PID3) ARM CUSMOD */ 526 #define DSU_PID3_CUSMOD_Msk (_U_(0xF) << DSU_PID3_CUSMOD_Pos) 527 #define DSU_PID3_CUSMOD(value) (DSU_PID3_CUSMOD_Msk & ((value) << DSU_PID3_CUSMOD_Pos)) 528 #define DSU_PID3_REVAND_Pos 4 /**< \brief (DSU_PID3) Revision Number */ 529 #define DSU_PID3_REVAND_Msk (_U_(0xF) << DSU_PID3_REVAND_Pos) 530 #define DSU_PID3_REVAND(value) (DSU_PID3_REVAND_Msk & ((value) << DSU_PID3_REVAND_Pos)) 531 #define DSU_PID3_MASK _U_(0x000000FF) /**< \brief (DSU_PID3) MASK Register */ 532 533 /* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/ 32) Component Identification 0 -------- */ 534 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 535 typedef union { 536 struct { 537 uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */ 538 uint32_t :24; /*!< bit: 8..31 Reserved */ 539 } bit; /*!< Structure used for bit access */ 540 uint32_t reg; /*!< Type used for register access */ 541 } DSU_CID0_Type; 542 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 543 544 #define DSU_CID0_OFFSET 0x1FF0 /**< \brief (DSU_CID0 offset) Component Identification 0 */ 545 #define DSU_CID0_RESETVALUE _U_(0x0000000D) /**< \brief (DSU_CID0 reset_value) Component Identification 0 */ 546 547 #define DSU_CID0_PREAMBLEB0_Pos 0 /**< \brief (DSU_CID0) Preamble Byte 0 */ 548 #define DSU_CID0_PREAMBLEB0_Msk (_U_(0xFF) << DSU_CID0_PREAMBLEB0_Pos) 549 #define DSU_CID0_PREAMBLEB0(value) (DSU_CID0_PREAMBLEB0_Msk & ((value) << DSU_CID0_PREAMBLEB0_Pos)) 550 #define DSU_CID0_MASK _U_(0x000000FF) /**< \brief (DSU_CID0) MASK Register */ 551 552 /* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/ 32) Component Identification 1 -------- */ 553 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 554 typedef union { 555 struct { 556 uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */ 557 uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */ 558 uint32_t :24; /*!< bit: 8..31 Reserved */ 559 } bit; /*!< Structure used for bit access */ 560 uint32_t reg; /*!< Type used for register access */ 561 } DSU_CID1_Type; 562 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 563 564 #define DSU_CID1_OFFSET 0x1FF4 /**< \brief (DSU_CID1 offset) Component Identification 1 */ 565 #define DSU_CID1_RESETVALUE _U_(0x00000010) /**< \brief (DSU_CID1 reset_value) Component Identification 1 */ 566 567 #define DSU_CID1_PREAMBLE_Pos 0 /**< \brief (DSU_CID1) Preamble */ 568 #define DSU_CID1_PREAMBLE_Msk (_U_(0xF) << DSU_CID1_PREAMBLE_Pos) 569 #define DSU_CID1_PREAMBLE(value) (DSU_CID1_PREAMBLE_Msk & ((value) << DSU_CID1_PREAMBLE_Pos)) 570 #define DSU_CID1_CCLASS_Pos 4 /**< \brief (DSU_CID1) Component Class */ 571 #define DSU_CID1_CCLASS_Msk (_U_(0xF) << DSU_CID1_CCLASS_Pos) 572 #define DSU_CID1_CCLASS(value) (DSU_CID1_CCLASS_Msk & ((value) << DSU_CID1_CCLASS_Pos)) 573 #define DSU_CID1_MASK _U_(0x000000FF) /**< \brief (DSU_CID1) MASK Register */ 574 575 /* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/ 32) Component Identification 2 -------- */ 576 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 577 typedef union { 578 struct { 579 uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */ 580 uint32_t :24; /*!< bit: 8..31 Reserved */ 581 } bit; /*!< Structure used for bit access */ 582 uint32_t reg; /*!< Type used for register access */ 583 } DSU_CID2_Type; 584 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 585 586 #define DSU_CID2_OFFSET 0x1FF8 /**< \brief (DSU_CID2 offset) Component Identification 2 */ 587 #define DSU_CID2_RESETVALUE _U_(0x00000005) /**< \brief (DSU_CID2 reset_value) Component Identification 2 */ 588 589 #define DSU_CID2_PREAMBLEB2_Pos 0 /**< \brief (DSU_CID2) Preamble Byte 2 */ 590 #define DSU_CID2_PREAMBLEB2_Msk (_U_(0xFF) << DSU_CID2_PREAMBLEB2_Pos) 591 #define DSU_CID2_PREAMBLEB2(value) (DSU_CID2_PREAMBLEB2_Msk & ((value) << DSU_CID2_PREAMBLEB2_Pos)) 592 #define DSU_CID2_MASK _U_(0x000000FF) /**< \brief (DSU_CID2) MASK Register */ 593 594 /* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/ 32) Component Identification 3 -------- */ 595 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 596 typedef union { 597 struct { 598 uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */ 599 uint32_t :24; /*!< bit: 8..31 Reserved */ 600 } bit; /*!< Structure used for bit access */ 601 uint32_t reg; /*!< Type used for register access */ 602 } DSU_CID3_Type; 603 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 604 605 #define DSU_CID3_OFFSET 0x1FFC /**< \brief (DSU_CID3 offset) Component Identification 3 */ 606 #define DSU_CID3_RESETVALUE _U_(0x000000B1) /**< \brief (DSU_CID3 reset_value) Component Identification 3 */ 607 608 #define DSU_CID3_PREAMBLEB3_Pos 0 /**< \brief (DSU_CID3) Preamble Byte 3 */ 609 #define DSU_CID3_PREAMBLEB3_Msk (_U_(0xFF) << DSU_CID3_PREAMBLEB3_Pos) 610 #define DSU_CID3_PREAMBLEB3(value) (DSU_CID3_PREAMBLEB3_Msk & ((value) << DSU_CID3_PREAMBLEB3_Pos)) 611 #define DSU_CID3_MASK _U_(0x000000FF) /**< \brief (DSU_CID3) MASK Register */ 612 613 /** \brief DSU hardware registers */ 614 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 615 typedef struct { 616 __O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */ 617 __IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */ 618 __I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */ 619 __I DSU_STATUSC_Type STATUSC; /**< \brief Offset: 0x0003 (R/ 8) Status C */ 620 __IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */ 621 __IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */ 622 __IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */ 623 __IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */ 624 __I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */ 625 RoReg8 Reserved1[0xD4]; 626 __IO DSU_DCFG_Type DCFG[2]; /**< \brief Offset: 0x00F0 (R/W 32) Device Configuration */ 627 RoReg8 Reserved2[0xF08]; 628 __I DSU_ENTRY0_Type ENTRY0; /**< \brief Offset: 0x1000 (R/ 32) CoreSight ROM Table Entry 0 */ 629 __I DSU_ENTRY1_Type ENTRY1; /**< \brief Offset: 0x1004 (R/ 32) CoreSight ROM Table Entry 1 */ 630 __I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) CoreSight ROM Table End */ 631 RoReg8 Reserved3[0xFC0]; 632 __I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) CoreSight ROM Table Memory Type */ 633 __I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */ 634 __I DSU_PID5_Type PID5; /**< \brief Offset: 0x1FD4 (R/ 32) Peripheral Identification 5 */ 635 __I DSU_PID6_Type PID6; /**< \brief Offset: 0x1FD8 (R/ 32) Peripheral Identification 6 */ 636 __I DSU_PID7_Type PID7; /**< \brief Offset: 0x1FDC (R/ 32) Peripheral Identification 7 */ 637 __I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */ 638 __I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */ 639 __I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */ 640 __I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */ 641 __I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */ 642 __I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */ 643 __I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */ 644 __I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */ 645 } Dsu; 646 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 647 648 /*@}*/ 649 650 #endif /* _SAMC21_DSU_COMPONENT_ */ 651
