1 /** 2 * \file 3 * 4 * \brief Component description for DAC 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMC21_DAC_COMPONENT_ 31 #define _SAMC21_DAC_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR DAC */ 35 /* ========================================================================== */ 36 /** \addtogroup SAMC21_DAC Digital Analog Converter */ 37 /*@{*/ 38 39 #define DAC_U2214 40 #define REV_DAC 0x201 41 42 /* -------- DAC_CTRLA : (DAC Offset: 0x00) (R/W 8) Control A -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint8_t SWRST:1; /*!< bit: 0 Software Reset */ 47 uint8_t ENABLE:1; /*!< bit: 1 Enable */ 48 uint8_t :4; /*!< bit: 2.. 5 Reserved */ 49 uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ 50 uint8_t :1; /*!< bit: 7 Reserved */ 51 } bit; /*!< Structure used for bit access */ 52 uint8_t reg; /*!< Type used for register access */ 53 } DAC_CTRLA_Type; 54 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 55 56 #define DAC_CTRLA_OFFSET 0x00 /**< \brief (DAC_CTRLA offset) Control A */ 57 #define DAC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (DAC_CTRLA reset_value) Control A */ 58 59 #define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */ 60 #define DAC_CTRLA_SWRST (_U_(0x1) << DAC_CTRLA_SWRST_Pos) 61 #define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable */ 62 #define DAC_CTRLA_ENABLE (_U_(0x1) << DAC_CTRLA_ENABLE_Pos) 63 #define DAC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (DAC_CTRLA) Run in Standby */ 64 #define DAC_CTRLA_RUNSTDBY (_U_(0x1) << DAC_CTRLA_RUNSTDBY_Pos) 65 #define DAC_CTRLA_MASK _U_(0x43) /**< \brief (DAC_CTRLA) MASK Register */ 66 67 /* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W 8) Control B -------- */ 68 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 69 typedef union { 70 struct { 71 uint8_t EOEN:1; /*!< bit: 0 External Output Enable */ 72 uint8_t IOEN:1; /*!< bit: 1 Internal Output Enable */ 73 uint8_t LEFTADJ:1; /*!< bit: 2 Left Adjusted Data */ 74 uint8_t VPD:1; /*!< bit: 3 Voltage Pump Disable */ 75 uint8_t :1; /*!< bit: 4 Reserved */ 76 uint8_t DITHER:1; /*!< bit: 5 Dither Enable */ 77 uint8_t REFSEL:2; /*!< bit: 6.. 7 Reference Selection */ 78 } bit; /*!< Structure used for bit access */ 79 uint8_t reg; /*!< Type used for register access */ 80 } DAC_CTRLB_Type; 81 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 82 83 #define DAC_CTRLB_OFFSET 0x01 /**< \brief (DAC_CTRLB offset) Control B */ 84 #define DAC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (DAC_CTRLB reset_value) Control B */ 85 86 #define DAC_CTRLB_EOEN_Pos 0 /**< \brief (DAC_CTRLB) External Output Enable */ 87 #define DAC_CTRLB_EOEN (_U_(0x1) << DAC_CTRLB_EOEN_Pos) 88 #define DAC_CTRLB_IOEN_Pos 1 /**< \brief (DAC_CTRLB) Internal Output Enable */ 89 #define DAC_CTRLB_IOEN (_U_(0x1) << DAC_CTRLB_IOEN_Pos) 90 #define DAC_CTRLB_LEFTADJ_Pos 2 /**< \brief (DAC_CTRLB) Left Adjusted Data */ 91 #define DAC_CTRLB_LEFTADJ (_U_(0x1) << DAC_CTRLB_LEFTADJ_Pos) 92 #define DAC_CTRLB_VPD_Pos 3 /**< \brief (DAC_CTRLB) Voltage Pump Disable */ 93 #define DAC_CTRLB_VPD (_U_(0x1) << DAC_CTRLB_VPD_Pos) 94 #define DAC_CTRLB_DITHER_Pos 5 /**< \brief (DAC_CTRLB) Dither Enable */ 95 #define DAC_CTRLB_DITHER (_U_(0x1) << DAC_CTRLB_DITHER_Pos) 96 #define DAC_CTRLB_REFSEL_Pos 6 /**< \brief (DAC_CTRLB) Reference Selection */ 97 #define DAC_CTRLB_REFSEL_Msk (_U_(0x3) << DAC_CTRLB_REFSEL_Pos) 98 #define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos)) 99 #define DAC_CTRLB_REFSEL_INT1V_Val _U_(0x0) /**< \brief (DAC_CTRLB) Internal 1.0V reference */ 100 #define DAC_CTRLB_REFSEL_AVCC_Val _U_(0x1) /**< \brief (DAC_CTRLB) AVCC */ 101 #define DAC_CTRLB_REFSEL_VREFP_Val _U_(0x2) /**< \brief (DAC_CTRLB) External reference */ 102 #define DAC_CTRLB_REFSEL_INT1V (DAC_CTRLB_REFSEL_INT1V_Val << DAC_CTRLB_REFSEL_Pos) 103 #define DAC_CTRLB_REFSEL_AVCC (DAC_CTRLB_REFSEL_AVCC_Val << DAC_CTRLB_REFSEL_Pos) 104 #define DAC_CTRLB_REFSEL_VREFP (DAC_CTRLB_REFSEL_VREFP_Val << DAC_CTRLB_REFSEL_Pos) 105 #define DAC_CTRLB_MASK _U_(0xEF) /**< \brief (DAC_CTRLB) MASK Register */ 106 107 /* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W 8) Event Control -------- */ 108 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 109 typedef union { 110 struct { 111 uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event Input */ 112 uint8_t EMPTYEO:1; /*!< bit: 1 Data Buffer Empty Event Output */ 113 uint8_t INVEI:1; /*!< bit: 2 Invert Event Input */ 114 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 115 } bit; /*!< Structure used for bit access */ 116 uint8_t reg; /*!< Type used for register access */ 117 } DAC_EVCTRL_Type; 118 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 119 120 #define DAC_EVCTRL_OFFSET 0x02 /**< \brief (DAC_EVCTRL offset) Event Control */ 121 #define DAC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_EVCTRL reset_value) Event Control */ 122 123 #define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input */ 124 #define DAC_EVCTRL_STARTEI (_U_(0x1) << DAC_EVCTRL_STARTEI_Pos) 125 #define DAC_EVCTRL_EMPTYEO_Pos 1 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output */ 126 #define DAC_EVCTRL_EMPTYEO (_U_(0x1) << DAC_EVCTRL_EMPTYEO_Pos) 127 #define DAC_EVCTRL_INVEI_Pos 2 /**< \brief (DAC_EVCTRL) Invert Event Input */ 128 #define DAC_EVCTRL_INVEI (_U_(0x1) << DAC_EVCTRL_INVEI_Pos) 129 #define DAC_EVCTRL_MASK _U_(0x07) /**< \brief (DAC_EVCTRL) MASK Register */ 130 131 /* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ 132 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 133 typedef union { 134 struct { 135 uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */ 136 uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */ 137 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 138 } bit; /*!< Structure used for bit access */ 139 uint8_t reg; /*!< Type used for register access */ 140 } DAC_INTENCLR_Type; 141 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 142 143 #define DAC_INTENCLR_OFFSET 0x04 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */ 144 #define DAC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */ 145 146 #define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable */ 147 #define DAC_INTENCLR_UNDERRUN (_U_(0x1) << DAC_INTENCLR_UNDERRUN_Pos) 148 #define DAC_INTENCLR_EMPTY_Pos 1 /**< \brief (DAC_INTENCLR) Data Buffer Empty Interrupt Enable */ 149 #define DAC_INTENCLR_EMPTY (_U_(0x1) << DAC_INTENCLR_EMPTY_Pos) 150 #define DAC_INTENCLR_MASK _U_(0x03) /**< \brief (DAC_INTENCLR) MASK Register */ 151 152 /* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ 153 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 154 typedef union { 155 struct { 156 uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */ 157 uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */ 158 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 159 } bit; /*!< Structure used for bit access */ 160 uint8_t reg; /*!< Type used for register access */ 161 } DAC_INTENSET_Type; 162 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 163 164 #define DAC_INTENSET_OFFSET 0x05 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */ 165 #define DAC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */ 166 167 #define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable */ 168 #define DAC_INTENSET_UNDERRUN (_U_(0x1) << DAC_INTENSET_UNDERRUN_Pos) 169 #define DAC_INTENSET_EMPTY_Pos 1 /**< \brief (DAC_INTENSET) Data Buffer Empty Interrupt Enable */ 170 #define DAC_INTENSET_EMPTY (_U_(0x1) << DAC_INTENSET_EMPTY_Pos) 171 #define DAC_INTENSET_MASK _U_(0x03) /**< \brief (DAC_INTENSET) MASK Register */ 172 173 /* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ 174 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 175 typedef union { // __I to avoid read-modify-write on write-to-clear register 176 struct { 177 __I uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */ 178 __I uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */ 179 __I uint8_t :6; /*!< bit: 2.. 7 Reserved */ 180 } bit; /*!< Structure used for bit access */ 181 uint8_t reg; /*!< Type used for register access */ 182 } DAC_INTFLAG_Type; 183 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 184 185 #define DAC_INTFLAG_OFFSET 0x06 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */ 186 #define DAC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */ 187 188 #define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Underrun */ 189 #define DAC_INTFLAG_UNDERRUN (_U_(0x1) << DAC_INTFLAG_UNDERRUN_Pos) 190 #define DAC_INTFLAG_EMPTY_Pos 1 /**< \brief (DAC_INTFLAG) Data Buffer Empty */ 191 #define DAC_INTFLAG_EMPTY (_U_(0x1) << DAC_INTFLAG_EMPTY_Pos) 192 #define DAC_INTFLAG_MASK _U_(0x03) /**< \brief (DAC_INTFLAG) MASK Register */ 193 194 /* -------- DAC_STATUS : (DAC Offset: 0x07) (R/ 8) Status -------- */ 195 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 196 typedef union { 197 struct { 198 uint8_t READY:1; /*!< bit: 0 Ready */ 199 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 200 } bit; /*!< Structure used for bit access */ 201 uint8_t reg; /*!< Type used for register access */ 202 } DAC_STATUS_Type; 203 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 204 205 #define DAC_STATUS_OFFSET 0x07 /**< \brief (DAC_STATUS offset) Status */ 206 #define DAC_STATUS_RESETVALUE _U_(0x00) /**< \brief (DAC_STATUS reset_value) Status */ 207 208 #define DAC_STATUS_READY_Pos 0 /**< \brief (DAC_STATUS) Ready */ 209 #define DAC_STATUS_READY (_U_(0x1) << DAC_STATUS_READY_Pos) 210 #define DAC_STATUS_MASK _U_(0x01) /**< \brief (DAC_STATUS) MASK Register */ 211 212 /* -------- DAC_DATA : (DAC Offset: 0x08) ( /W 16) Data -------- */ 213 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 214 typedef union { 215 struct { 216 uint16_t DATA:16; /*!< bit: 0..15 Data value to be converted */ 217 } bit; /*!< Structure used for bit access */ 218 uint16_t reg; /*!< Type used for register access */ 219 } DAC_DATA_Type; 220 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 221 222 #define DAC_DATA_OFFSET 0x08 /**< \brief (DAC_DATA offset) Data */ 223 #define DAC_DATA_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATA reset_value) Data */ 224 225 #define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) Data value to be converted */ 226 #define DAC_DATA_DATA_Msk (_U_(0xFFFF) << DAC_DATA_DATA_Pos) 227 #define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos)) 228 #define DAC_DATA_MASK _U_(0xFFFF) /**< \brief (DAC_DATA) MASK Register */ 229 230 /* -------- DAC_DATABUF : (DAC Offset: 0x0C) ( /W 16) Data Buffer -------- */ 231 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 232 typedef union { 233 struct { 234 uint16_t DATABUF:16; /*!< bit: 0..15 Data Buffer */ 235 } bit; /*!< Structure used for bit access */ 236 uint16_t reg; /*!< Type used for register access */ 237 } DAC_DATABUF_Type; 238 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 239 240 #define DAC_DATABUF_OFFSET 0x0C /**< \brief (DAC_DATABUF offset) Data Buffer */ 241 #define DAC_DATABUF_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATABUF reset_value) Data Buffer */ 242 243 #define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) Data Buffer */ 244 #define DAC_DATABUF_DATABUF_Msk (_U_(0xFFFF) << DAC_DATABUF_DATABUF_Pos) 245 #define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos)) 246 #define DAC_DATABUF_MASK _U_(0xFFFF) /**< \brief (DAC_DATABUF) MASK Register */ 247 248 /* -------- DAC_SYNCBUSY : (DAC Offset: 0x10) (R/ 32) Synchronization Busy -------- */ 249 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 250 typedef union { 251 struct { 252 uint32_t SWRST:1; /*!< bit: 0 Software Reset */ 253 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 254 uint32_t DATA:1; /*!< bit: 2 Data */ 255 uint32_t DATABUF:1; /*!< bit: 3 Data Buffer */ 256 uint32_t :28; /*!< bit: 4..31 Reserved */ 257 } bit; /*!< Structure used for bit access */ 258 uint32_t reg; /*!< Type used for register access */ 259 } DAC_SYNCBUSY_Type; 260 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 261 262 #define DAC_SYNCBUSY_OFFSET 0x10 /**< \brief (DAC_SYNCBUSY offset) Synchronization Busy */ 263 #define DAC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (DAC_SYNCBUSY reset_value) Synchronization Busy */ 264 265 #define DAC_SYNCBUSY_SWRST_Pos 0 /**< \brief (DAC_SYNCBUSY) Software Reset */ 266 #define DAC_SYNCBUSY_SWRST (_U_(0x1) << DAC_SYNCBUSY_SWRST_Pos) 267 #define DAC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (DAC_SYNCBUSY) Enable */ 268 #define DAC_SYNCBUSY_ENABLE (_U_(0x1) << DAC_SYNCBUSY_ENABLE_Pos) 269 #define DAC_SYNCBUSY_DATA_Pos 2 /**< \brief (DAC_SYNCBUSY) Data */ 270 #define DAC_SYNCBUSY_DATA (_U_(0x1) << DAC_SYNCBUSY_DATA_Pos) 271 #define DAC_SYNCBUSY_DATABUF_Pos 3 /**< \brief (DAC_SYNCBUSY) Data Buffer */ 272 #define DAC_SYNCBUSY_DATABUF (_U_(0x1) << DAC_SYNCBUSY_DATABUF_Pos) 273 #define DAC_SYNCBUSY_MASK _U_(0x0000000F) /**< \brief (DAC_SYNCBUSY) MASK Register */ 274 275 /* -------- DAC_DBGCTRL : (DAC Offset: 0x14) (R/W 8) Debug Control -------- */ 276 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 277 typedef union { 278 struct { 279 uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ 280 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 281 } bit; /*!< Structure used for bit access */ 282 uint8_t reg; /*!< Type used for register access */ 283 } DAC_DBGCTRL_Type; 284 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 285 286 #define DAC_DBGCTRL_OFFSET 0x14 /**< \brief (DAC_DBGCTRL offset) Debug Control */ 287 #define DAC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_DBGCTRL reset_value) Debug Control */ 288 289 #define DAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DAC_DBGCTRL) Debug Run */ 290 #define DAC_DBGCTRL_DBGRUN (_U_(0x1) << DAC_DBGCTRL_DBGRUN_Pos) 291 #define DAC_DBGCTRL_MASK _U_(0x01) /**< \brief (DAC_DBGCTRL) MASK Register */ 292 293 /** \brief DAC hardware registers */ 294 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 295 typedef struct { 296 __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ 297 __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 (R/W 8) Control B */ 298 __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 8) Event Control */ 299 RoReg8 Reserved1[0x1]; 300 __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ 301 __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ 302 __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ 303 __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x07 (R/ 8) Status */ 304 __O DAC_DATA_Type DATA; /**< \brief Offset: 0x08 ( /W 16) Data */ 305 RoReg8 Reserved2[0x2]; 306 __O DAC_DATABUF_Type DATABUF; /**< \brief Offset: 0x0C ( /W 16) Data Buffer */ 307 RoReg8 Reserved3[0x2]; 308 __I DAC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Busy */ 309 __IO DAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x14 (R/W 8) Debug Control */ 310 } Dac; 311 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 312 313 /*@}*/ 314 315 #endif /* _SAMC21_DAC_COMPONENT_ */ 316
