1 /** 2 * \file 3 * 4 * \brief Instance description for MCLK 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMC20_MCLK_INSTANCE_ 31 #define _SAMC20_MCLK_INSTANCE_ 32 33 /* ========== Register definition for MCLK peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_MCLK_INTENCLR (0x40000801) /**< \brief (MCLK) Interrupt Enable Clear */ 36 #define REG_MCLK_INTENSET (0x40000802) /**< \brief (MCLK) Interrupt Enable Set */ 37 #define REG_MCLK_INTFLAG (0x40000803) /**< \brief (MCLK) Interrupt Flag Status and Clear */ 38 #define REG_MCLK_CPUDIV (0x40000804) /**< \brief (MCLK) CPU Clock Division */ 39 #define REG_MCLK_AHBMASK (0x40000810) /**< \brief (MCLK) AHB Mask */ 40 #define REG_MCLK_APBAMASK (0x40000814) /**< \brief (MCLK) APBA Mask */ 41 #define REG_MCLK_APBBMASK (0x40000818) /**< \brief (MCLK) APBB Mask */ 42 #define REG_MCLK_APBCMASK (0x4000081C) /**< \brief (MCLK) APBC Mask */ 43 #define REG_MCLK_APBDMASK (0x40000820) /**< \brief (MCLK) APBD Mask */ 44 #else 45 #define REG_MCLK_INTENCLR (*(RwReg8 *)0x40000801UL) /**< \brief (MCLK) Interrupt Enable Clear */ 46 #define REG_MCLK_INTENSET (*(RwReg8 *)0x40000802UL) /**< \brief (MCLK) Interrupt Enable Set */ 47 #define REG_MCLK_INTFLAG (*(RwReg8 *)0x40000803UL) /**< \brief (MCLK) Interrupt Flag Status and Clear */ 48 #define REG_MCLK_CPUDIV (*(RwReg8 *)0x40000804UL) /**< \brief (MCLK) CPU Clock Division */ 49 #define REG_MCLK_AHBMASK (*(RwReg *)0x40000810UL) /**< \brief (MCLK) AHB Mask */ 50 #define REG_MCLK_APBAMASK (*(RwReg *)0x40000814UL) /**< \brief (MCLK) APBA Mask */ 51 #define REG_MCLK_APBBMASK (*(RwReg *)0x40000818UL) /**< \brief (MCLK) APBB Mask */ 52 #define REG_MCLK_APBCMASK (*(RwReg *)0x4000081CUL) /**< \brief (MCLK) APBC Mask */ 53 #define REG_MCLK_APBDMASK (*(RwReg *)0x40000820UL) /**< \brief (MCLK) APBD Mask */ 54 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 55 56 /* ========== Instance parameters for MCLK peripheral ========== */ 57 #define MCLK_CTRLA_MCSEL_GCLK 1 58 #define MCLK_CTRLA_MCSEL_OSC8M 0 59 #define MCLK_MCLK_CLK_APB_NUM 4 60 #define MCLK_SYSTEM_CLOCK 4000000 // System Clock Frequency at Reset 61 62 #endif /* _SAMC20_MCLK_INSTANCE_ */ 63
