1 /** 2 * \file 3 * 4 * \brief Component description for SUPC 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMC20_SUPC_COMPONENT_ 31 #define _SAMC20_SUPC_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR SUPC */ 35 /* ========================================================================== */ 36 /** \addtogroup SAMC20_SUPC Supply Controller */ 37 /*@{*/ 38 39 #define SUPC_U2117 40 #define REV_SUPC 0x220 41 42 /* -------- SUPC_INTENCLR : (SUPC Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint32_t BODVDDRDY:1; /*!< bit: 0 BODVDD Ready */ 47 uint32_t BODVDDDET:1; /*!< bit: 1 BODVDD Detection */ 48 uint32_t BVDDSRDY:1; /*!< bit: 2 BODVDD Synchronization Ready */ 49 uint32_t BODCORERDY:1; /*!< bit: 3 BODCORE Ready */ 50 uint32_t BODCOREDET:1; /*!< bit: 4 BODCORE Detection */ 51 uint32_t BCORESRDY:1; /*!< bit: 5 BODCORE Synchronization Ready */ 52 uint32_t VREG33RDY:1; /*!< bit: 6 VREG33 Ready */ 53 uint32_t :25; /*!< bit: 7..31 Reserved */ 54 } bit; /*!< Structure used for bit access */ 55 uint32_t reg; /*!< Type used for register access */ 56 } SUPC_INTENCLR_Type; 57 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 58 59 #define SUPC_INTENCLR_OFFSET 0x00 /**< \brief (SUPC_INTENCLR offset) Interrupt Enable Clear */ 60 #define SUPC_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_INTENCLR reset_value) Interrupt Enable Clear */ 61 62 #define SUPC_INTENCLR_BODVDDRDY_Pos 0 /**< \brief (SUPC_INTENCLR) BODVDD Ready */ 63 #define SUPC_INTENCLR_BODVDDRDY (_U_(0x1) << SUPC_INTENCLR_BODVDDRDY_Pos) 64 #define SUPC_INTENCLR_BODVDDDET_Pos 1 /**< \brief (SUPC_INTENCLR) BODVDD Detection */ 65 #define SUPC_INTENCLR_BODVDDDET (_U_(0x1) << SUPC_INTENCLR_BODVDDDET_Pos) 66 #define SUPC_INTENCLR_BVDDSRDY_Pos 2 /**< \brief (SUPC_INTENCLR) BODVDD Synchronization Ready */ 67 #define SUPC_INTENCLR_BVDDSRDY (_U_(0x1) << SUPC_INTENCLR_BVDDSRDY_Pos) 68 #define SUPC_INTENCLR_BODCORERDY_Pos 3 /**< \brief (SUPC_INTENCLR) BODCORE Ready */ 69 #define SUPC_INTENCLR_BODCORERDY (_U_(0x1) << SUPC_INTENCLR_BODCORERDY_Pos) 70 #define SUPC_INTENCLR_BODCOREDET_Pos 4 /**< \brief (SUPC_INTENCLR) BODCORE Detection */ 71 #define SUPC_INTENCLR_BODCOREDET (_U_(0x1) << SUPC_INTENCLR_BODCOREDET_Pos) 72 #define SUPC_INTENCLR_BCORESRDY_Pos 5 /**< \brief (SUPC_INTENCLR) BODCORE Synchronization Ready */ 73 #define SUPC_INTENCLR_BCORESRDY (_U_(0x1) << SUPC_INTENCLR_BCORESRDY_Pos) 74 #define SUPC_INTENCLR_VREG33RDY_Pos 6 /**< \brief (SUPC_INTENCLR) VREG33 Ready */ 75 #define SUPC_INTENCLR_VREG33RDY (_U_(0x1) << SUPC_INTENCLR_VREG33RDY_Pos) 76 #define SUPC_INTENCLR_MASK _U_(0x0000007F) /**< \brief (SUPC_INTENCLR) MASK Register */ 77 78 /* -------- SUPC_INTENSET : (SUPC Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */ 79 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 80 typedef union { 81 struct { 82 uint32_t BODVDDRDY:1; /*!< bit: 0 BODVDD Ready */ 83 uint32_t BODVDDDET:1; /*!< bit: 1 BODVDD Detection */ 84 uint32_t BVDDSRDY:1; /*!< bit: 2 BODVDD Synchronization Ready */ 85 uint32_t BODCORERDY:1; /*!< bit: 3 BODCORE Ready */ 86 uint32_t BODCOREDET:1; /*!< bit: 4 BODCORE Detection */ 87 uint32_t BCORESRDY:1; /*!< bit: 5 BODCORE Synchronization Ready */ 88 uint32_t VREG33RDY:1; /*!< bit: 6 VREG33 Ready */ 89 uint32_t :25; /*!< bit: 7..31 Reserved */ 90 } bit; /*!< Structure used for bit access */ 91 uint32_t reg; /*!< Type used for register access */ 92 } SUPC_INTENSET_Type; 93 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 94 95 #define SUPC_INTENSET_OFFSET 0x04 /**< \brief (SUPC_INTENSET offset) Interrupt Enable Set */ 96 #define SUPC_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_INTENSET reset_value) Interrupt Enable Set */ 97 98 #define SUPC_INTENSET_BODVDDRDY_Pos 0 /**< \brief (SUPC_INTENSET) BODVDD Ready */ 99 #define SUPC_INTENSET_BODVDDRDY (_U_(0x1) << SUPC_INTENSET_BODVDDRDY_Pos) 100 #define SUPC_INTENSET_BODVDDDET_Pos 1 /**< \brief (SUPC_INTENSET) BODVDD Detection */ 101 #define SUPC_INTENSET_BODVDDDET (_U_(0x1) << SUPC_INTENSET_BODVDDDET_Pos) 102 #define SUPC_INTENSET_BVDDSRDY_Pos 2 /**< \brief (SUPC_INTENSET) BODVDD Synchronization Ready */ 103 #define SUPC_INTENSET_BVDDSRDY (_U_(0x1) << SUPC_INTENSET_BVDDSRDY_Pos) 104 #define SUPC_INTENSET_BODCORERDY_Pos 3 /**< \brief (SUPC_INTENSET) BODCORE Ready */ 105 #define SUPC_INTENSET_BODCORERDY (_U_(0x1) << SUPC_INTENSET_BODCORERDY_Pos) 106 #define SUPC_INTENSET_BODCOREDET_Pos 4 /**< \brief (SUPC_INTENSET) BODCORE Detection */ 107 #define SUPC_INTENSET_BODCOREDET (_U_(0x1) << SUPC_INTENSET_BODCOREDET_Pos) 108 #define SUPC_INTENSET_BCORESRDY_Pos 5 /**< \brief (SUPC_INTENSET) BODCORE Synchronization Ready */ 109 #define SUPC_INTENSET_BCORESRDY (_U_(0x1) << SUPC_INTENSET_BCORESRDY_Pos) 110 #define SUPC_INTENSET_VREG33RDY_Pos 6 /**< \brief (SUPC_INTENSET) VREG33 Ready */ 111 #define SUPC_INTENSET_VREG33RDY (_U_(0x1) << SUPC_INTENSET_VREG33RDY_Pos) 112 #define SUPC_INTENSET_MASK _U_(0x0000007F) /**< \brief (SUPC_INTENSET) MASK Register */ 113 114 /* -------- SUPC_INTFLAG : (SUPC Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */ 115 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 116 typedef union { // __I to avoid read-modify-write on write-to-clear register 117 struct { 118 __I uint32_t BODVDDRDY:1; /*!< bit: 0 BODVDD Ready */ 119 __I uint32_t BODVDDDET:1; /*!< bit: 1 BODVDD Detection */ 120 __I uint32_t BVDDSRDY:1; /*!< bit: 2 BODVDD Synchronization Ready */ 121 __I uint32_t BODCORERDY:1; /*!< bit: 3 BODCORE Ready */ 122 __I uint32_t BODCOREDET:1; /*!< bit: 4 BODCORE Detection */ 123 __I uint32_t BCORESRDY:1; /*!< bit: 5 BODCORE Synchronization Ready */ 124 __I uint32_t VREG33RDY:1; /*!< bit: 6 VREG33 Ready */ 125 __I uint32_t Reserved1:25; /*!< bit: 7..31 Reserved */ 126 } bit; /*!< Structure used for bit access */ 127 uint32_t reg; /*!< Type used for register access */ 128 } SUPC_INTFLAG_Type; 129 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 130 131 #define SUPC_INTFLAG_OFFSET 0x08 /**< \brief (SUPC_INTFLAG offset) Interrupt Flag Status and Clear */ 132 #define SUPC_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_INTFLAG reset_value) Interrupt Flag Status and Clear */ 133 134 #define SUPC_INTFLAG_BODVDDRDY_Pos 0 /**< \brief (SUPC_INTFLAG) BODVDD Ready */ 135 #define SUPC_INTFLAG_BODVDDRDY (_U_(0x1) << SUPC_INTFLAG_BODVDDRDY_Pos) 136 #define SUPC_INTFLAG_BODVDDDET_Pos 1 /**< \brief (SUPC_INTFLAG) BODVDD Detection */ 137 #define SUPC_INTFLAG_BODVDDDET (_U_(0x1) << SUPC_INTFLAG_BODVDDDET_Pos) 138 #define SUPC_INTFLAG_BVDDSRDY_Pos 2 /**< \brief (SUPC_INTFLAG) BODVDD Synchronization Ready */ 139 #define SUPC_INTFLAG_BVDDSRDY (_U_(0x1) << SUPC_INTFLAG_BVDDSRDY_Pos) 140 #define SUPC_INTFLAG_BODCORERDY_Pos 3 /**< \brief (SUPC_INTFLAG) BODCORE Ready */ 141 #define SUPC_INTFLAG_BODCORERDY (_U_(0x1) << SUPC_INTFLAG_BODCORERDY_Pos) 142 #define SUPC_INTFLAG_BODCOREDET_Pos 4 /**< \brief (SUPC_INTFLAG) BODCORE Detection */ 143 #define SUPC_INTFLAG_BODCOREDET (_U_(0x1) << SUPC_INTFLAG_BODCOREDET_Pos) 144 #define SUPC_INTFLAG_BCORESRDY_Pos 5 /**< \brief (SUPC_INTFLAG) BODCORE Synchronization Ready */ 145 #define SUPC_INTFLAG_BCORESRDY (_U_(0x1) << SUPC_INTFLAG_BCORESRDY_Pos) 146 #define SUPC_INTFLAG_VREG33RDY_Pos 6 /**< \brief (SUPC_INTFLAG) VREG33 Ready */ 147 #define SUPC_INTFLAG_VREG33RDY (_U_(0x1) << SUPC_INTFLAG_VREG33RDY_Pos) 148 #define SUPC_INTFLAG_MASK _U_(0x0000007F) /**< \brief (SUPC_INTFLAG) MASK Register */ 149 150 /* -------- SUPC_STATUS : (SUPC Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */ 151 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 152 typedef union { 153 struct { 154 uint32_t BODVDDRDY:1; /*!< bit: 0 BODVDD Ready */ 155 uint32_t BODVDDDET:1; /*!< bit: 1 BODVDD Detection */ 156 uint32_t BVDDSRDY:1; /*!< bit: 2 BODVDD Synchronization Ready */ 157 uint32_t BODCORERDY:1; /*!< bit: 3 BODCORE Ready */ 158 uint32_t BODCOREDET:1; /*!< bit: 4 BODCORE Detection */ 159 uint32_t BCORESRDY:1; /*!< bit: 5 BODCORE Synchronization Ready */ 160 uint32_t VREG33RDY:1; /*!< bit: 6 VREG33 Ready */ 161 uint32_t :25; /*!< bit: 7..31 Reserved */ 162 } bit; /*!< Structure used for bit access */ 163 uint32_t reg; /*!< Type used for register access */ 164 } SUPC_STATUS_Type; 165 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 166 167 #define SUPC_STATUS_OFFSET 0x0C /**< \brief (SUPC_STATUS offset) Power and Clocks Status */ 168 #define SUPC_STATUS_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_STATUS reset_value) Power and Clocks Status */ 169 170 #define SUPC_STATUS_BODVDDRDY_Pos 0 /**< \brief (SUPC_STATUS) BODVDD Ready */ 171 #define SUPC_STATUS_BODVDDRDY (_U_(0x1) << SUPC_STATUS_BODVDDRDY_Pos) 172 #define SUPC_STATUS_BODVDDDET_Pos 1 /**< \brief (SUPC_STATUS) BODVDD Detection */ 173 #define SUPC_STATUS_BODVDDDET (_U_(0x1) << SUPC_STATUS_BODVDDDET_Pos) 174 #define SUPC_STATUS_BVDDSRDY_Pos 2 /**< \brief (SUPC_STATUS) BODVDD Synchronization Ready */ 175 #define SUPC_STATUS_BVDDSRDY (_U_(0x1) << SUPC_STATUS_BVDDSRDY_Pos) 176 #define SUPC_STATUS_BODCORERDY_Pos 3 /**< \brief (SUPC_STATUS) BODCORE Ready */ 177 #define SUPC_STATUS_BODCORERDY (_U_(0x1) << SUPC_STATUS_BODCORERDY_Pos) 178 #define SUPC_STATUS_BODCOREDET_Pos 4 /**< \brief (SUPC_STATUS) BODCORE Detection */ 179 #define SUPC_STATUS_BODCOREDET (_U_(0x1) << SUPC_STATUS_BODCOREDET_Pos) 180 #define SUPC_STATUS_BCORESRDY_Pos 5 /**< \brief (SUPC_STATUS) BODCORE Synchronization Ready */ 181 #define SUPC_STATUS_BCORESRDY (_U_(0x1) << SUPC_STATUS_BCORESRDY_Pos) 182 #define SUPC_STATUS_VREG33RDY_Pos 6 /**< \brief (SUPC_STATUS) VREG33 Ready */ 183 #define SUPC_STATUS_VREG33RDY (_U_(0x1) << SUPC_STATUS_VREG33RDY_Pos) 184 #define SUPC_STATUS_MASK _U_(0x0000007F) /**< \brief (SUPC_STATUS) MASK Register */ 185 186 /* -------- SUPC_BODVDD : (SUPC Offset: 0x10) (R/W 32) BODVDD Control -------- */ 187 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 188 typedef union { 189 struct { 190 uint32_t :1; /*!< bit: 0 Reserved */ 191 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 192 uint32_t HYST:1; /*!< bit: 2 Hysteresis Enable */ 193 uint32_t ACTION:2; /*!< bit: 3.. 4 Action when Threshold Crossed */ 194 uint32_t STDBYCFG:1; /*!< bit: 5 Configuration in Standby mode */ 195 uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ 196 uint32_t :1; /*!< bit: 7 Reserved */ 197 uint32_t ACTCFG:1; /*!< bit: 8 Configuration in Active mode */ 198 uint32_t :3; /*!< bit: 9..11 Reserved */ 199 uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */ 200 uint32_t LEVEL:6; /*!< bit: 16..21 Threshold Level for VDD */ 201 uint32_t :10; /*!< bit: 22..31 Reserved */ 202 } bit; /*!< Structure used for bit access */ 203 uint32_t reg; /*!< Type used for register access */ 204 } SUPC_BODVDD_Type; 205 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 206 207 #define SUPC_BODVDD_OFFSET 0x10 /**< \brief (SUPC_BODVDD offset) BODVDD Control */ 208 #define SUPC_BODVDD_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_BODVDD reset_value) BODVDD Control */ 209 210 #define SUPC_BODVDD_ENABLE_Pos 1 /**< \brief (SUPC_BODVDD) Enable */ 211 #define SUPC_BODVDD_ENABLE (_U_(0x1) << SUPC_BODVDD_ENABLE_Pos) 212 #define SUPC_BODVDD_HYST_Pos 2 /**< \brief (SUPC_BODVDD) Hysteresis Enable */ 213 #define SUPC_BODVDD_HYST (_U_(0x1) << SUPC_BODVDD_HYST_Pos) 214 #define SUPC_BODVDD_ACTION_Pos 3 /**< \brief (SUPC_BODVDD) Action when Threshold Crossed */ 215 #define SUPC_BODVDD_ACTION_Msk (_U_(0x3) << SUPC_BODVDD_ACTION_Pos) 216 #define SUPC_BODVDD_ACTION(value) (SUPC_BODVDD_ACTION_Msk & ((value) << SUPC_BODVDD_ACTION_Pos)) 217 #define SUPC_BODVDD_ACTION_NONE_Val _U_(0x0) /**< \brief (SUPC_BODVDD) No action */ 218 #define SUPC_BODVDD_ACTION_RESET_Val _U_(0x1) /**< \brief (SUPC_BODVDD) The BOD33 generates a reset */ 219 #define SUPC_BODVDD_ACTION_INT_Val _U_(0x2) /**< \brief (SUPC_BODVDD) The BOD33 generates an interrupt */ 220 #define SUPC_BODVDD_ACTION_NONE (SUPC_BODVDD_ACTION_NONE_Val << SUPC_BODVDD_ACTION_Pos) 221 #define SUPC_BODVDD_ACTION_RESET (SUPC_BODVDD_ACTION_RESET_Val << SUPC_BODVDD_ACTION_Pos) 222 #define SUPC_BODVDD_ACTION_INT (SUPC_BODVDD_ACTION_INT_Val << SUPC_BODVDD_ACTION_Pos) 223 #define SUPC_BODVDD_STDBYCFG_Pos 5 /**< \brief (SUPC_BODVDD) Configuration in Standby mode */ 224 #define SUPC_BODVDD_STDBYCFG (_U_(0x1) << SUPC_BODVDD_STDBYCFG_Pos) 225 #define SUPC_BODVDD_RUNSTDBY_Pos 6 /**< \brief (SUPC_BODVDD) Run during Standby */ 226 #define SUPC_BODVDD_RUNSTDBY (_U_(0x1) << SUPC_BODVDD_RUNSTDBY_Pos) 227 #define SUPC_BODVDD_ACTCFG_Pos 8 /**< \brief (SUPC_BODVDD) Configuration in Active mode */ 228 #define SUPC_BODVDD_ACTCFG (_U_(0x1) << SUPC_BODVDD_ACTCFG_Pos) 229 #define SUPC_BODVDD_PSEL_Pos 12 /**< \brief (SUPC_BODVDD) Prescaler Select */ 230 #define SUPC_BODVDD_PSEL_Msk (_U_(0xF) << SUPC_BODVDD_PSEL_Pos) 231 #define SUPC_BODVDD_PSEL(value) (SUPC_BODVDD_PSEL_Msk & ((value) << SUPC_BODVDD_PSEL_Pos)) 232 #define SUPC_BODVDD_PSEL_DIV2_Val _U_(0x0) /**< \brief (SUPC_BODVDD) Divide clock by 2 */ 233 #define SUPC_BODVDD_PSEL_DIV4_Val _U_(0x1) /**< \brief (SUPC_BODVDD) Divide clock by 4 */ 234 #define SUPC_BODVDD_PSEL_DIV8_Val _U_(0x2) /**< \brief (SUPC_BODVDD) Divide clock by 8 */ 235 #define SUPC_BODVDD_PSEL_DIV16_Val _U_(0x3) /**< \brief (SUPC_BODVDD) Divide clock by 16 */ 236 #define SUPC_BODVDD_PSEL_DIV32_Val _U_(0x4) /**< \brief (SUPC_BODVDD) Divide clock by 32 */ 237 #define SUPC_BODVDD_PSEL_DIV64_Val _U_(0x5) /**< \brief (SUPC_BODVDD) Divide clock by 64 */ 238 #define SUPC_BODVDD_PSEL_DIV128_Val _U_(0x6) /**< \brief (SUPC_BODVDD) Divide clock by 128 */ 239 #define SUPC_BODVDD_PSEL_DIV256_Val _U_(0x7) /**< \brief (SUPC_BODVDD) Divide clock by 256 */ 240 #define SUPC_BODVDD_PSEL_DIV512_Val _U_(0x8) /**< \brief (SUPC_BODVDD) Divide clock by 512 */ 241 #define SUPC_BODVDD_PSEL_DIV1024_Val _U_(0x9) /**< \brief (SUPC_BODVDD) Divide clock by 1024 */ 242 #define SUPC_BODVDD_PSEL_DIV2048_Val _U_(0xA) /**< \brief (SUPC_BODVDD) Divide clock by 2048 */ 243 #define SUPC_BODVDD_PSEL_DIV4096_Val _U_(0xB) /**< \brief (SUPC_BODVDD) Divide clock by 4096 */ 244 #define SUPC_BODVDD_PSEL_DIV8192_Val _U_(0xC) /**< \brief (SUPC_BODVDD) Divide clock by 8192 */ 245 #define SUPC_BODVDD_PSEL_DIV16384_Val _U_(0xD) /**< \brief (SUPC_BODVDD) Divide clock by 16384 */ 246 #define SUPC_BODVDD_PSEL_DIV32768_Val _U_(0xE) /**< \brief (SUPC_BODVDD) Divide clock by 32768 */ 247 #define SUPC_BODVDD_PSEL_DIV65536_Val _U_(0xF) /**< \brief (SUPC_BODVDD) Divide clock by 65536 */ 248 #define SUPC_BODVDD_PSEL_DIV2 (SUPC_BODVDD_PSEL_DIV2_Val << SUPC_BODVDD_PSEL_Pos) 249 #define SUPC_BODVDD_PSEL_DIV4 (SUPC_BODVDD_PSEL_DIV4_Val << SUPC_BODVDD_PSEL_Pos) 250 #define SUPC_BODVDD_PSEL_DIV8 (SUPC_BODVDD_PSEL_DIV8_Val << SUPC_BODVDD_PSEL_Pos) 251 #define SUPC_BODVDD_PSEL_DIV16 (SUPC_BODVDD_PSEL_DIV16_Val << SUPC_BODVDD_PSEL_Pos) 252 #define SUPC_BODVDD_PSEL_DIV32 (SUPC_BODVDD_PSEL_DIV32_Val << SUPC_BODVDD_PSEL_Pos) 253 #define SUPC_BODVDD_PSEL_DIV64 (SUPC_BODVDD_PSEL_DIV64_Val << SUPC_BODVDD_PSEL_Pos) 254 #define SUPC_BODVDD_PSEL_DIV128 (SUPC_BODVDD_PSEL_DIV128_Val << SUPC_BODVDD_PSEL_Pos) 255 #define SUPC_BODVDD_PSEL_DIV256 (SUPC_BODVDD_PSEL_DIV256_Val << SUPC_BODVDD_PSEL_Pos) 256 #define SUPC_BODVDD_PSEL_DIV512 (SUPC_BODVDD_PSEL_DIV512_Val << SUPC_BODVDD_PSEL_Pos) 257 #define SUPC_BODVDD_PSEL_DIV1024 (SUPC_BODVDD_PSEL_DIV1024_Val << SUPC_BODVDD_PSEL_Pos) 258 #define SUPC_BODVDD_PSEL_DIV2048 (SUPC_BODVDD_PSEL_DIV2048_Val << SUPC_BODVDD_PSEL_Pos) 259 #define SUPC_BODVDD_PSEL_DIV4096 (SUPC_BODVDD_PSEL_DIV4096_Val << SUPC_BODVDD_PSEL_Pos) 260 #define SUPC_BODVDD_PSEL_DIV8192 (SUPC_BODVDD_PSEL_DIV8192_Val << SUPC_BODVDD_PSEL_Pos) 261 #define SUPC_BODVDD_PSEL_DIV16384 (SUPC_BODVDD_PSEL_DIV16384_Val << SUPC_BODVDD_PSEL_Pos) 262 #define SUPC_BODVDD_PSEL_DIV32768 (SUPC_BODVDD_PSEL_DIV32768_Val << SUPC_BODVDD_PSEL_Pos) 263 #define SUPC_BODVDD_PSEL_DIV65536 (SUPC_BODVDD_PSEL_DIV65536_Val << SUPC_BODVDD_PSEL_Pos) 264 #define SUPC_BODVDD_LEVEL_Pos 16 /**< \brief (SUPC_BODVDD) Threshold Level for VDD */ 265 #define SUPC_BODVDD_LEVEL_Msk (_U_(0x3F) << SUPC_BODVDD_LEVEL_Pos) 266 #define SUPC_BODVDD_LEVEL(value) (SUPC_BODVDD_LEVEL_Msk & ((value) << SUPC_BODVDD_LEVEL_Pos)) 267 #define SUPC_BODVDD_MASK _U_(0x003FF17E) /**< \brief (SUPC_BODVDD) MASK Register */ 268 269 /* -------- SUPC_BODCORE : (SUPC Offset: 0x14) (R/W 32) BODCORE Control -------- */ 270 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 271 typedef union { 272 struct { 273 uint32_t :1; /*!< bit: 0 Reserved */ 274 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 275 uint32_t HYST:1; /*!< bit: 2 Hysteresis Enable */ 276 uint32_t ACTION:2; /*!< bit: 3.. 4 Action when Threshold Crossed */ 277 uint32_t STDBYCFG:1; /*!< bit: 5 Configuration in Standby mode */ 278 uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ 279 uint32_t :1; /*!< bit: 7 Reserved */ 280 uint32_t ACTCFG:1; /*!< bit: 8 Configuration in Active mode */ 281 uint32_t :3; /*!< bit: 9..11 Reserved */ 282 uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */ 283 uint32_t LEVEL:6; /*!< bit: 16..21 Threshold Level */ 284 uint32_t :10; /*!< bit: 22..31 Reserved */ 285 } bit; /*!< Structure used for bit access */ 286 uint32_t reg; /*!< Type used for register access */ 287 } SUPC_BODCORE_Type; 288 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 289 290 #define SUPC_BODCORE_OFFSET 0x14 /**< \brief (SUPC_BODCORE offset) BODCORE Control */ 291 #define SUPC_BODCORE_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_BODCORE reset_value) BODCORE Control */ 292 293 #define SUPC_BODCORE_ENABLE_Pos 1 /**< \brief (SUPC_BODCORE) Enable */ 294 #define SUPC_BODCORE_ENABLE (_U_(0x1) << SUPC_BODCORE_ENABLE_Pos) 295 #define SUPC_BODCORE_HYST_Pos 2 /**< \brief (SUPC_BODCORE) Hysteresis Enable */ 296 #define SUPC_BODCORE_HYST (_U_(0x1) << SUPC_BODCORE_HYST_Pos) 297 #define SUPC_BODCORE_ACTION_Pos 3 /**< \brief (SUPC_BODCORE) Action when Threshold Crossed */ 298 #define SUPC_BODCORE_ACTION_Msk (_U_(0x3) << SUPC_BODCORE_ACTION_Pos) 299 #define SUPC_BODCORE_ACTION(value) (SUPC_BODCORE_ACTION_Msk & ((value) << SUPC_BODCORE_ACTION_Pos)) 300 #define SUPC_BODCORE_ACTION_NONE_Val _U_(0x0) /**< \brief (SUPC_BODCORE) No action */ 301 #define SUPC_BODCORE_ACTION_RESET_Val _U_(0x1) /**< \brief (SUPC_BODCORE) The BOD12 generates a reset */ 302 #define SUPC_BODCORE_ACTION_INT_Val _U_(0x2) /**< \brief (SUPC_BODCORE) The BOD12 generates an interrupt */ 303 #define SUPC_BODCORE_ACTION_NONE (SUPC_BODCORE_ACTION_NONE_Val << SUPC_BODCORE_ACTION_Pos) 304 #define SUPC_BODCORE_ACTION_RESET (SUPC_BODCORE_ACTION_RESET_Val << SUPC_BODCORE_ACTION_Pos) 305 #define SUPC_BODCORE_ACTION_INT (SUPC_BODCORE_ACTION_INT_Val << SUPC_BODCORE_ACTION_Pos) 306 #define SUPC_BODCORE_STDBYCFG_Pos 5 /**< \brief (SUPC_BODCORE) Configuration in Standby mode */ 307 #define SUPC_BODCORE_STDBYCFG (_U_(0x1) << SUPC_BODCORE_STDBYCFG_Pos) 308 #define SUPC_BODCORE_RUNSTDBY_Pos 6 /**< \brief (SUPC_BODCORE) Run during Standby */ 309 #define SUPC_BODCORE_RUNSTDBY (_U_(0x1) << SUPC_BODCORE_RUNSTDBY_Pos) 310 #define SUPC_BODCORE_ACTCFG_Pos 8 /**< \brief (SUPC_BODCORE) Configuration in Active mode */ 311 #define SUPC_BODCORE_ACTCFG (_U_(0x1) << SUPC_BODCORE_ACTCFG_Pos) 312 #define SUPC_BODCORE_PSEL_Pos 12 /**< \brief (SUPC_BODCORE) Prescaler Select */ 313 #define SUPC_BODCORE_PSEL_Msk (_U_(0xF) << SUPC_BODCORE_PSEL_Pos) 314 #define SUPC_BODCORE_PSEL(value) (SUPC_BODCORE_PSEL_Msk & ((value) << SUPC_BODCORE_PSEL_Pos)) 315 #define SUPC_BODCORE_PSEL_DIV2_Val _U_(0x0) /**< \brief (SUPC_BODCORE) Divide clock by 2 */ 316 #define SUPC_BODCORE_PSEL_DIV4_Val _U_(0x1) /**< \brief (SUPC_BODCORE) Divide clock by 4 */ 317 #define SUPC_BODCORE_PSEL_DIV8_Val _U_(0x2) /**< \brief (SUPC_BODCORE) Divide clock by 8 */ 318 #define SUPC_BODCORE_PSEL_DIV16_Val _U_(0x3) /**< \brief (SUPC_BODCORE) Divide clock by 16 */ 319 #define SUPC_BODCORE_PSEL_DIV32_Val _U_(0x4) /**< \brief (SUPC_BODCORE) Divide clock by 32 */ 320 #define SUPC_BODCORE_PSEL_DIV64_Val _U_(0x5) /**< \brief (SUPC_BODCORE) Divide clock by 64 */ 321 #define SUPC_BODCORE_PSEL_DIV128_Val _U_(0x6) /**< \brief (SUPC_BODCORE) Divide clock by 128 */ 322 #define SUPC_BODCORE_PSEL_DIV256_Val _U_(0x7) /**< \brief (SUPC_BODCORE) Divide clock by 256 */ 323 #define SUPC_BODCORE_PSEL_DIV512_Val _U_(0x8) /**< \brief (SUPC_BODCORE) Divide clock by 512 */ 324 #define SUPC_BODCORE_PSEL_DIV1024_Val _U_(0x9) /**< \brief (SUPC_BODCORE) Divide clock by 1024 */ 325 #define SUPC_BODCORE_PSEL_DIV2048_Val _U_(0xA) /**< \brief (SUPC_BODCORE) Divide clock by 2048 */ 326 #define SUPC_BODCORE_PSEL_DIV4096_Val _U_(0xB) /**< \brief (SUPC_BODCORE) Divide clock by 4096 */ 327 #define SUPC_BODCORE_PSEL_DIV8192_Val _U_(0xC) /**< \brief (SUPC_BODCORE) Divide clock by 8192 */ 328 #define SUPC_BODCORE_PSEL_DIV16384_Val _U_(0xD) /**< \brief (SUPC_BODCORE) Divide clock by 16384 */ 329 #define SUPC_BODCORE_PSEL_DIV32768_Val _U_(0xE) /**< \brief (SUPC_BODCORE) Divide clock by 32768 */ 330 #define SUPC_BODCORE_PSEL_DIV65536_Val _U_(0xF) /**< \brief (SUPC_BODCORE) Divide clock by 65536 */ 331 #define SUPC_BODCORE_PSEL_DIV2 (SUPC_BODCORE_PSEL_DIV2_Val << SUPC_BODCORE_PSEL_Pos) 332 #define SUPC_BODCORE_PSEL_DIV4 (SUPC_BODCORE_PSEL_DIV4_Val << SUPC_BODCORE_PSEL_Pos) 333 #define SUPC_BODCORE_PSEL_DIV8 (SUPC_BODCORE_PSEL_DIV8_Val << SUPC_BODCORE_PSEL_Pos) 334 #define SUPC_BODCORE_PSEL_DIV16 (SUPC_BODCORE_PSEL_DIV16_Val << SUPC_BODCORE_PSEL_Pos) 335 #define SUPC_BODCORE_PSEL_DIV32 (SUPC_BODCORE_PSEL_DIV32_Val << SUPC_BODCORE_PSEL_Pos) 336 #define SUPC_BODCORE_PSEL_DIV64 (SUPC_BODCORE_PSEL_DIV64_Val << SUPC_BODCORE_PSEL_Pos) 337 #define SUPC_BODCORE_PSEL_DIV128 (SUPC_BODCORE_PSEL_DIV128_Val << SUPC_BODCORE_PSEL_Pos) 338 #define SUPC_BODCORE_PSEL_DIV256 (SUPC_BODCORE_PSEL_DIV256_Val << SUPC_BODCORE_PSEL_Pos) 339 #define SUPC_BODCORE_PSEL_DIV512 (SUPC_BODCORE_PSEL_DIV512_Val << SUPC_BODCORE_PSEL_Pos) 340 #define SUPC_BODCORE_PSEL_DIV1024 (SUPC_BODCORE_PSEL_DIV1024_Val << SUPC_BODCORE_PSEL_Pos) 341 #define SUPC_BODCORE_PSEL_DIV2048 (SUPC_BODCORE_PSEL_DIV2048_Val << SUPC_BODCORE_PSEL_Pos) 342 #define SUPC_BODCORE_PSEL_DIV4096 (SUPC_BODCORE_PSEL_DIV4096_Val << SUPC_BODCORE_PSEL_Pos) 343 #define SUPC_BODCORE_PSEL_DIV8192 (SUPC_BODCORE_PSEL_DIV8192_Val << SUPC_BODCORE_PSEL_Pos) 344 #define SUPC_BODCORE_PSEL_DIV16384 (SUPC_BODCORE_PSEL_DIV16384_Val << SUPC_BODCORE_PSEL_Pos) 345 #define SUPC_BODCORE_PSEL_DIV32768 (SUPC_BODCORE_PSEL_DIV32768_Val << SUPC_BODCORE_PSEL_Pos) 346 #define SUPC_BODCORE_PSEL_DIV65536 (SUPC_BODCORE_PSEL_DIV65536_Val << SUPC_BODCORE_PSEL_Pos) 347 #define SUPC_BODCORE_LEVEL_Pos 16 /**< \brief (SUPC_BODCORE) Threshold Level */ 348 #define SUPC_BODCORE_LEVEL_Msk (_U_(0x3F) << SUPC_BODCORE_LEVEL_Pos) 349 #define SUPC_BODCORE_LEVEL(value) (SUPC_BODCORE_LEVEL_Msk & ((value) << SUPC_BODCORE_LEVEL_Pos)) 350 #define SUPC_BODCORE_MASK _U_(0x003FF17E) /**< \brief (SUPC_BODCORE) MASK Register */ 351 352 /* -------- SUPC_VREG : (SUPC Offset: 0x18) (R/W 32) VREG Control -------- */ 353 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 354 typedef union { 355 struct { 356 uint32_t :1; /*!< bit: 0 Reserved */ 357 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 358 uint32_t :4; /*!< bit: 2.. 5 Reserved */ 359 uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ 360 uint32_t :25; /*!< bit: 7..31 Reserved */ 361 } bit; /*!< Structure used for bit access */ 362 uint32_t reg; /*!< Type used for register access */ 363 } SUPC_VREG_Type; 364 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 365 366 #define SUPC_VREG_OFFSET 0x18 /**< \brief (SUPC_VREG offset) VREG Control */ 367 #define SUPC_VREG_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_VREG reset_value) VREG Control */ 368 369 #define SUPC_VREG_ENABLE_Pos 1 /**< \brief (SUPC_VREG) Enable */ 370 #define SUPC_VREG_ENABLE (_U_(0x1) << SUPC_VREG_ENABLE_Pos) 371 #define SUPC_VREG_RUNSTDBY_Pos 6 /**< \brief (SUPC_VREG) Run during Standby */ 372 #define SUPC_VREG_RUNSTDBY (_U_(0x1) << SUPC_VREG_RUNSTDBY_Pos) 373 #define SUPC_VREG_MASK _U_(0x00000042) /**< \brief (SUPC_VREG) MASK Register */ 374 375 /* -------- SUPC_VREF : (SUPC Offset: 0x1C) (R/W 32) VREF Control -------- */ 376 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 377 typedef union { 378 struct { 379 uint32_t :1; /*!< bit: 0 Reserved */ 380 uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Output Enable */ 381 uint32_t VREFOE:1; /*!< bit: 2 Voltage Reference Output Enable */ 382 uint32_t :3; /*!< bit: 3.. 5 Reserved */ 383 uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ 384 uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Contrl */ 385 uint32_t :8; /*!< bit: 8..15 Reserved */ 386 uint32_t SEL:4; /*!< bit: 16..19 Voltage Reference Selection */ 387 uint32_t :12; /*!< bit: 20..31 Reserved */ 388 } bit; /*!< Structure used for bit access */ 389 uint32_t reg; /*!< Type used for register access */ 390 } SUPC_VREF_Type; 391 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 392 393 #define SUPC_VREF_OFFSET 0x1C /**< \brief (SUPC_VREF offset) VREF Control */ 394 #define SUPC_VREF_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_VREF reset_value) VREF Control */ 395 396 #define SUPC_VREF_TSEN_Pos 1 /**< \brief (SUPC_VREF) Temperature Sensor Output Enable */ 397 #define SUPC_VREF_TSEN (_U_(0x1) << SUPC_VREF_TSEN_Pos) 398 #define SUPC_VREF_VREFOE_Pos 2 /**< \brief (SUPC_VREF) Voltage Reference Output Enable */ 399 #define SUPC_VREF_VREFOE (_U_(0x1) << SUPC_VREF_VREFOE_Pos) 400 #define SUPC_VREF_RUNSTDBY_Pos 6 /**< \brief (SUPC_VREF) Run during Standby */ 401 #define SUPC_VREF_RUNSTDBY (_U_(0x1) << SUPC_VREF_RUNSTDBY_Pos) 402 #define SUPC_VREF_ONDEMAND_Pos 7 /**< \brief (SUPC_VREF) On Demand Contrl */ 403 #define SUPC_VREF_ONDEMAND (_U_(0x1) << SUPC_VREF_ONDEMAND_Pos) 404 #define SUPC_VREF_SEL_Pos 16 /**< \brief (SUPC_VREF) Voltage Reference Selection */ 405 #define SUPC_VREF_SEL_Msk (_U_(0xF) << SUPC_VREF_SEL_Pos) 406 #define SUPC_VREF_SEL(value) (SUPC_VREF_SEL_Msk & ((value) << SUPC_VREF_SEL_Pos)) 407 #define SUPC_VREF_SEL_1V024_Val _U_(0x0) /**< \brief (SUPC_VREF) 1.024V voltage reference typical value */ 408 #define SUPC_VREF_SEL_2V048_Val _U_(0x2) /**< \brief (SUPC_VREF) 2.048V voltage reference typical value */ 409 #define SUPC_VREF_SEL_4V096_Val _U_(0x3) /**< \brief (SUPC_VREF) 4.096V voltage reference typical value */ 410 #define SUPC_VREF_SEL_1V024 (SUPC_VREF_SEL_1V024_Val << SUPC_VREF_SEL_Pos) 411 #define SUPC_VREF_SEL_2V048 (SUPC_VREF_SEL_2V048_Val << SUPC_VREF_SEL_Pos) 412 #define SUPC_VREF_SEL_4V096 (SUPC_VREF_SEL_4V096_Val << SUPC_VREF_SEL_Pos) 413 #define SUPC_VREF_MASK _U_(0x000F00C6) /**< \brief (SUPC_VREF) MASK Register */ 414 415 /* -------- SUPC_VREG33 : (SUPC Offset: 0x20) (R/W 32) VREG33 Control -------- */ 416 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 417 typedef union { 418 struct { 419 uint32_t :1; /*!< bit: 0 Reserved */ 420 uint32_t ENABLE:1; /*!< bit: 1 VREG33 Enable */ 421 uint32_t ENRDY:1; /*!< bit: 2 VREG33 Ready Enable */ 422 uint32_t BYPASS:1; /*!< bit: 3 VREG33 Bypass */ 423 uint32_t ISOEN:1; /*!< bit: 4 Isolation Enable */ 424 uint32_t :27; /*!< bit: 5..31 Reserved */ 425 } bit; /*!< Structure used for bit access */ 426 uint32_t reg; /*!< Type used for register access */ 427 } SUPC_VREG33_Type; 428 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 429 430 #define SUPC_VREG33_OFFSET 0x20 /**< \brief (SUPC_VREG33 offset) VREG33 Control */ 431 #define SUPC_VREG33_RESETVALUE _U_(0x00000010) /**< \brief (SUPC_VREG33 reset_value) VREG33 Control */ 432 433 #define SUPC_VREG33_ENABLE_Pos 1 /**< \brief (SUPC_VREG33) VREG33 Enable */ 434 #define SUPC_VREG33_ENABLE (_U_(0x1) << SUPC_VREG33_ENABLE_Pos) 435 #define SUPC_VREG33_ENRDY_Pos 2 /**< \brief (SUPC_VREG33) VREG33 Ready Enable */ 436 #define SUPC_VREG33_ENRDY (_U_(0x1) << SUPC_VREG33_ENRDY_Pos) 437 #define SUPC_VREG33_BYPASS_Pos 3 /**< \brief (SUPC_VREG33) VREG33 Bypass */ 438 #define SUPC_VREG33_BYPASS (_U_(0x1) << SUPC_VREG33_BYPASS_Pos) 439 #define SUPC_VREG33_ISOEN_Pos 4 /**< \brief (SUPC_VREG33) Isolation Enable */ 440 #define SUPC_VREG33_ISOEN (_U_(0x1) << SUPC_VREG33_ISOEN_Pos) 441 #define SUPC_VREG33_MASK _U_(0x0000001E) /**< \brief (SUPC_VREG33) MASK Register */ 442 443 /** \brief SUPC hardware registers */ 444 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 445 typedef struct { 446 __IO SUPC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */ 447 __IO SUPC_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */ 448 __IO SUPC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */ 449 __I SUPC_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */ 450 __IO SUPC_BODVDD_Type BODVDD; /**< \brief Offset: 0x10 (R/W 32) BODVDD Control */ 451 __IO SUPC_BODCORE_Type BODCORE; /**< \brief Offset: 0x14 (R/W 32) BODCORE Control */ 452 __IO SUPC_VREG_Type VREG; /**< \brief Offset: 0x18 (R/W 32) VREG Control */ 453 __IO SUPC_VREF_Type VREF; /**< \brief Offset: 0x1C (R/W 32) VREF Control */ 454 __IO SUPC_VREG33_Type VREG33; /**< \brief Offset: 0x20 (R/W 32) VREG33 Control */ 455 } Supc; 456 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 457 458 /*@}*/ 459 460 #endif /* _SAMC20_SUPC_COMPONENT_ */ 461
