1 /** 2 * \file 3 * 4 * \brief Component description for OSC32KCTRL 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMC20_OSC32KCTRL_COMPONENT_ 31 #define _SAMC20_OSC32KCTRL_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR OSC32KCTRL */ 35 /* ========================================================================== */ 36 /** \addtogroup SAMC20_OSC32KCTRL 32k Oscillators Control */ 37 /*@{*/ 38 39 #define OSC32KCTRL_U2246 40 #define REV_OSC32KCTRL 0x210 41 42 /* -------- OSC32KCTRL_INTENCLR : (OSC32KCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready Interrupt Enable */ 47 uint32_t OSC32KRDY:1; /*!< bit: 1 OSC32K Ready Interrupt Enable */ 48 uint32_t CLKFAIL:1; /*!< bit: 2 XOSC32K Clock Failure Detector Interrupt Enable */ 49 uint32_t :29; /*!< bit: 3..31 Reserved */ 50 } bit; /*!< Structure used for bit access */ 51 uint32_t reg; /*!< Type used for register access */ 52 } OSC32KCTRL_INTENCLR_Type; 53 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 54 55 #define OSC32KCTRL_INTENCLR_OFFSET 0x00 /**< \brief (OSC32KCTRL_INTENCLR offset) Interrupt Enable Clear */ 56 #define OSC32KCTRL_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_INTENCLR reset_value) Interrupt Enable Clear */ 57 58 #define OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_INTENCLR) XOSC32K Ready Interrupt Enable */ 59 #define OSC32KCTRL_INTENCLR_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos) 60 #define OSC32KCTRL_INTENCLR_OSC32KRDY_Pos 1 /**< \brief (OSC32KCTRL_INTENCLR) OSC32K Ready Interrupt Enable */ 61 #define OSC32KCTRL_INTENCLR_OSC32KRDY (_U_(0x1) << OSC32KCTRL_INTENCLR_OSC32KRDY_Pos) 62 #define OSC32KCTRL_INTENCLR_CLKFAIL_Pos 2 /**< \brief (OSC32KCTRL_INTENCLR) XOSC32K Clock Failure Detector Interrupt Enable */ 63 #define OSC32KCTRL_INTENCLR_CLKFAIL (_U_(0x1) << OSC32KCTRL_INTENCLR_CLKFAIL_Pos) 64 #define OSC32KCTRL_INTENCLR_MASK _U_(0x00000007) /**< \brief (OSC32KCTRL_INTENCLR) MASK Register */ 65 66 /* -------- OSC32KCTRL_INTENSET : (OSC32KCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */ 67 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 68 typedef union { 69 struct { 70 uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready Interrupt Enable */ 71 uint32_t OSC32KRDY:1; /*!< bit: 1 OSC32K Ready Interrupt Enable */ 72 uint32_t CLKFAIL:1; /*!< bit: 2 XOSC32K Clock Failure Detector Interrupt Enable */ 73 uint32_t :29; /*!< bit: 3..31 Reserved */ 74 } bit; /*!< Structure used for bit access */ 75 uint32_t reg; /*!< Type used for register access */ 76 } OSC32KCTRL_INTENSET_Type; 77 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 78 79 #define OSC32KCTRL_INTENSET_OFFSET 0x04 /**< \brief (OSC32KCTRL_INTENSET offset) Interrupt Enable Set */ 80 #define OSC32KCTRL_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_INTENSET reset_value) Interrupt Enable Set */ 81 82 #define OSC32KCTRL_INTENSET_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_INTENSET) XOSC32K Ready Interrupt Enable */ 83 #define OSC32KCTRL_INTENSET_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTENSET_XOSC32KRDY_Pos) 84 #define OSC32KCTRL_INTENSET_OSC32KRDY_Pos 1 /**< \brief (OSC32KCTRL_INTENSET) OSC32K Ready Interrupt Enable */ 85 #define OSC32KCTRL_INTENSET_OSC32KRDY (_U_(0x1) << OSC32KCTRL_INTENSET_OSC32KRDY_Pos) 86 #define OSC32KCTRL_INTENSET_CLKFAIL_Pos 2 /**< \brief (OSC32KCTRL_INTENSET) XOSC32K Clock Failure Detector Interrupt Enable */ 87 #define OSC32KCTRL_INTENSET_CLKFAIL (_U_(0x1) << OSC32KCTRL_INTENSET_CLKFAIL_Pos) 88 #define OSC32KCTRL_INTENSET_MASK _U_(0x00000007) /**< \brief (OSC32KCTRL_INTENSET) MASK Register */ 89 90 /* -------- OSC32KCTRL_INTFLAG : (OSC32KCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */ 91 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 92 typedef union { // __I to avoid read-modify-write on write-to-clear register 93 struct { 94 __I uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready */ 95 __I uint32_t OSC32KRDY:1; /*!< bit: 1 OSC32K Ready */ 96 __I uint32_t CLKFAIL:1; /*!< bit: 2 XOSC32K Clock Failure Detector */ 97 __I uint32_t Reserved1:29; /*!< bit: 3..31 Reserved */ 98 } bit; /*!< Structure used for bit access */ 99 uint32_t reg; /*!< Type used for register access */ 100 } OSC32KCTRL_INTFLAG_Type; 101 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 102 103 #define OSC32KCTRL_INTFLAG_OFFSET 0x08 /**< \brief (OSC32KCTRL_INTFLAG offset) Interrupt Flag Status and Clear */ 104 #define OSC32KCTRL_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */ 105 106 #define OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_INTFLAG) XOSC32K Ready */ 107 #define OSC32KCTRL_INTFLAG_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos) 108 #define OSC32KCTRL_INTFLAG_OSC32KRDY_Pos 1 /**< \brief (OSC32KCTRL_INTFLAG) OSC32K Ready */ 109 #define OSC32KCTRL_INTFLAG_OSC32KRDY (_U_(0x1) << OSC32KCTRL_INTFLAG_OSC32KRDY_Pos) 110 #define OSC32KCTRL_INTFLAG_CLKFAIL_Pos 2 /**< \brief (OSC32KCTRL_INTFLAG) XOSC32K Clock Failure Detector */ 111 #define OSC32KCTRL_INTFLAG_CLKFAIL (_U_(0x1) << OSC32KCTRL_INTFLAG_CLKFAIL_Pos) 112 #define OSC32KCTRL_INTFLAG_MASK _U_(0x00000007) /**< \brief (OSC32KCTRL_INTFLAG) MASK Register */ 113 114 /* -------- OSC32KCTRL_STATUS : (OSC32KCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */ 115 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 116 typedef union { 117 struct { 118 uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready */ 119 uint32_t OSC32KRDY:1; /*!< bit: 1 OSC32K Ready */ 120 uint32_t CLKFAIL:1; /*!< bit: 2 XOSC32K Clock Failure Detector */ 121 uint32_t CLKSW:1; /*!< bit: 3 XOSC32K Clock switch */ 122 uint32_t :28; /*!< bit: 4..31 Reserved */ 123 } bit; /*!< Structure used for bit access */ 124 uint32_t reg; /*!< Type used for register access */ 125 } OSC32KCTRL_STATUS_Type; 126 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 127 128 #define OSC32KCTRL_STATUS_OFFSET 0x0C /**< \brief (OSC32KCTRL_STATUS offset) Power and Clocks Status */ 129 #define OSC32KCTRL_STATUS_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_STATUS reset_value) Power and Clocks Status */ 130 131 #define OSC32KCTRL_STATUS_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_STATUS) XOSC32K Ready */ 132 #define OSC32KCTRL_STATUS_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KRDY_Pos) 133 #define OSC32KCTRL_STATUS_OSC32KRDY_Pos 1 /**< \brief (OSC32KCTRL_STATUS) OSC32K Ready */ 134 #define OSC32KCTRL_STATUS_OSC32KRDY (_U_(0x1) << OSC32KCTRL_STATUS_OSC32KRDY_Pos) 135 #define OSC32KCTRL_STATUS_CLKFAIL_Pos 2 /**< \brief (OSC32KCTRL_STATUS) XOSC32K Clock Failure Detector */ 136 #define OSC32KCTRL_STATUS_CLKFAIL (_U_(0x1) << OSC32KCTRL_STATUS_CLKFAIL_Pos) 137 #define OSC32KCTRL_STATUS_CLKSW_Pos 3 /**< \brief (OSC32KCTRL_STATUS) XOSC32K Clock switch */ 138 #define OSC32KCTRL_STATUS_CLKSW (_U_(0x1) << OSC32KCTRL_STATUS_CLKSW_Pos) 139 #define OSC32KCTRL_STATUS_MASK _U_(0x0000000F) /**< \brief (OSC32KCTRL_STATUS) MASK Register */ 140 141 /* -------- OSC32KCTRL_RTCCTRL : (OSC32KCTRL Offset: 0x10) (R/W 32) Clock selection -------- */ 142 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 143 typedef union { 144 struct { 145 uint32_t RTCSEL:3; /*!< bit: 0.. 2 RTC Clock Selection */ 146 uint32_t :29; /*!< bit: 3..31 Reserved */ 147 } bit; /*!< Structure used for bit access */ 148 uint32_t reg; /*!< Type used for register access */ 149 } OSC32KCTRL_RTCCTRL_Type; 150 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 151 152 #define OSC32KCTRL_RTCCTRL_OFFSET 0x10 /**< \brief (OSC32KCTRL_RTCCTRL offset) Clock selection */ 153 #define OSC32KCTRL_RTCCTRL_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_RTCCTRL reset_value) Clock selection */ 154 155 #define OSC32KCTRL_RTCCTRL_RTCSEL_Pos 0 /**< \brief (OSC32KCTRL_RTCCTRL) RTC Clock Selection */ 156 #define OSC32KCTRL_RTCCTRL_RTCSEL_Msk (_U_(0x7) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) 157 #define OSC32KCTRL_RTCCTRL_RTCSEL(value) (OSC32KCTRL_RTCCTRL_RTCSEL_Msk & ((value) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)) 158 #define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val _U_(0x0) /**< \brief (OSC32KCTRL_RTCCTRL) 1.024kHz from 32kHz internal ULP oscillator */ 159 #define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val _U_(0x1) /**< \brief (OSC32KCTRL_RTCCTRL) 32.768kHz from 32kHz internal ULP oscillator */ 160 #define OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K_Val _U_(0x2) /**< \brief (OSC32KCTRL_RTCCTRL) 1.024kHz from 32.768kHz internal oscillator */ 161 #define OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K_Val _U_(0x3) /**< \brief (OSC32KCTRL_RTCCTRL) 32.768kHz from 32.768kHz internal oscillator */ 162 #define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val _U_(0x4) /**< \brief (OSC32KCTRL_RTCCTRL) 1.024kHz from 32.768kHz internal oscillator */ 163 #define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val _U_(0x5) /**< \brief (OSC32KCTRL_RTCCTRL) 32.768kHz from 32.768kHz external crystal oscillator */ 164 #define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) 165 #define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) 166 #define OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K (OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) 167 #define OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K (OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) 168 #define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) 169 #define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) 170 #define OSC32KCTRL_RTCCTRL_MASK _U_(0x00000007) /**< \brief (OSC32KCTRL_RTCCTRL) MASK Register */ 171 172 /* -------- OSC32KCTRL_XOSC32K : (OSC32KCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */ 173 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 174 typedef union { 175 struct { 176 uint16_t :1; /*!< bit: 0 Reserved */ 177 uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ 178 uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */ 179 uint16_t EN32K:1; /*!< bit: 3 32kHz Output Enable */ 180 uint16_t EN1K:1; /*!< bit: 4 1kHz Output Enable */ 181 uint16_t :1; /*!< bit: 5 Reserved */ 182 uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ 183 uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ 184 uint16_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */ 185 uint16_t :1; /*!< bit: 11 Reserved */ 186 uint16_t WRTLOCK:1; /*!< bit: 12 Write Lock */ 187 uint16_t :3; /*!< bit: 13..15 Reserved */ 188 } bit; /*!< Structure used for bit access */ 189 uint16_t reg; /*!< Type used for register access */ 190 } OSC32KCTRL_XOSC32K_Type; 191 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 192 193 #define OSC32KCTRL_XOSC32K_OFFSET 0x14 /**< \brief (OSC32KCTRL_XOSC32K offset) 32kHz External Crystal Oscillator (XOSC32K) Control */ 194 #define OSC32KCTRL_XOSC32K_RESETVALUE _U_(0x0080) /**< \brief (OSC32KCTRL_XOSC32K reset_value) 32kHz External Crystal Oscillator (XOSC32K) Control */ 195 196 #define OSC32KCTRL_XOSC32K_ENABLE_Pos 1 /**< \brief (OSC32KCTRL_XOSC32K) Oscillator Enable */ 197 #define OSC32KCTRL_XOSC32K_ENABLE (_U_(0x1) << OSC32KCTRL_XOSC32K_ENABLE_Pos) 198 #define OSC32KCTRL_XOSC32K_XTALEN_Pos 2 /**< \brief (OSC32KCTRL_XOSC32K) Crystal Oscillator Enable */ 199 #define OSC32KCTRL_XOSC32K_XTALEN (_U_(0x1) << OSC32KCTRL_XOSC32K_XTALEN_Pos) 200 #define OSC32KCTRL_XOSC32K_EN32K_Pos 3 /**< \brief (OSC32KCTRL_XOSC32K) 32kHz Output Enable */ 201 #define OSC32KCTRL_XOSC32K_EN32K (_U_(0x1) << OSC32KCTRL_XOSC32K_EN32K_Pos) 202 #define OSC32KCTRL_XOSC32K_EN1K_Pos 4 /**< \brief (OSC32KCTRL_XOSC32K) 1kHz Output Enable */ 203 #define OSC32KCTRL_XOSC32K_EN1K (_U_(0x1) << OSC32KCTRL_XOSC32K_EN1K_Pos) 204 #define OSC32KCTRL_XOSC32K_RUNSTDBY_Pos 6 /**< \brief (OSC32KCTRL_XOSC32K) Run in Standby */ 205 #define OSC32KCTRL_XOSC32K_RUNSTDBY (_U_(0x1) << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos) 206 #define OSC32KCTRL_XOSC32K_ONDEMAND_Pos 7 /**< \brief (OSC32KCTRL_XOSC32K) On Demand Control */ 207 #define OSC32KCTRL_XOSC32K_ONDEMAND (_U_(0x1) << OSC32KCTRL_XOSC32K_ONDEMAND_Pos) 208 #define OSC32KCTRL_XOSC32K_STARTUP_Pos 8 /**< \brief (OSC32KCTRL_XOSC32K) Oscillator Start-Up Time */ 209 #define OSC32KCTRL_XOSC32K_STARTUP_Msk (_U_(0x7) << OSC32KCTRL_XOSC32K_STARTUP_Pos) 210 #define OSC32KCTRL_XOSC32K_STARTUP(value) (OSC32KCTRL_XOSC32K_STARTUP_Msk & ((value) << OSC32KCTRL_XOSC32K_STARTUP_Pos)) 211 #define OSC32KCTRL_XOSC32K_WRTLOCK_Pos 12 /**< \brief (OSC32KCTRL_XOSC32K) Write Lock */ 212 #define OSC32KCTRL_XOSC32K_WRTLOCK (_U_(0x1) << OSC32KCTRL_XOSC32K_WRTLOCK_Pos) 213 #define OSC32KCTRL_XOSC32K_MASK _U_(0x17DE) /**< \brief (OSC32KCTRL_XOSC32K) MASK Register */ 214 215 /* -------- OSC32KCTRL_CFDCTRL : (OSC32KCTRL Offset: 0x16) (R/W 8) Clock Failure Detector Control -------- */ 216 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 217 typedef union { 218 struct { 219 uint8_t CFDEN:1; /*!< bit: 0 Clock Failure Detector Enable */ 220 uint8_t SWBACK:1; /*!< bit: 1 Clock Switch Back */ 221 uint8_t CFDPRESC:1; /*!< bit: 2 Clock Failure Detector Prescaler */ 222 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 223 } bit; /*!< Structure used for bit access */ 224 uint8_t reg; /*!< Type used for register access */ 225 } OSC32KCTRL_CFDCTRL_Type; 226 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 227 228 #define OSC32KCTRL_CFDCTRL_OFFSET 0x16 /**< \brief (OSC32KCTRL_CFDCTRL offset) Clock Failure Detector Control */ 229 #define OSC32KCTRL_CFDCTRL_RESETVALUE _U_(0x00) /**< \brief (OSC32KCTRL_CFDCTRL reset_value) Clock Failure Detector Control */ 230 231 #define OSC32KCTRL_CFDCTRL_CFDEN_Pos 0 /**< \brief (OSC32KCTRL_CFDCTRL) Clock Failure Detector Enable */ 232 #define OSC32KCTRL_CFDCTRL_CFDEN (_U_(0x1) << OSC32KCTRL_CFDCTRL_CFDEN_Pos) 233 #define OSC32KCTRL_CFDCTRL_SWBACK_Pos 1 /**< \brief (OSC32KCTRL_CFDCTRL) Clock Switch Back */ 234 #define OSC32KCTRL_CFDCTRL_SWBACK (_U_(0x1) << OSC32KCTRL_CFDCTRL_SWBACK_Pos) 235 #define OSC32KCTRL_CFDCTRL_CFDPRESC_Pos 2 /**< \brief (OSC32KCTRL_CFDCTRL) Clock Failure Detector Prescaler */ 236 #define OSC32KCTRL_CFDCTRL_CFDPRESC (_U_(0x1) << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos) 237 #define OSC32KCTRL_CFDCTRL_MASK _U_(0x07) /**< \brief (OSC32KCTRL_CFDCTRL) MASK Register */ 238 239 /* -------- OSC32KCTRL_EVCTRL : (OSC32KCTRL Offset: 0x17) (R/W 8) Event Control -------- */ 240 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 241 typedef union { 242 struct { 243 uint8_t CFDEO:1; /*!< bit: 0 Clock Failure Detector Event Output Enable */ 244 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 245 } bit; /*!< Structure used for bit access */ 246 uint8_t reg; /*!< Type used for register access */ 247 } OSC32KCTRL_EVCTRL_Type; 248 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 249 250 #define OSC32KCTRL_EVCTRL_OFFSET 0x17 /**< \brief (OSC32KCTRL_EVCTRL offset) Event Control */ 251 #define OSC32KCTRL_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (OSC32KCTRL_EVCTRL reset_value) Event Control */ 252 253 #define OSC32KCTRL_EVCTRL_CFDEO_Pos 0 /**< \brief (OSC32KCTRL_EVCTRL) Clock Failure Detector Event Output Enable */ 254 #define OSC32KCTRL_EVCTRL_CFDEO (_U_(0x1) << OSC32KCTRL_EVCTRL_CFDEO_Pos) 255 #define OSC32KCTRL_EVCTRL_MASK _U_(0x01) /**< \brief (OSC32KCTRL_EVCTRL) MASK Register */ 256 257 /* -------- OSC32KCTRL_OSC32K : (OSC32KCTRL Offset: 0x18) (R/W 32) 32kHz Internal Oscillator (OSC32K) Control -------- */ 258 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 259 typedef union { 260 struct { 261 uint32_t :1; /*!< bit: 0 Reserved */ 262 uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ 263 uint32_t EN32K:1; /*!< bit: 2 32kHz Output Enable */ 264 uint32_t EN1K:1; /*!< bit: 3 1kHz Output Enable */ 265 uint32_t :2; /*!< bit: 4.. 5 Reserved */ 266 uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ 267 uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ 268 uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */ 269 uint32_t :1; /*!< bit: 11 Reserved */ 270 uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */ 271 uint32_t :3; /*!< bit: 13..15 Reserved */ 272 uint32_t CALIB:7; /*!< bit: 16..22 Oscillator Calibration */ 273 uint32_t :9; /*!< bit: 23..31 Reserved */ 274 } bit; /*!< Structure used for bit access */ 275 uint32_t reg; /*!< Type used for register access */ 276 } OSC32KCTRL_OSC32K_Type; 277 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 278 279 #define OSC32KCTRL_OSC32K_OFFSET 0x18 /**< \brief (OSC32KCTRL_OSC32K offset) 32kHz Internal Oscillator (OSC32K) Control */ 280 #define OSC32KCTRL_OSC32K_RESETVALUE _U_(0x003F0080) /**< \brief (OSC32KCTRL_OSC32K reset_value) 32kHz Internal Oscillator (OSC32K) Control */ 281 282 #define OSC32KCTRL_OSC32K_ENABLE_Pos 1 /**< \brief (OSC32KCTRL_OSC32K) Oscillator Enable */ 283 #define OSC32KCTRL_OSC32K_ENABLE (_U_(0x1) << OSC32KCTRL_OSC32K_ENABLE_Pos) 284 #define OSC32KCTRL_OSC32K_EN32K_Pos 2 /**< \brief (OSC32KCTRL_OSC32K) 32kHz Output Enable */ 285 #define OSC32KCTRL_OSC32K_EN32K (_U_(0x1) << OSC32KCTRL_OSC32K_EN32K_Pos) 286 #define OSC32KCTRL_OSC32K_EN1K_Pos 3 /**< \brief (OSC32KCTRL_OSC32K) 1kHz Output Enable */ 287 #define OSC32KCTRL_OSC32K_EN1K (_U_(0x1) << OSC32KCTRL_OSC32K_EN1K_Pos) 288 #define OSC32KCTRL_OSC32K_RUNSTDBY_Pos 6 /**< \brief (OSC32KCTRL_OSC32K) Run in Standby */ 289 #define OSC32KCTRL_OSC32K_RUNSTDBY (_U_(0x1) << OSC32KCTRL_OSC32K_RUNSTDBY_Pos) 290 #define OSC32KCTRL_OSC32K_ONDEMAND_Pos 7 /**< \brief (OSC32KCTRL_OSC32K) On Demand Control */ 291 #define OSC32KCTRL_OSC32K_ONDEMAND (_U_(0x1) << OSC32KCTRL_OSC32K_ONDEMAND_Pos) 292 #define OSC32KCTRL_OSC32K_STARTUP_Pos 8 /**< \brief (OSC32KCTRL_OSC32K) Oscillator Start-Up Time */ 293 #define OSC32KCTRL_OSC32K_STARTUP_Msk (_U_(0x7) << OSC32KCTRL_OSC32K_STARTUP_Pos) 294 #define OSC32KCTRL_OSC32K_STARTUP(value) (OSC32KCTRL_OSC32K_STARTUP_Msk & ((value) << OSC32KCTRL_OSC32K_STARTUP_Pos)) 295 #define OSC32KCTRL_OSC32K_WRTLOCK_Pos 12 /**< \brief (OSC32KCTRL_OSC32K) Write Lock */ 296 #define OSC32KCTRL_OSC32K_WRTLOCK (_U_(0x1) << OSC32KCTRL_OSC32K_WRTLOCK_Pos) 297 #define OSC32KCTRL_OSC32K_CALIB_Pos 16 /**< \brief (OSC32KCTRL_OSC32K) Oscillator Calibration */ 298 #define OSC32KCTRL_OSC32K_CALIB_Msk (_U_(0x7F) << OSC32KCTRL_OSC32K_CALIB_Pos) 299 #define OSC32KCTRL_OSC32K_CALIB(value) (OSC32KCTRL_OSC32K_CALIB_Msk & ((value) << OSC32KCTRL_OSC32K_CALIB_Pos)) 300 #define OSC32KCTRL_OSC32K_MASK _U_(0x007F17CE) /**< \brief (OSC32KCTRL_OSC32K) MASK Register */ 301 302 /* -------- OSC32KCTRL_OSCULP32K : (OSC32KCTRL Offset: 0x1C) (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */ 303 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 304 typedef union { 305 struct { 306 uint32_t :8; /*!< bit: 0.. 7 Reserved */ 307 uint32_t CALIB:5; /*!< bit: 8..12 Oscillator Calibration */ 308 uint32_t :2; /*!< bit: 13..14 Reserved */ 309 uint32_t WRTLOCK:1; /*!< bit: 15 Write Lock */ 310 uint32_t :16; /*!< bit: 16..31 Reserved */ 311 } bit; /*!< Structure used for bit access */ 312 uint32_t reg; /*!< Type used for register access */ 313 } OSC32KCTRL_OSCULP32K_Type; 314 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 315 316 #define OSC32KCTRL_OSCULP32K_OFFSET 0x1C /**< \brief (OSC32KCTRL_OSCULP32K offset) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ 317 318 #define OSC32KCTRL_OSCULP32K_CALIB_Pos 8 /**< \brief (OSC32KCTRL_OSCULP32K) Oscillator Calibration */ 319 #define OSC32KCTRL_OSCULP32K_CALIB_Msk (_U_(0x1F) << OSC32KCTRL_OSCULP32K_CALIB_Pos) 320 #define OSC32KCTRL_OSCULP32K_CALIB(value) (OSC32KCTRL_OSCULP32K_CALIB_Msk & ((value) << OSC32KCTRL_OSCULP32K_CALIB_Pos)) 321 #define OSC32KCTRL_OSCULP32K_WRTLOCK_Pos 15 /**< \brief (OSC32KCTRL_OSCULP32K) Write Lock */ 322 #define OSC32KCTRL_OSCULP32K_WRTLOCK (_U_(0x1) << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos) 323 #define OSC32KCTRL_OSCULP32K_MASK _U_(0x00009F00) /**< \brief (OSC32KCTRL_OSCULP32K) MASK Register */ 324 325 /** \brief OSC32KCTRL hardware registers */ 326 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 327 typedef struct { 328 __IO OSC32KCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */ 329 __IO OSC32KCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */ 330 __IO OSC32KCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */ 331 __I OSC32KCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */ 332 __IO OSC32KCTRL_RTCCTRL_Type RTCCTRL; /**< \brief Offset: 0x10 (R/W 32) Clock selection */ 333 __IO OSC32KCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */ 334 __IO OSC32KCTRL_CFDCTRL_Type CFDCTRL; /**< \brief Offset: 0x16 (R/W 8) Clock Failure Detector Control */ 335 __IO OSC32KCTRL_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x17 (R/W 8) Event Control */ 336 __IO OSC32KCTRL_OSC32K_Type OSC32K; /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */ 337 __IO OSC32KCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ 338 } Osc32kctrl; 339 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 340 341 /*@}*/ 342 343 #endif /* _SAMC20_OSC32KCTRL_COMPONENT_ */ 344
