1 /** 2 * \file 3 * 4 * \brief Component description for CCL 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMC20_CCL_COMPONENT_ 31 #define _SAMC20_CCL_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR CCL */ 35 /* ========================================================================== */ 36 /** \addtogroup SAMC20_CCL Configurable Custom Logic */ 37 /*@{*/ 38 39 #define CCL_U2225 40 #define REV_CCL 0x200 41 42 /* -------- CCL_CTRL : (CCL Offset: 0x0) (R/W 8) Control -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint8_t SWRST:1; /*!< bit: 0 Software Reset */ 47 uint8_t ENABLE:1; /*!< bit: 1 Enable */ 48 uint8_t :4; /*!< bit: 2.. 5 Reserved */ 49 uint8_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ 50 uint8_t :1; /*!< bit: 7 Reserved */ 51 } bit; /*!< Structure used for bit access */ 52 uint8_t reg; /*!< Type used for register access */ 53 } CCL_CTRL_Type; 54 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 55 56 #define CCL_CTRL_OFFSET 0x0 /**< \brief (CCL_CTRL offset) Control */ 57 #define CCL_CTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_CTRL reset_value) Control */ 58 59 #define CCL_CTRL_SWRST_Pos 0 /**< \brief (CCL_CTRL) Software Reset */ 60 #define CCL_CTRL_SWRST (_U_(0x1) << CCL_CTRL_SWRST_Pos) 61 #define CCL_CTRL_ENABLE_Pos 1 /**< \brief (CCL_CTRL) Enable */ 62 #define CCL_CTRL_ENABLE (_U_(0x1) << CCL_CTRL_ENABLE_Pos) 63 #define CCL_CTRL_RUNSTDBY_Pos 6 /**< \brief (CCL_CTRL) Run during Standby */ 64 #define CCL_CTRL_RUNSTDBY (_U_(0x1) << CCL_CTRL_RUNSTDBY_Pos) 65 #define CCL_CTRL_MASK _U_(0x43) /**< \brief (CCL_CTRL) MASK Register */ 66 67 /* -------- CCL_SEQCTRL : (CCL Offset: 0x4) (R/W 8) SEQ Control x -------- */ 68 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 69 typedef union { 70 struct { 71 uint8_t SEQSEL:4; /*!< bit: 0.. 3 Sequential Selection */ 72 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 73 } bit; /*!< Structure used for bit access */ 74 uint8_t reg; /*!< Type used for register access */ 75 } CCL_SEQCTRL_Type; 76 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 77 78 #define CCL_SEQCTRL_OFFSET 0x4 /**< \brief (CCL_SEQCTRL offset) SEQ Control x */ 79 #define CCL_SEQCTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_SEQCTRL reset_value) SEQ Control x */ 80 81 #define CCL_SEQCTRL_SEQSEL_Pos 0 /**< \brief (CCL_SEQCTRL) Sequential Selection */ 82 #define CCL_SEQCTRL_SEQSEL_Msk (_U_(0xF) << CCL_SEQCTRL_SEQSEL_Pos) 83 #define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & ((value) << CCL_SEQCTRL_SEQSEL_Pos)) 84 #define CCL_SEQCTRL_SEQSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_SEQCTRL) Sequential logic is disabled */ 85 #define CCL_SEQCTRL_SEQSEL_DFF_Val _U_(0x1) /**< \brief (CCL_SEQCTRL) D flip flop */ 86 #define CCL_SEQCTRL_SEQSEL_JK_Val _U_(0x2) /**< \brief (CCL_SEQCTRL) JK flip flop */ 87 #define CCL_SEQCTRL_SEQSEL_LATCH_Val _U_(0x3) /**< \brief (CCL_SEQCTRL) D latch */ 88 #define CCL_SEQCTRL_SEQSEL_RS_Val _U_(0x4) /**< \brief (CCL_SEQCTRL) RS latch */ 89 #define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos) 90 #define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos) 91 #define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos) 92 #define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos) 93 #define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos) 94 #define CCL_SEQCTRL_MASK _U_(0x0F) /**< \brief (CCL_SEQCTRL) MASK Register */ 95 96 /* -------- CCL_LUTCTRL : (CCL Offset: 0x8) (R/W 32) LUT Control x -------- */ 97 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 98 typedef union { 99 struct { 100 uint32_t :1; /*!< bit: 0 Reserved */ 101 uint32_t ENABLE:1; /*!< bit: 1 LUT Enable */ 102 uint32_t :2; /*!< bit: 2.. 3 Reserved */ 103 uint32_t FILTSEL:2; /*!< bit: 4.. 5 Filter Selection */ 104 uint32_t :1; /*!< bit: 6 Reserved */ 105 uint32_t EDGESEL:1; /*!< bit: 7 Edge Selection */ 106 uint32_t INSEL0:4; /*!< bit: 8..11 Input Selection 0 */ 107 uint32_t INSEL1:4; /*!< bit: 12..15 Input Selection 1 */ 108 uint32_t INSEL2:4; /*!< bit: 16..19 Input Selection 2 */ 109 uint32_t INVEI:1; /*!< bit: 20 Input Event Invert */ 110 uint32_t LUTEI:1; /*!< bit: 21 Event Input Enable */ 111 uint32_t LUTEO:1; /*!< bit: 22 Event Output Enable */ 112 uint32_t :1; /*!< bit: 23 Reserved */ 113 uint32_t TRUTH:8; /*!< bit: 24..31 Truth Value */ 114 } bit; /*!< Structure used for bit access */ 115 uint32_t reg; /*!< Type used for register access */ 116 } CCL_LUTCTRL_Type; 117 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 118 119 #define CCL_LUTCTRL_OFFSET 0x8 /**< \brief (CCL_LUTCTRL offset) LUT Control x */ 120 #define CCL_LUTCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CCL_LUTCTRL reset_value) LUT Control x */ 121 122 #define CCL_LUTCTRL_ENABLE_Pos 1 /**< \brief (CCL_LUTCTRL) LUT Enable */ 123 #define CCL_LUTCTRL_ENABLE (_U_(0x1) << CCL_LUTCTRL_ENABLE_Pos) 124 #define CCL_LUTCTRL_FILTSEL_Pos 4 /**< \brief (CCL_LUTCTRL) Filter Selection */ 125 #define CCL_LUTCTRL_FILTSEL_Msk (_U_(0x3) << CCL_LUTCTRL_FILTSEL_Pos) 126 #define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & ((value) << CCL_LUTCTRL_FILTSEL_Pos)) 127 #define CCL_LUTCTRL_FILTSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Filter disabled */ 128 #define CCL_LUTCTRL_FILTSEL_SYNCH_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Synchronizer enabled */ 129 #define CCL_LUTCTRL_FILTSEL_FILTER_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Filter enabled */ 130 #define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos) 131 #define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos) 132 #define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos) 133 #define CCL_LUTCTRL_EDGESEL_Pos 7 /**< \brief (CCL_LUTCTRL) Edge Selection */ 134 #define CCL_LUTCTRL_EDGESEL (_U_(0x1) << CCL_LUTCTRL_EDGESEL_Pos) 135 #define CCL_LUTCTRL_INSEL0_Pos 8 /**< \brief (CCL_LUTCTRL) Input Selection 0 */ 136 #define CCL_LUTCTRL_INSEL0_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL0_Pos) 137 #define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & ((value) << CCL_LUTCTRL_INSEL0_Pos)) 138 #define CCL_LUTCTRL_INSEL0_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */ 139 #define CCL_LUTCTRL_INSEL0_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */ 140 #define CCL_LUTCTRL_INSEL0_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */ 141 #define CCL_LUTCTRL_INSEL0_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event in put source */ 142 #define CCL_LUTCTRL_INSEL0_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */ 143 #define CCL_LUTCTRL_INSEL0_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */ 144 #define CCL_LUTCTRL_INSEL0_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */ 145 #define CCL_LUTCTRL_INSEL0_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */ 146 #define CCL_LUTCTRL_INSEL0_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */ 147 #define CCL_LUTCTRL_INSEL0_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM inout source */ 148 #define CCL_LUTCTRL_INSEL0_ALT2TC_Val _U_(0xA) /**< \brief (CCL_LUTCTRL) Alternate 2 TC input source */ 149 #define CCL_LUTCTRL_INSEL0_ASYNCEVENT_Val _U_(0xB) /**< \brief (CCL_LUTCTRL) ASYNC EVENT input source. The EVENT input will bypass edge detection logic. */ 150 #define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos) 151 #define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos) 152 #define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos) 153 #define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos) 154 #define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos) 155 #define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos) 156 #define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos) 157 #define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos) 158 #define CCL_LUTCTRL_INSEL0_TCC (CCL_LUTCTRL_INSEL0_TCC_Val << CCL_LUTCTRL_INSEL0_Pos) 159 #define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos) 160 #define CCL_LUTCTRL_INSEL0_ALT2TC (CCL_LUTCTRL_INSEL0_ALT2TC_Val << CCL_LUTCTRL_INSEL0_Pos) 161 #define CCL_LUTCTRL_INSEL0_ASYNCEVENT (CCL_LUTCTRL_INSEL0_ASYNCEVENT_Val << CCL_LUTCTRL_INSEL0_Pos) 162 #define CCL_LUTCTRL_INSEL1_Pos 12 /**< \brief (CCL_LUTCTRL) Input Selection 1 */ 163 #define CCL_LUTCTRL_INSEL1_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL1_Pos) 164 #define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & ((value) << CCL_LUTCTRL_INSEL1_Pos)) 165 #define CCL_LUTCTRL_INSEL2_Pos 16 /**< \brief (CCL_LUTCTRL) Input Selection 2 */ 166 #define CCL_LUTCTRL_INSEL2_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL2_Pos) 167 #define CCL_LUTCTRL_INSEL2(value) (CCL_LUTCTRL_INSEL2_Msk & ((value) << CCL_LUTCTRL_INSEL2_Pos)) 168 #define CCL_LUTCTRL_INVEI_Pos 20 /**< \brief (CCL_LUTCTRL) Input Event Invert */ 169 #define CCL_LUTCTRL_INVEI (_U_(0x1) << CCL_LUTCTRL_INVEI_Pos) 170 #define CCL_LUTCTRL_LUTEI_Pos 21 /**< \brief (CCL_LUTCTRL) Event Input Enable */ 171 #define CCL_LUTCTRL_LUTEI (_U_(0x1) << CCL_LUTCTRL_LUTEI_Pos) 172 #define CCL_LUTCTRL_LUTEO_Pos 22 /**< \brief (CCL_LUTCTRL) Event Output Enable */ 173 #define CCL_LUTCTRL_LUTEO (_U_(0x1) << CCL_LUTCTRL_LUTEO_Pos) 174 #define CCL_LUTCTRL_TRUTH_Pos 24 /**< \brief (CCL_LUTCTRL) Truth Value */ 175 #define CCL_LUTCTRL_TRUTH_Msk (_U_(0xFF) << CCL_LUTCTRL_TRUTH_Pos) 176 #define CCL_LUTCTRL_TRUTH(value) (CCL_LUTCTRL_TRUTH_Msk & ((value) << CCL_LUTCTRL_TRUTH_Pos)) 177 #define CCL_LUTCTRL_MASK _U_(0xFF7FFFB2) /**< \brief (CCL_LUTCTRL) MASK Register */ 178 179 /** \brief CCL hardware registers */ 180 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 181 typedef struct { 182 __IO CCL_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ 183 RoReg8 Reserved1[0x3]; 184 __IO CCL_SEQCTRL_Type SEQCTRL[2]; /**< \brief Offset: 0x4 (R/W 8) SEQ Control x */ 185 RoReg8 Reserved2[0x2]; 186 __IO CCL_LUTCTRL_Type LUTCTRL[4]; /**< \brief Offset: 0x8 (R/W 32) LUT Control x */ 187 } Ccl; 188 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 189 190 /*@}*/ 191 192 #endif /* _SAMC20_CCL_COMPONENT_ */ 193