1 /** 2 * \file 3 * 4 * \brief Instance description for EIC 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMC20_EIC_INSTANCE_ 31 #define _SAMC20_EIC_INSTANCE_ 32 33 /* ========== Register definition for EIC peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_EIC_CTRLA (0x40002800) /**< \brief (EIC) Control */ 36 #define REG_EIC_NMICTRL (0x40002801) /**< \brief (EIC) NMI Control */ 37 #define REG_EIC_NMIFLAG (0x40002802) /**< \brief (EIC) NMI Interrupt Flag */ 38 #define REG_EIC_SYNCBUSY (0x40002804) /**< \brief (EIC) Syncbusy register */ 39 #define REG_EIC_EVCTRL (0x40002808) /**< \brief (EIC) Event Control */ 40 #define REG_EIC_INTENCLR (0x4000280C) /**< \brief (EIC) Interrupt Enable Clear */ 41 #define REG_EIC_INTENSET (0x40002810) /**< \brief (EIC) Interrupt Enable Set */ 42 #define REG_EIC_INTFLAG (0x40002814) /**< \brief (EIC) Interrupt Flag Status and Clear */ 43 #define REG_EIC_ASYNCH (0x40002818) /**< \brief (EIC) EIC Asynchronous edge Detection Enable */ 44 #define REG_EIC_CONFIG0 (0x4000281C) /**< \brief (EIC) Configuration 0 */ 45 #define REG_EIC_CONFIG1 (0x40002820) /**< \brief (EIC) Configuration 1 */ 46 #else 47 #define REG_EIC_CTRLA (*(RwReg8 *)0x40002800UL) /**< \brief (EIC) Control */ 48 #define REG_EIC_NMICTRL (*(RwReg8 *)0x40002801UL) /**< \brief (EIC) NMI Control */ 49 #define REG_EIC_NMIFLAG (*(RwReg16*)0x40002802UL) /**< \brief (EIC) NMI Interrupt Flag */ 50 #define REG_EIC_SYNCBUSY (*(RoReg *)0x40002804UL) /**< \brief (EIC) Syncbusy register */ 51 #define REG_EIC_EVCTRL (*(RwReg *)0x40002808UL) /**< \brief (EIC) Event Control */ 52 #define REG_EIC_INTENCLR (*(RwReg *)0x4000280CUL) /**< \brief (EIC) Interrupt Enable Clear */ 53 #define REG_EIC_INTENSET (*(RwReg *)0x40002810UL) /**< \brief (EIC) Interrupt Enable Set */ 54 #define REG_EIC_INTFLAG (*(RwReg *)0x40002814UL) /**< \brief (EIC) Interrupt Flag Status and Clear */ 55 #define REG_EIC_ASYNCH (*(RwReg *)0x40002818UL) /**< \brief (EIC) EIC Asynchronous edge Detection Enable */ 56 #define REG_EIC_CONFIG0 (*(RwReg *)0x4000281CUL) /**< \brief (EIC) Configuration 0 */ 57 #define REG_EIC_CONFIG1 (*(RwReg *)0x40002820UL) /**< \brief (EIC) Configuration 1 */ 58 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 59 60 /* ========== Instance parameters for EIC peripheral ========== */ 61 #define EIC_EXTINT_NUM 16 62 #define EIC_GCLK_ID 2 63 #define EIC_NUMBER_OF_CONFIG_REGS 2 64 #define EIC_NUMBER_OF_INTERRUPTS 16 65 66 #endif /* _SAMC20_EIC_INSTANCE_ */ 67
