1 /** 2 * \file 3 * 4 * \brief Component description for PAC 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMC20_PAC_COMPONENT_ 31 #define _SAMC20_PAC_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR PAC */ 35 /* ========================================================================== */ 36 /** \addtogroup SAMC20_PAC Peripheral Access Controller */ 37 /*@{*/ 38 39 #define PAC_U2120 40 #define REV_PAC 0x110 41 42 /* -------- PAC_WRCTRL : (PAC Offset: 0x00) (R/W 32) Write control -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint32_t PERID:16; /*!< bit: 0..15 Peripheral identifier */ 47 uint32_t KEY:8; /*!< bit: 16..23 Peripheral access control key */ 48 uint32_t :8; /*!< bit: 24..31 Reserved */ 49 } bit; /*!< Structure used for bit access */ 50 uint32_t reg; /*!< Type used for register access */ 51 } PAC_WRCTRL_Type; 52 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 53 54 #define PAC_WRCTRL_OFFSET 0x00 /**< \brief (PAC_WRCTRL offset) Write control */ 55 #define PAC_WRCTRL_RESETVALUE _U_(0x00000000) /**< \brief (PAC_WRCTRL reset_value) Write control */ 56 57 #define PAC_WRCTRL_PERID_Pos 0 /**< \brief (PAC_WRCTRL) Peripheral identifier */ 58 #define PAC_WRCTRL_PERID_Msk (_U_(0xFFFF) << PAC_WRCTRL_PERID_Pos) 59 #define PAC_WRCTRL_PERID(value) (PAC_WRCTRL_PERID_Msk & ((value) << PAC_WRCTRL_PERID_Pos)) 60 #define PAC_WRCTRL_KEY_Pos 16 /**< \brief (PAC_WRCTRL) Peripheral access control key */ 61 #define PAC_WRCTRL_KEY_Msk (_U_(0xFF) << PAC_WRCTRL_KEY_Pos) 62 #define PAC_WRCTRL_KEY(value) (PAC_WRCTRL_KEY_Msk & ((value) << PAC_WRCTRL_KEY_Pos)) 63 #define PAC_WRCTRL_KEY_OFF_Val _U_(0x0) /**< \brief (PAC_WRCTRL) No action */ 64 #define PAC_WRCTRL_KEY_CLR_Val _U_(0x1) /**< \brief (PAC_WRCTRL) Clear protection */ 65 #define PAC_WRCTRL_KEY_SET_Val _U_(0x2) /**< \brief (PAC_WRCTRL) Set protection */ 66 #define PAC_WRCTRL_KEY_SETLCK_Val _U_(0x3) /**< \brief (PAC_WRCTRL) Set and lock protection */ 67 #define PAC_WRCTRL_KEY_OFF (PAC_WRCTRL_KEY_OFF_Val << PAC_WRCTRL_KEY_Pos) 68 #define PAC_WRCTRL_KEY_CLR (PAC_WRCTRL_KEY_CLR_Val << PAC_WRCTRL_KEY_Pos) 69 #define PAC_WRCTRL_KEY_SET (PAC_WRCTRL_KEY_SET_Val << PAC_WRCTRL_KEY_Pos) 70 #define PAC_WRCTRL_KEY_SETLCK (PAC_WRCTRL_KEY_SETLCK_Val << PAC_WRCTRL_KEY_Pos) 71 #define PAC_WRCTRL_MASK _U_(0x00FFFFFF) /**< \brief (PAC_WRCTRL) MASK Register */ 72 73 /* -------- PAC_EVCTRL : (PAC Offset: 0x04) (R/W 8) Event control -------- */ 74 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 75 typedef union { 76 struct { 77 uint8_t ERREO:1; /*!< bit: 0 Peripheral acess error event output */ 78 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 79 } bit; /*!< Structure used for bit access */ 80 uint8_t reg; /*!< Type used for register access */ 81 } PAC_EVCTRL_Type; 82 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 83 84 #define PAC_EVCTRL_OFFSET 0x04 /**< \brief (PAC_EVCTRL offset) Event control */ 85 #define PAC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (PAC_EVCTRL reset_value) Event control */ 86 87 #define PAC_EVCTRL_ERREO_Pos 0 /**< \brief (PAC_EVCTRL) Peripheral acess error event output */ 88 #define PAC_EVCTRL_ERREO (_U_(0x1) << PAC_EVCTRL_ERREO_Pos) 89 #define PAC_EVCTRL_MASK _U_(0x01) /**< \brief (PAC_EVCTRL) MASK Register */ 90 91 /* -------- PAC_INTENCLR : (PAC Offset: 0x08) (R/W 8) Interrupt enable clear -------- */ 92 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 93 typedef union { 94 struct { 95 uint8_t ERR:1; /*!< bit: 0 Peripheral access error interrupt disable */ 96 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 97 } bit; /*!< Structure used for bit access */ 98 uint8_t reg; /*!< Type used for register access */ 99 } PAC_INTENCLR_Type; 100 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 101 102 #define PAC_INTENCLR_OFFSET 0x08 /**< \brief (PAC_INTENCLR offset) Interrupt enable clear */ 103 #define PAC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (PAC_INTENCLR reset_value) Interrupt enable clear */ 104 105 #define PAC_INTENCLR_ERR_Pos 0 /**< \brief (PAC_INTENCLR) Peripheral access error interrupt disable */ 106 #define PAC_INTENCLR_ERR (_U_(0x1) << PAC_INTENCLR_ERR_Pos) 107 #define PAC_INTENCLR_MASK _U_(0x01) /**< \brief (PAC_INTENCLR) MASK Register */ 108 109 /* -------- PAC_INTENSET : (PAC Offset: 0x09) (R/W 8) Interrupt enable set -------- */ 110 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 111 typedef union { 112 struct { 113 uint8_t ERR:1; /*!< bit: 0 Peripheral access error interrupt enable */ 114 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 115 } bit; /*!< Structure used for bit access */ 116 uint8_t reg; /*!< Type used for register access */ 117 } PAC_INTENSET_Type; 118 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 119 120 #define PAC_INTENSET_OFFSET 0x09 /**< \brief (PAC_INTENSET offset) Interrupt enable set */ 121 #define PAC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (PAC_INTENSET reset_value) Interrupt enable set */ 122 123 #define PAC_INTENSET_ERR_Pos 0 /**< \brief (PAC_INTENSET) Peripheral access error interrupt enable */ 124 #define PAC_INTENSET_ERR (_U_(0x1) << PAC_INTENSET_ERR_Pos) 125 #define PAC_INTENSET_MASK _U_(0x01) /**< \brief (PAC_INTENSET) MASK Register */ 126 127 /* -------- PAC_INTFLAGAHB : (PAC Offset: 0x10) (R/W 32) Bridge interrupt flag status -------- */ 128 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 129 typedef union { // __I to avoid read-modify-write on write-to-clear register 130 struct { 131 __I uint32_t FLASH_:1; /*!< bit: 0 FLASH */ 132 __I uint32_t HSRAMCM0P_:1; /*!< bit: 1 HSRAMCM0P */ 133 __I uint32_t HSRAMDSU_:1; /*!< bit: 2 HSRAMDSU */ 134 __I uint32_t HPB1_:1; /*!< bit: 3 HPB1 */ 135 __I uint32_t HPB0_:1; /*!< bit: 4 HPB0 */ 136 __I uint32_t HPB2_:1; /*!< bit: 5 HPB2 */ 137 __I uint32_t LPRAMDMAC_:1; /*!< bit: 6 LPRAMDMAC */ 138 __I uint32_t DIVAS_:1; /*!< bit: 7 DIVAS */ 139 __I uint32_t Reserved1:24; /*!< bit: 8..31 Reserved */ 140 } bit; /*!< Structure used for bit access */ 141 uint32_t reg; /*!< Type used for register access */ 142 } PAC_INTFLAGAHB_Type; 143 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 144 145 #define PAC_INTFLAGAHB_OFFSET 0x10 /**< \brief (PAC_INTFLAGAHB offset) Bridge interrupt flag status */ 146 #define PAC_INTFLAGAHB_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGAHB reset_value) Bridge interrupt flag status */ 147 148 #define PAC_INTFLAGAHB_FLASH_Pos 0 /**< \brief (PAC_INTFLAGAHB) FLASH */ 149 #define PAC_INTFLAGAHB_FLASH (_U_(0x1) << PAC_INTFLAGAHB_FLASH_Pos) 150 #define PAC_INTFLAGAHB_HSRAMCM0P_Pos 1 /**< \brief (PAC_INTFLAGAHB) HSRAMCM0P */ 151 #define PAC_INTFLAGAHB_HSRAMCM0P (_U_(0x1) << PAC_INTFLAGAHB_HSRAMCM0P_Pos) 152 #define PAC_INTFLAGAHB_HSRAMDSU_Pos 2 /**< \brief (PAC_INTFLAGAHB) HSRAMDSU */ 153 #define PAC_INTFLAGAHB_HSRAMDSU (_U_(0x1) << PAC_INTFLAGAHB_HSRAMDSU_Pos) 154 #define PAC_INTFLAGAHB_HPB1_Pos 3 /**< \brief (PAC_INTFLAGAHB) HPB1 */ 155 #define PAC_INTFLAGAHB_HPB1 (_U_(0x1) << PAC_INTFLAGAHB_HPB1_Pos) 156 #define PAC_INTFLAGAHB_HPB0_Pos 4 /**< \brief (PAC_INTFLAGAHB) HPB0 */ 157 #define PAC_INTFLAGAHB_HPB0 (_U_(0x1) << PAC_INTFLAGAHB_HPB0_Pos) 158 #define PAC_INTFLAGAHB_HPB2_Pos 5 /**< \brief (PAC_INTFLAGAHB) HPB2 */ 159 #define PAC_INTFLAGAHB_HPB2 (_U_(0x1) << PAC_INTFLAGAHB_HPB2_Pos) 160 #define PAC_INTFLAGAHB_LPRAMDMAC_Pos 6 /**< \brief (PAC_INTFLAGAHB) LPRAMDMAC */ 161 #define PAC_INTFLAGAHB_LPRAMDMAC (_U_(0x1) << PAC_INTFLAGAHB_LPRAMDMAC_Pos) 162 #define PAC_INTFLAGAHB_DIVAS_Pos 7 /**< \brief (PAC_INTFLAGAHB) DIVAS */ 163 #define PAC_INTFLAGAHB_DIVAS (_U_(0x1) << PAC_INTFLAGAHB_DIVAS_Pos) 164 #define PAC_INTFLAGAHB_MASK _U_(0x000000FF) /**< \brief (PAC_INTFLAGAHB) MASK Register */ 165 166 /* -------- PAC_INTFLAGA : (PAC Offset: 0x14) (R/W 32) Peripheral interrupt flag status - Bridge A -------- */ 167 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 168 typedef union { // __I to avoid read-modify-write on write-to-clear register 169 struct { 170 __I uint32_t PAC_:1; /*!< bit: 0 PAC */ 171 __I uint32_t PM_:1; /*!< bit: 1 PM */ 172 __I uint32_t MCLK_:1; /*!< bit: 2 MCLK */ 173 __I uint32_t RSTC_:1; /*!< bit: 3 RSTC */ 174 __I uint32_t OSCCTRL_:1; /*!< bit: 4 OSCCTRL */ 175 __I uint32_t OSC32KCTRL_:1; /*!< bit: 5 OSC32KCTRL */ 176 __I uint32_t SUPC_:1; /*!< bit: 6 SUPC */ 177 __I uint32_t GCLK_:1; /*!< bit: 7 GCLK */ 178 __I uint32_t WDT_:1; /*!< bit: 8 WDT */ 179 __I uint32_t RTC_:1; /*!< bit: 9 RTC */ 180 __I uint32_t EIC_:1; /*!< bit: 10 EIC */ 181 __I uint32_t FREQM_:1; /*!< bit: 11 FREQM */ 182 __I uint32_t Reserved1:20; /*!< bit: 12..31 Reserved */ 183 } bit; /*!< Structure used for bit access */ 184 uint32_t reg; /*!< Type used for register access */ 185 } PAC_INTFLAGA_Type; 186 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 187 188 #define PAC_INTFLAGA_OFFSET 0x14 /**< \brief (PAC_INTFLAGA offset) Peripheral interrupt flag status - Bridge A */ 189 #define PAC_INTFLAGA_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGA reset_value) Peripheral interrupt flag status - Bridge A */ 190 191 #define PAC_INTFLAGA_PAC_Pos 0 /**< \brief (PAC_INTFLAGA) PAC */ 192 #define PAC_INTFLAGA_PAC (_U_(0x1) << PAC_INTFLAGA_PAC_Pos) 193 #define PAC_INTFLAGA_PM_Pos 1 /**< \brief (PAC_INTFLAGA) PM */ 194 #define PAC_INTFLAGA_PM (_U_(0x1) << PAC_INTFLAGA_PM_Pos) 195 #define PAC_INTFLAGA_MCLK_Pos 2 /**< \brief (PAC_INTFLAGA) MCLK */ 196 #define PAC_INTFLAGA_MCLK (_U_(0x1) << PAC_INTFLAGA_MCLK_Pos) 197 #define PAC_INTFLAGA_RSTC_Pos 3 /**< \brief (PAC_INTFLAGA) RSTC */ 198 #define PAC_INTFLAGA_RSTC (_U_(0x1) << PAC_INTFLAGA_RSTC_Pos) 199 #define PAC_INTFLAGA_OSCCTRL_Pos 4 /**< \brief (PAC_INTFLAGA) OSCCTRL */ 200 #define PAC_INTFLAGA_OSCCTRL (_U_(0x1) << PAC_INTFLAGA_OSCCTRL_Pos) 201 #define PAC_INTFLAGA_OSC32KCTRL_Pos 5 /**< \brief (PAC_INTFLAGA) OSC32KCTRL */ 202 #define PAC_INTFLAGA_OSC32KCTRL (_U_(0x1) << PAC_INTFLAGA_OSC32KCTRL_Pos) 203 #define PAC_INTFLAGA_SUPC_Pos 6 /**< \brief (PAC_INTFLAGA) SUPC */ 204 #define PAC_INTFLAGA_SUPC (_U_(0x1) << PAC_INTFLAGA_SUPC_Pos) 205 #define PAC_INTFLAGA_GCLK_Pos 7 /**< \brief (PAC_INTFLAGA) GCLK */ 206 #define PAC_INTFLAGA_GCLK (_U_(0x1) << PAC_INTFLAGA_GCLK_Pos) 207 #define PAC_INTFLAGA_WDT_Pos 8 /**< \brief (PAC_INTFLAGA) WDT */ 208 #define PAC_INTFLAGA_WDT (_U_(0x1) << PAC_INTFLAGA_WDT_Pos) 209 #define PAC_INTFLAGA_RTC_Pos 9 /**< \brief (PAC_INTFLAGA) RTC */ 210 #define PAC_INTFLAGA_RTC (_U_(0x1) << PAC_INTFLAGA_RTC_Pos) 211 #define PAC_INTFLAGA_EIC_Pos 10 /**< \brief (PAC_INTFLAGA) EIC */ 212 #define PAC_INTFLAGA_EIC (_U_(0x1) << PAC_INTFLAGA_EIC_Pos) 213 #define PAC_INTFLAGA_FREQM_Pos 11 /**< \brief (PAC_INTFLAGA) FREQM */ 214 #define PAC_INTFLAGA_FREQM (_U_(0x1) << PAC_INTFLAGA_FREQM_Pos) 215 #define PAC_INTFLAGA_MASK _U_(0x00000FFF) /**< \brief (PAC_INTFLAGA) MASK Register */ 216 217 /* -------- PAC_INTFLAGB : (PAC Offset: 0x18) (R/W 32) Peripheral interrupt flag status - Bridge B -------- */ 218 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 219 typedef union { // __I to avoid read-modify-write on write-to-clear register 220 struct { 221 __I uint32_t PORT_:1; /*!< bit: 0 PORT */ 222 __I uint32_t DSU_:1; /*!< bit: 1 DSU */ 223 __I uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL */ 224 __I uint32_t DMAC_:1; /*!< bit: 3 DMAC */ 225 __I uint32_t MTB_:1; /*!< bit: 4 MTB */ 226 __I uint32_t HMATRIXHS_:1; /*!< bit: 5 HMATRIXHS */ 227 __I uint32_t Reserved1:26; /*!< bit: 6..31 Reserved */ 228 } bit; /*!< Structure used for bit access */ 229 uint32_t reg; /*!< Type used for register access */ 230 } PAC_INTFLAGB_Type; 231 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 232 233 #define PAC_INTFLAGB_OFFSET 0x18 /**< \brief (PAC_INTFLAGB offset) Peripheral interrupt flag status - Bridge B */ 234 #define PAC_INTFLAGB_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGB reset_value) Peripheral interrupt flag status - Bridge B */ 235 236 #define PAC_INTFLAGB_PORT_Pos 0 /**< \brief (PAC_INTFLAGB) PORT */ 237 #define PAC_INTFLAGB_PORT (_U_(0x1) << PAC_INTFLAGB_PORT_Pos) 238 #define PAC_INTFLAGB_DSU_Pos 1 /**< \brief (PAC_INTFLAGB) DSU */ 239 #define PAC_INTFLAGB_DSU (_U_(0x1) << PAC_INTFLAGB_DSU_Pos) 240 #define PAC_INTFLAGB_NVMCTRL_Pos 2 /**< \brief (PAC_INTFLAGB) NVMCTRL */ 241 #define PAC_INTFLAGB_NVMCTRL (_U_(0x1) << PAC_INTFLAGB_NVMCTRL_Pos) 242 #define PAC_INTFLAGB_DMAC_Pos 3 /**< \brief (PAC_INTFLAGB) DMAC */ 243 #define PAC_INTFLAGB_DMAC (_U_(0x1) << PAC_INTFLAGB_DMAC_Pos) 244 #define PAC_INTFLAGB_MTB_Pos 4 /**< \brief (PAC_INTFLAGB) MTB */ 245 #define PAC_INTFLAGB_MTB (_U_(0x1) << PAC_INTFLAGB_MTB_Pos) 246 #define PAC_INTFLAGB_HMATRIXHS_Pos 5 /**< \brief (PAC_INTFLAGB) HMATRIXHS */ 247 #define PAC_INTFLAGB_HMATRIXHS (_U_(0x1) << PAC_INTFLAGB_HMATRIXHS_Pos) 248 #define PAC_INTFLAGB_MASK _U_(0x0000003F) /**< \brief (PAC_INTFLAGB) MASK Register */ 249 250 /* -------- PAC_INTFLAGC : (PAC Offset: 0x1C) (R/W 32) Peripheral interrupt flag status - Bridge C -------- */ 251 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 252 typedef union { // __I to avoid read-modify-write on write-to-clear register 253 struct { 254 __I uint32_t EVSYS_:1; /*!< bit: 0 EVSYS */ 255 __I uint32_t SERCOM0_:1; /*!< bit: 1 SERCOM0 */ 256 __I uint32_t SERCOM1_:1; /*!< bit: 2 SERCOM1 */ 257 __I uint32_t SERCOM2_:1; /*!< bit: 3 SERCOM2 */ 258 __I uint32_t SERCOM3_:1; /*!< bit: 4 SERCOM3 */ 259 __I uint32_t Reserved1:4; /*!< bit: 5.. 8 Reserved */ 260 __I uint32_t TCC0_:1; /*!< bit: 9 TCC0 */ 261 __I uint32_t TCC1_:1; /*!< bit: 10 TCC1 */ 262 __I uint32_t TCC2_:1; /*!< bit: 11 TCC2 */ 263 __I uint32_t TC0_:1; /*!< bit: 12 TC0 */ 264 __I uint32_t TC1_:1; /*!< bit: 13 TC1 */ 265 __I uint32_t TC2_:1; /*!< bit: 14 TC2 */ 266 __I uint32_t TC3_:1; /*!< bit: 15 TC3 */ 267 __I uint32_t TC4_:1; /*!< bit: 16 TC4 */ 268 __I uint32_t ADC0_:1; /*!< bit: 17 ADC0 */ 269 __I uint32_t Reserved2:2; /*!< bit: 18..19 Reserved */ 270 __I uint32_t AC_:1; /*!< bit: 20 AC */ 271 __I uint32_t Reserved3:1; /*!< bit: 21 Reserved */ 272 __I uint32_t PTC_:1; /*!< bit: 22 PTC */ 273 __I uint32_t CCL_:1; /*!< bit: 23 CCL */ 274 __I uint32_t Reserved4:8; /*!< bit: 24..31 Reserved */ 275 } bit; /*!< Structure used for bit access */ 276 uint32_t reg; /*!< Type used for register access */ 277 } PAC_INTFLAGC_Type; 278 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 279 280 #define PAC_INTFLAGC_OFFSET 0x1C /**< \brief (PAC_INTFLAGC offset) Peripheral interrupt flag status - Bridge C */ 281 #define PAC_INTFLAGC_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGC reset_value) Peripheral interrupt flag status - Bridge C */ 282 283 #define PAC_INTFLAGC_EVSYS_Pos 0 /**< \brief (PAC_INTFLAGC) EVSYS */ 284 #define PAC_INTFLAGC_EVSYS (_U_(0x1) << PAC_INTFLAGC_EVSYS_Pos) 285 #define PAC_INTFLAGC_SERCOM0_Pos 1 /**< \brief (PAC_INTFLAGC) SERCOM0 */ 286 #define PAC_INTFLAGC_SERCOM0 (_U_(0x1) << PAC_INTFLAGC_SERCOM0_Pos) 287 #define PAC_INTFLAGC_SERCOM1_Pos 2 /**< \brief (PAC_INTFLAGC) SERCOM1 */ 288 #define PAC_INTFLAGC_SERCOM1 (_U_(0x1) << PAC_INTFLAGC_SERCOM1_Pos) 289 #define PAC_INTFLAGC_SERCOM2_Pos 3 /**< \brief (PAC_INTFLAGC) SERCOM2 */ 290 #define PAC_INTFLAGC_SERCOM2 (_U_(0x1) << PAC_INTFLAGC_SERCOM2_Pos) 291 #define PAC_INTFLAGC_SERCOM3_Pos 4 /**< \brief (PAC_INTFLAGC) SERCOM3 */ 292 #define PAC_INTFLAGC_SERCOM3 (_U_(0x1) << PAC_INTFLAGC_SERCOM3_Pos) 293 #define PAC_INTFLAGC_TCC0_Pos 9 /**< \brief (PAC_INTFLAGC) TCC0 */ 294 #define PAC_INTFLAGC_TCC0 (_U_(0x1) << PAC_INTFLAGC_TCC0_Pos) 295 #define PAC_INTFLAGC_TCC1_Pos 10 /**< \brief (PAC_INTFLAGC) TCC1 */ 296 #define PAC_INTFLAGC_TCC1 (_U_(0x1) << PAC_INTFLAGC_TCC1_Pos) 297 #define PAC_INTFLAGC_TCC2_Pos 11 /**< \brief (PAC_INTFLAGC) TCC2 */ 298 #define PAC_INTFLAGC_TCC2 (_U_(0x1) << PAC_INTFLAGC_TCC2_Pos) 299 #define PAC_INTFLAGC_TC0_Pos 12 /**< \brief (PAC_INTFLAGC) TC0 */ 300 #define PAC_INTFLAGC_TC0 (_U_(0x1) << PAC_INTFLAGC_TC0_Pos) 301 #define PAC_INTFLAGC_TC1_Pos 13 /**< \brief (PAC_INTFLAGC) TC1 */ 302 #define PAC_INTFLAGC_TC1 (_U_(0x1) << PAC_INTFLAGC_TC1_Pos) 303 #define PAC_INTFLAGC_TC2_Pos 14 /**< \brief (PAC_INTFLAGC) TC2 */ 304 #define PAC_INTFLAGC_TC2 (_U_(0x1) << PAC_INTFLAGC_TC2_Pos) 305 #define PAC_INTFLAGC_TC3_Pos 15 /**< \brief (PAC_INTFLAGC) TC3 */ 306 #define PAC_INTFLAGC_TC3 (_U_(0x1) << PAC_INTFLAGC_TC3_Pos) 307 #define PAC_INTFLAGC_TC4_Pos 16 /**< \brief (PAC_INTFLAGC) TC4 */ 308 #define PAC_INTFLAGC_TC4 (_U_(0x1) << PAC_INTFLAGC_TC4_Pos) 309 #define PAC_INTFLAGC_ADC0_Pos 17 /**< \brief (PAC_INTFLAGC) ADC0 */ 310 #define PAC_INTFLAGC_ADC0 (_U_(0x1) << PAC_INTFLAGC_ADC0_Pos) 311 #define PAC_INTFLAGC_AC_Pos 20 /**< \brief (PAC_INTFLAGC) AC */ 312 #define PAC_INTFLAGC_AC (_U_(0x1) << PAC_INTFLAGC_AC_Pos) 313 #define PAC_INTFLAGC_PTC_Pos 22 /**< \brief (PAC_INTFLAGC) PTC */ 314 #define PAC_INTFLAGC_PTC (_U_(0x1) << PAC_INTFLAGC_PTC_Pos) 315 #define PAC_INTFLAGC_CCL_Pos 23 /**< \brief (PAC_INTFLAGC) CCL */ 316 #define PAC_INTFLAGC_CCL (_U_(0x1) << PAC_INTFLAGC_CCL_Pos) 317 #define PAC_INTFLAGC_MASK _U_(0x00D3FE1F) /**< \brief (PAC_INTFLAGC) MASK Register */ 318 319 /* -------- PAC_STATUSA : (PAC Offset: 0x34) (R/ 32) Peripheral write protection status - Bridge A -------- */ 320 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 321 typedef union { 322 struct { 323 uint32_t PAC_:1; /*!< bit: 0 PAC APB Protect Enable */ 324 uint32_t PM_:1; /*!< bit: 1 PM APB Protect Enable */ 325 uint32_t MCLK_:1; /*!< bit: 2 MCLK APB Protect Enable */ 326 uint32_t RSTC_:1; /*!< bit: 3 RSTC APB Protect Enable */ 327 uint32_t OSCCTRL_:1; /*!< bit: 4 OSCCTRL APB Protect Enable */ 328 uint32_t OSC32KCTRL_:1; /*!< bit: 5 OSC32KCTRL APB Protect Enable */ 329 uint32_t SUPC_:1; /*!< bit: 6 SUPC APB Protect Enable */ 330 uint32_t GCLK_:1; /*!< bit: 7 GCLK APB Protect Enable */ 331 uint32_t WDT_:1; /*!< bit: 8 WDT APB Protect Enable */ 332 uint32_t RTC_:1; /*!< bit: 9 RTC APB Protect Enable */ 333 uint32_t EIC_:1; /*!< bit: 10 EIC APB Protect Enable */ 334 uint32_t FREQM_:1; /*!< bit: 11 FREQM APB Protect Enable */ 335 uint32_t :20; /*!< bit: 12..31 Reserved */ 336 } bit; /*!< Structure used for bit access */ 337 uint32_t reg; /*!< Type used for register access */ 338 } PAC_STATUSA_Type; 339 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 340 341 #define PAC_STATUSA_OFFSET 0x34 /**< \brief (PAC_STATUSA offset) Peripheral write protection status - Bridge A */ 342 #define PAC_STATUSA_RESETVALUE _U_(0x00000000) /**< \brief (PAC_STATUSA reset_value) Peripheral write protection status - Bridge A */ 343 344 #define PAC_STATUSA_PAC_Pos 0 /**< \brief (PAC_STATUSA) PAC APB Protect Enable */ 345 #define PAC_STATUSA_PAC (_U_(0x1) << PAC_STATUSA_PAC_Pos) 346 #define PAC_STATUSA_PM_Pos 1 /**< \brief (PAC_STATUSA) PM APB Protect Enable */ 347 #define PAC_STATUSA_PM (_U_(0x1) << PAC_STATUSA_PM_Pos) 348 #define PAC_STATUSA_MCLK_Pos 2 /**< \brief (PAC_STATUSA) MCLK APB Protect Enable */ 349 #define PAC_STATUSA_MCLK (_U_(0x1) << PAC_STATUSA_MCLK_Pos) 350 #define PAC_STATUSA_RSTC_Pos 3 /**< \brief (PAC_STATUSA) RSTC APB Protect Enable */ 351 #define PAC_STATUSA_RSTC (_U_(0x1) << PAC_STATUSA_RSTC_Pos) 352 #define PAC_STATUSA_OSCCTRL_Pos 4 /**< \brief (PAC_STATUSA) OSCCTRL APB Protect Enable */ 353 #define PAC_STATUSA_OSCCTRL (_U_(0x1) << PAC_STATUSA_OSCCTRL_Pos) 354 #define PAC_STATUSA_OSC32KCTRL_Pos 5 /**< \brief (PAC_STATUSA) OSC32KCTRL APB Protect Enable */ 355 #define PAC_STATUSA_OSC32KCTRL (_U_(0x1) << PAC_STATUSA_OSC32KCTRL_Pos) 356 #define PAC_STATUSA_SUPC_Pos 6 /**< \brief (PAC_STATUSA) SUPC APB Protect Enable */ 357 #define PAC_STATUSA_SUPC (_U_(0x1) << PAC_STATUSA_SUPC_Pos) 358 #define PAC_STATUSA_GCLK_Pos 7 /**< \brief (PAC_STATUSA) GCLK APB Protect Enable */ 359 #define PAC_STATUSA_GCLK (_U_(0x1) << PAC_STATUSA_GCLK_Pos) 360 #define PAC_STATUSA_WDT_Pos 8 /**< \brief (PAC_STATUSA) WDT APB Protect Enable */ 361 #define PAC_STATUSA_WDT (_U_(0x1) << PAC_STATUSA_WDT_Pos) 362 #define PAC_STATUSA_RTC_Pos 9 /**< \brief (PAC_STATUSA) RTC APB Protect Enable */ 363 #define PAC_STATUSA_RTC (_U_(0x1) << PAC_STATUSA_RTC_Pos) 364 #define PAC_STATUSA_EIC_Pos 10 /**< \brief (PAC_STATUSA) EIC APB Protect Enable */ 365 #define PAC_STATUSA_EIC (_U_(0x1) << PAC_STATUSA_EIC_Pos) 366 #define PAC_STATUSA_FREQM_Pos 11 /**< \brief (PAC_STATUSA) FREQM APB Protect Enable */ 367 #define PAC_STATUSA_FREQM (_U_(0x1) << PAC_STATUSA_FREQM_Pos) 368 #define PAC_STATUSA_MASK _U_(0x00000FFF) /**< \brief (PAC_STATUSA) MASK Register */ 369 370 /* -------- PAC_STATUSB : (PAC Offset: 0x38) (R/ 32) Peripheral write protection status - Bridge B -------- */ 371 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 372 typedef union { 373 struct { 374 uint32_t PORT_:1; /*!< bit: 0 PORT APB Protect Enable */ 375 uint32_t DSU_:1; /*!< bit: 1 DSU APB Protect Enable */ 376 uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Protect Enable */ 377 uint32_t DMAC_:1; /*!< bit: 3 DMAC APB Protect Enable */ 378 uint32_t MTB_:1; /*!< bit: 4 MTB APB Protect Enable */ 379 uint32_t HMATRIXHS_:1; /*!< bit: 5 HMATRIXHS APB Protect Enable */ 380 uint32_t :26; /*!< bit: 6..31 Reserved */ 381 } bit; /*!< Structure used for bit access */ 382 uint32_t reg; /*!< Type used for register access */ 383 } PAC_STATUSB_Type; 384 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 385 386 #define PAC_STATUSB_OFFSET 0x38 /**< \brief (PAC_STATUSB offset) Peripheral write protection status - Bridge B */ 387 #define PAC_STATUSB_RESETVALUE _U_(0x00000002) /**< \brief (PAC_STATUSB reset_value) Peripheral write protection status - Bridge B */ 388 389 #define PAC_STATUSB_PORT_Pos 0 /**< \brief (PAC_STATUSB) PORT APB Protect Enable */ 390 #define PAC_STATUSB_PORT (_U_(0x1) << PAC_STATUSB_PORT_Pos) 391 #define PAC_STATUSB_DSU_Pos 1 /**< \brief (PAC_STATUSB) DSU APB Protect Enable */ 392 #define PAC_STATUSB_DSU (_U_(0x1) << PAC_STATUSB_DSU_Pos) 393 #define PAC_STATUSB_NVMCTRL_Pos 2 /**< \brief (PAC_STATUSB) NVMCTRL APB Protect Enable */ 394 #define PAC_STATUSB_NVMCTRL (_U_(0x1) << PAC_STATUSB_NVMCTRL_Pos) 395 #define PAC_STATUSB_DMAC_Pos 3 /**< \brief (PAC_STATUSB) DMAC APB Protect Enable */ 396 #define PAC_STATUSB_DMAC (_U_(0x1) << PAC_STATUSB_DMAC_Pos) 397 #define PAC_STATUSB_MTB_Pos 4 /**< \brief (PAC_STATUSB) MTB APB Protect Enable */ 398 #define PAC_STATUSB_MTB (_U_(0x1) << PAC_STATUSB_MTB_Pos) 399 #define PAC_STATUSB_HMATRIXHS_Pos 5 /**< \brief (PAC_STATUSB) HMATRIXHS APB Protect Enable */ 400 #define PAC_STATUSB_HMATRIXHS (_U_(0x1) << PAC_STATUSB_HMATRIXHS_Pos) 401 #define PAC_STATUSB_MASK _U_(0x0000003F) /**< \brief (PAC_STATUSB) MASK Register */ 402 403 /* -------- PAC_STATUSC : (PAC Offset: 0x3C) (R/ 32) Peripheral write protection status - Bridge C -------- */ 404 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 405 typedef union { 406 struct { 407 uint32_t EVSYS_:1; /*!< bit: 0 EVSYS APB Protect Enable */ 408 uint32_t SERCOM0_:1; /*!< bit: 1 SERCOM0 APB Protect Enable */ 409 uint32_t SERCOM1_:1; /*!< bit: 2 SERCOM1 APB Protect Enable */ 410 uint32_t SERCOM2_:1; /*!< bit: 3 SERCOM2 APB Protect Enable */ 411 uint32_t SERCOM3_:1; /*!< bit: 4 SERCOM3 APB Protect Enable */ 412 uint32_t :4; /*!< bit: 5.. 8 Reserved */ 413 uint32_t TCC0_:1; /*!< bit: 9 TCC0 APB Protect Enable */ 414 uint32_t TCC1_:1; /*!< bit: 10 TCC1 APB Protect Enable */ 415 uint32_t TCC2_:1; /*!< bit: 11 TCC2 APB Protect Enable */ 416 uint32_t TC0_:1; /*!< bit: 12 TC0 APB Protect Enable */ 417 uint32_t TC1_:1; /*!< bit: 13 TC1 APB Protect Enable */ 418 uint32_t TC2_:1; /*!< bit: 14 TC2 APB Protect Enable */ 419 uint32_t TC3_:1; /*!< bit: 15 TC3 APB Protect Enable */ 420 uint32_t TC4_:1; /*!< bit: 16 TC4 APB Protect Enable */ 421 uint32_t ADC0_:1; /*!< bit: 17 ADC0 APB Protect Enable */ 422 uint32_t :2; /*!< bit: 18..19 Reserved */ 423 uint32_t AC_:1; /*!< bit: 20 AC APB Protect Enable */ 424 uint32_t :1; /*!< bit: 21 Reserved */ 425 uint32_t PTC_:1; /*!< bit: 22 PTC APB Protect Enable */ 426 uint32_t CCL_:1; /*!< bit: 23 CCL APB Protect Enable */ 427 uint32_t :8; /*!< bit: 24..31 Reserved */ 428 } bit; /*!< Structure used for bit access */ 429 uint32_t reg; /*!< Type used for register access */ 430 } PAC_STATUSC_Type; 431 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 432 433 #define PAC_STATUSC_OFFSET 0x3C /**< \brief (PAC_STATUSC offset) Peripheral write protection status - Bridge C */ 434 #define PAC_STATUSC_RESETVALUE _U_(0x02000000) /**< \brief (PAC_STATUSC reset_value) Peripheral write protection status - Bridge C */ 435 436 #define PAC_STATUSC_EVSYS_Pos 0 /**< \brief (PAC_STATUSC) EVSYS APB Protect Enable */ 437 #define PAC_STATUSC_EVSYS (_U_(0x1) << PAC_STATUSC_EVSYS_Pos) 438 #define PAC_STATUSC_SERCOM0_Pos 1 /**< \brief (PAC_STATUSC) SERCOM0 APB Protect Enable */ 439 #define PAC_STATUSC_SERCOM0 (_U_(0x1) << PAC_STATUSC_SERCOM0_Pos) 440 #define PAC_STATUSC_SERCOM1_Pos 2 /**< \brief (PAC_STATUSC) SERCOM1 APB Protect Enable */ 441 #define PAC_STATUSC_SERCOM1 (_U_(0x1) << PAC_STATUSC_SERCOM1_Pos) 442 #define PAC_STATUSC_SERCOM2_Pos 3 /**< \brief (PAC_STATUSC) SERCOM2 APB Protect Enable */ 443 #define PAC_STATUSC_SERCOM2 (_U_(0x1) << PAC_STATUSC_SERCOM2_Pos) 444 #define PAC_STATUSC_SERCOM3_Pos 4 /**< \brief (PAC_STATUSC) SERCOM3 APB Protect Enable */ 445 #define PAC_STATUSC_SERCOM3 (_U_(0x1) << PAC_STATUSC_SERCOM3_Pos) 446 #define PAC_STATUSC_TCC0_Pos 9 /**< \brief (PAC_STATUSC) TCC0 APB Protect Enable */ 447 #define PAC_STATUSC_TCC0 (_U_(0x1) << PAC_STATUSC_TCC0_Pos) 448 #define PAC_STATUSC_TCC1_Pos 10 /**< \brief (PAC_STATUSC) TCC1 APB Protect Enable */ 449 #define PAC_STATUSC_TCC1 (_U_(0x1) << PAC_STATUSC_TCC1_Pos) 450 #define PAC_STATUSC_TCC2_Pos 11 /**< \brief (PAC_STATUSC) TCC2 APB Protect Enable */ 451 #define PAC_STATUSC_TCC2 (_U_(0x1) << PAC_STATUSC_TCC2_Pos) 452 #define PAC_STATUSC_TC0_Pos 12 /**< \brief (PAC_STATUSC) TC0 APB Protect Enable */ 453 #define PAC_STATUSC_TC0 (_U_(0x1) << PAC_STATUSC_TC0_Pos) 454 #define PAC_STATUSC_TC1_Pos 13 /**< \brief (PAC_STATUSC) TC1 APB Protect Enable */ 455 #define PAC_STATUSC_TC1 (_U_(0x1) << PAC_STATUSC_TC1_Pos) 456 #define PAC_STATUSC_TC2_Pos 14 /**< \brief (PAC_STATUSC) TC2 APB Protect Enable */ 457 #define PAC_STATUSC_TC2 (_U_(0x1) << PAC_STATUSC_TC2_Pos) 458 #define PAC_STATUSC_TC3_Pos 15 /**< \brief (PAC_STATUSC) TC3 APB Protect Enable */ 459 #define PAC_STATUSC_TC3 (_U_(0x1) << PAC_STATUSC_TC3_Pos) 460 #define PAC_STATUSC_TC4_Pos 16 /**< \brief (PAC_STATUSC) TC4 APB Protect Enable */ 461 #define PAC_STATUSC_TC4 (_U_(0x1) << PAC_STATUSC_TC4_Pos) 462 #define PAC_STATUSC_ADC0_Pos 17 /**< \brief (PAC_STATUSC) ADC0 APB Protect Enable */ 463 #define PAC_STATUSC_ADC0 (_U_(0x1) << PAC_STATUSC_ADC0_Pos) 464 #define PAC_STATUSC_AC_Pos 20 /**< \brief (PAC_STATUSC) AC APB Protect Enable */ 465 #define PAC_STATUSC_AC (_U_(0x1) << PAC_STATUSC_AC_Pos) 466 #define PAC_STATUSC_PTC_Pos 22 /**< \brief (PAC_STATUSC) PTC APB Protect Enable */ 467 #define PAC_STATUSC_PTC (_U_(0x1) << PAC_STATUSC_PTC_Pos) 468 #define PAC_STATUSC_CCL_Pos 23 /**< \brief (PAC_STATUSC) CCL APB Protect Enable */ 469 #define PAC_STATUSC_CCL (_U_(0x1) << PAC_STATUSC_CCL_Pos) 470 #define PAC_STATUSC_MASK _U_(0x00D3FE1F) /**< \brief (PAC_STATUSC) MASK Register */ 471 472 /** \brief PAC hardware registers */ 473 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 474 typedef struct { 475 __IO PAC_WRCTRL_Type WRCTRL; /**< \brief Offset: 0x00 (R/W 32) Write control */ 476 __IO PAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 8) Event control */ 477 RoReg8 Reserved1[0x3]; 478 __IO PAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt enable clear */ 479 __IO PAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt enable set */ 480 RoReg8 Reserved2[0x6]; 481 __IO PAC_INTFLAGAHB_Type INTFLAGAHB; /**< \brief Offset: 0x10 (R/W 32) Bridge interrupt flag status */ 482 __IO PAC_INTFLAGA_Type INTFLAGA; /**< \brief Offset: 0x14 (R/W 32) Peripheral interrupt flag status - Bridge A */ 483 __IO PAC_INTFLAGB_Type INTFLAGB; /**< \brief Offset: 0x18 (R/W 32) Peripheral interrupt flag status - Bridge B */ 484 __IO PAC_INTFLAGC_Type INTFLAGC; /**< \brief Offset: 0x1C (R/W 32) Peripheral interrupt flag status - Bridge C */ 485 RoReg8 Reserved3[0x14]; 486 __I PAC_STATUSA_Type STATUSA; /**< \brief Offset: 0x34 (R/ 32) Peripheral write protection status - Bridge A */ 487 __I PAC_STATUSB_Type STATUSB; /**< \brief Offset: 0x38 (R/ 32) Peripheral write protection status - Bridge B */ 488 __I PAC_STATUSC_Type STATUSC; /**< \brief Offset: 0x3C (R/ 32) Peripheral write protection status - Bridge C */ 489 } Pac; 490 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 491 492 /*@}*/ 493 494 #endif /* _SAMC20_PAC_COMPONENT_ */ 495
